Susmit Biswas

A Pageable Defect Tolerant Nanoscale Memory System

Susmit Biswas, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner

susmit@cs.ucsb.edu

Susmit Biswas

Problem Statement

• In a nanoscale memory system with high manufacturing defect rate,

we aim to find a scheme with low static and dynamic overhead

to identify and avoid the use of defective blocks and

make usable memory in the granularity of 4-KByte size pages.

Susmit Biswas

Is it a significant problem?

• Manufacturing defect– 10 – 30% using Self-assembly

• DNA computing

– Low yield• Yield decreases with block size

Susmit Biswas

Is it a significant problem?

Susmit Biswas

Critical Factors

• Static Overhead– Bad block information

• Dynamic Overhead– Reading and writing latency

Susmit Biswas

ECC Overhead

source: Likharev07

Susmit Biswas

Contribution

• Analytical model

• Defect tolerance technique– ECC, defect map, sparing

• Study on area benefit

• Fixed size block or variable size?

Susmit Biswas

Prior Work

• Error Correcting Codes [Jeffery04] [Ou04]

• Reconfiguration using Defect Map [Tahoori05][Wang06][DeHon05][Likharev-JETC07]

• Built-in-self-Repair (BISR) [Bhavsar-ITC99][Schöber-ITC01][Nicolaidis-JET05]

• Combination of schemes [Sun06] [Likharev-JETC07][Biswas-ICCAD07]

Susmit Biswas

Technique

• Benefit from all– Error Correcting Code (BCH)

• Strength of code

– Defect Map• Level of map

– Spare Block• Amount of sparing

Susmit Biswas

Technique

• Store the defect map in unreliable memory

2

s spare blocks in blocks

2 1 log extra bits per block

B

s s s

Defect Map

Reconfiguration Map

Susmit Biswas

Technique

• Majority voting to provide correctness

101 111 101

MajorityVoter

101

Defect Map

Susmit Biswas

Defect

Map

System Architecture

Spare Map Metadata

Data

Susmit Biswas

Pros and Cons

• Pros– Locality of data and metadata– Low static overhead– High yield– Can be pipelined– Support for virtual memory system

• Cons– 2s + 1 memory block read

• Locality reduces overhead

Susmit Biswas

Results: Storage Efficiency

46.5

26.1

13.2

1.5 4.99E-03 9.85E-12

3.13E-286 0 0

0

10

20

30

40

50

2 5 10

Bit Error Rate (%)

Sto

rag

e E

ffic

ien

cy (

%) Combination

Linear List

Bloom Filter

Susmit Biswas

Results: Static Overhead

3.05

E-03

3.05

E-03

3.05

E-03

1.15

4

6.92

E-01

7.70

E-02

2040 60

0.0001

0.001

0.01

0.1

1

10

100

2 5 10

Bit Defect Rate (%)

Rel

iab

le M

emo

ry S

ize

(%) Combination

Linear List

Bloom filter

Susmit Biswas

Fixed vs. Variable Block

Susmit Biswas

Summary

• Defect tolerance technique– Combination of static and dynamic scheme

• Encoding defect-map with data– Locality of data– Low static overhead– High yield

• Higher yield using variable sized page– Static overhead increases

Susmit Biswas

Future Work

• Efficient BCH module design

• Interconnect reliability by redundancy

• Cache design using unreliable memory

Susmit Biswas

Contact: Susmit BiswasArch Lab, Department of Computer ScienceUniversity of California at Santa Barbarasusmit@cs.ucsb.edu

Online version available at: http://cs.ucsb.edu/~susmit/papers/nanoarch07_nanomemory.pdf

Susmit Biswas

References• [Sun06] F. Sun and T. Zhang. “Two Fault Tolerance Design

Approaches for Hybrid CMOS/Nanodevice Digital Memories”. Nanoarch 2006

• [Wang06] G. Wang, W. Gong, and R. Kastner. “Defect-Tolerant Nanocomputing Using Bloom Filters”. ICCAD 2006

• [DeHon05] A. DeHon and K. K. Likharev. “Hybrid CMOS /Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation”. ICCAD '05

• [Tahoori05] M. B. Tahoori. “A Mapping Algorithm for Defect-Tolerance of Recongurable Nano-Architectures”. ICCAD ’05

Susmit Biswas

References

• [Likharev07] D. Strukov and K. Likharev, “Defect-Tolerant Architectures for Nanoelectric Crossbar Memories”. Journal of Nanoscience and Nanotechnology, January 2007

• [Jeffery04] C. M. Jeffery, A. Basagalar, and R. J. O. Figueiredo, “Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures”. 4th IEEE Conference on Nanotechnology 2004.

• [Ou04] E. Ou and W. Yang, “Fast Error-Correcting Circuits for Fault-Tolerant Memory”, MTDT, pages 8 - 12, 2004.

Susmit Biswas

Reference

• [Ramón05] Ramón Compaňó, “Trends in nanoelectronics”, Journal of Nanotechnology 12, 2001

• [Biswas-ICCAD07] Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner, “Combining Static and Dynamic Defect-Tolerance Techniques for Nanoscale Memory Systems”, to appear in ICCAD 07