Surviving the Heat Wave - DfR Solutions Slides for YouTube/Surv… · DfR Webinar –October 27,...

© 2004 – 2010 9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com

Surviving the Heat Wave –

A presentation on thermally induced failures and reliability

risks created by advancements in electronics technologies

DfR Webinar – October 27, 2016

9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com

Semiconductor Level

EOS

Hot Carrier

Dielectric Breakdown

BTI

Package Level

Bond Wires

Materials

Lead Finish

Circuit Board Level

Solder Coarsening

Laminates

Impact of Potting – Sherlock slide

System – How to get the heat out

Heat Sinks

Vapor Chambers

Immersion Cooling

AGENDA

2

9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com3

o A. We use lots of different materials

o Semiconductors, Ceramics, Metals, Polymers

o B. We bond these different materials together

o Plating, Solder, Adhesive

o C. These materials expand/contract at different rates

Why Do Electronics Fail Under Thermal Cycling?


Why Do Electronics Fail Under Thermal Cycling? (cont.)

o Two different expansion/contraction behaviors

o Because solder is connecting two materials that are

expanding / contracting at different rates (GLOBAL)

o Because solder is expanding / contracting at a different rate

than the material to which it is connected (LOCAL)


o This differential expansion and contraction introduces stress into the solder joint

o This stress causes the solder to deform (aka, elastic and plastic strain)

o The extent of this strain (that is, strain range or strain energy) tells us the lifetime of the solder joint

o The higher the strain, themore the solder joint is damaged,the shorter the lifetime

How Do Electronics Fail Under Thermal Cycling? (cont.)


o Knowing the critical drivers for solder joint fatigue, we can

develop predictive models and design rules

Drivers for Solder Joint Thermo-Mechanical Failures

CTE of Board

Elastic Modulus (Compliance) of Board

CTE of Component

Elastic Modulus (Compliance) of Component

Length of Component

Volume of Solder

Thickness of Solder

Solder Fatigue Properties


Drivers for Solder Joint Thermo-Mechanical Failures

To understand the types of loads that an assembly might go through in its

intended life we should consider the various temperature cycles in the

field. Field conditions can be different for different usage and

applications even for the same product. Every industry segment has a

characteristic service life and usage conditions as shown in the following table.


o Induced by poor fabrication, thermal cycling, high temperature exposure and moisture penetration

o Affects all layers and materials in contact

o Die, attach, lead frame, die layers, passivation, bond pads

o Localized stress concentration leads to premature delamination

o Materials must be able to withstand the thermomechanical stresses created between the differences in the CTE of each material

Delamination

http://www.isu.edu.tw


Delamination of topmost metal layer induced by

adhesive fillet and defect from die singulation

Delamination of a Stacked Die


o Complex integrated circuits – CPU/GPU, Memories, FPGA, SoC, SiP, MCM

o Multiple tiers, new interconnect structures

o Silicon, itself, is aging at lithography nodes <50nm

o Failure rate driven by intrinsic failure rate of semiconductor and degradation of the 1st and 2nd-level interconnects

o Need to assess computational loading conditions

o Need to determine temperature rise under loading conditions

o Ceramic capacitors on the SoC substrate are also a significant risk due to voltage and temperature

o Necessary to identify capacitor temperature class

Complex Integrated Circuits


o The models employed in these assessments are from DfR’s Sherlock’s Semiconductor Wearout Technology library for sub-micron planar and FinFET devices

o Models used are Hot Carrier Injection (HCI) and Dielectric Breakdown (DB) degradation models for both voltage and temperature effects.

o It is assumed that the effects of electromigration (EM) and Bias Temperature Instability (BTI) are mitigated by robust DVT

Semiconductor Lifetime Modeling

HCI BTIGOB


o Degradation caused by Hot Carrier Effects (HCE) can be inferred by its effect on device performance, or event of catastrophic failure of an active region

o Hot carriers can initiate the dielectric breakdown process

o Parametric shifts will take place in threshold voltage, leakage current and capacitance

o Its effect on device performance may cause latch-up, timing and propagation delays

o Any material subjected to an excessively strong electric field will conduct electricity and may fail due to Dielectric Breakdown (DB). Electrons contained in the valence band of the dielectric escape into the conduction band by quantum tunneling mechanisms. o Accumulation of breakdown sites will result in performance degradation and

eventual failure of the transistor within the device

o A conducting path may even be created between the channel and the gate metallization

Degradation Mechanisms


o Degradation caused by Bias Temperature Instability can be

inferred by its effect on device performance

o Because this mechanism affects the molecular bonds at the Si-SiO2

interface, failure analysis images are not available

o Bias Temperature Instability causes an increase in the threshold

voltage required to switch a MOSFET

o BTI is driven by smaller electric fields than Hot Carrier Effects, which

makes it a more significant threat at smaller technology nodes where

increased electric fields are used in conjunction with smaller gate lengths

Degradation Mechanisms (Cont’d)


o Intel Puma 6 SoC

o 22nm FinFET lithography process

o Intel Atom processor

o Customer had specified a 10 year product life in their

application

Case Study – 22nm SoC


o The plot is the failure rate associated with a single SoC

semiconductor component using voltage and temperature

information gathered for the 22nm Intel Atom processor

o Calculated failure rate of 1814 FIT

o Assumes a continuous operation at full load, 24x7

Case Study – 22nm SoC (Cont’d)

0%

1%

2%

3%

4%

5%

6%

7%

0 1 2 3 4 5 6 7 8 9 10

Pro

bab

ility

of

Failu

re

Time (years)

Cumulative Probability of Failure


o Thermoelectric transport in small-scale semiconductors is largely asymmetric

o All devices experience self-heating through sub-microsecond voltage pulses

o Average energy (kinetic + chemical potential) of electrons increases with temperature

o Phenomenon is worse in FinFETs than in traditional planar geometries

o More pronounced in 2.5D and 3D devices due to deficiencies in routing of heat transport layers

o When silicon is heated, the electrical carriers normally present in the device are supplemented by thermally generated carriers

o Energy transport by generation, transport and recombination of minority carriers can become very significant and overcome convective energy transport by majority carriers in the opposite direction

Electrical Overstress


o In a typical EOS event, the extent of the damage can be used to draw

conclusions about the energy transfer pulse

o A few nanoseconds to a microsecond

causing melting of thin metallization

and polysilicon

o > 50 microseconds to 100 microseconds

causes junction punch through

o > 100 microseconds causes melted metal

o The damage seen in this cross section of a diode is consistent with slow

transient damage. The device was subjected to a long exposure of

high temperature during its off-time.

Electrical Overstress (Cont’d)

Die melted and re-

solidified in this area


o Ceramic capacitors with very thin dielectric layers can experience limited lifetime when subjected to elevated temperatures and voltage

o As general guidance, DfR Solutions evaluates all ceramic capacitors in a design with a rated voltage less than 6.3V

o Rated voltage typically has a direct correlation to dielectric thickness

o DfR Solutions uses an Arrhenius-based analytical solution that extrapolates time to failure from industry test conditions

Ceramic Capacitor Wearout

electrodes

Dielectric

x22


o The lifetime curves above are from reference sheets for

Murata GRM033R60J225ME47D (0201/X5R/6.3V/2.2uF)

and GRM155R60J106ME11D (0402/X5R/6.3V/10uF)

Example of a Limited Lifetime Ceramic Capacitor

0

1

2

3

4

5

6

7

8

9

10

60 62 64 66 68 70

Life

tim

e (yrs

) at 80%

Rate

d

Voltage

Capacitor Temperature (oC)


o Several concerns with lifetime curves provided by Murata

o Does not provide a voltage acceleration factor. Cannot extrapolate from 5VDC to 4.2VDC

o Does not define the failure rate for ‘useful lifetime’. Useful lifetime could be a very low probability of failure (<1%) or mean time to failure (MTTF), which is 63% failure

o Not clear why two different products (0201/2.2uF/6.3V and 0402/22uF/6.3V) have same life curve

o Because of uncertainty regarding definition of ‘useful lifetime’, DfR Solutions recommends that the goal should be a ‘useful lifetime’ of at least 2X product lifetime

Limited Lifetime Ceramic Capacitors (Cont’d)


o Bond wires fail from excessive intermetallic formation

o Exposure to elevated temperature from environment and

localized heating from current density

Bond Wires

L Levine, Update on High Volume Copper Ball Bonding


o Issue #1: Thermocompression

bonding at 350C

o Formation of brittle AuAl2

(purple plague)

o Issue #2: High Temperature Post-

Bonding Processes

o Curing, Lid Sealing, Baking

o Diffusion of gold into Au5Al2

o Formation of Kirkendall voiding

Bond Wires - Gold

Tummala, Microelectronics Packaging Handbook


o Copper-aluminum forms intermetallics at a much slower rate

o Most common activation energy of 1.26 – 1.47 eV

o Micron reported 0.63 eV

o Different intermetallics form at

different temperatures

o Can a 150C/200C test be

extrapolated to 85C?

o Fracture mode with pure Cu

changed from bulk Cu to

interfacial failure

Bond Wires - Copper

HJ Kim, IEEE CPT, 2003

L. England, ECTC, 2007

C. Breach, The Great Debate: Copper vs. Gold

Ball Bonding


Die stacking technologies have been demonstrated up to 9

high stacks

Most stack ups are limited to 4 die

Driven by test, yield and logistic limitations

Stacked die packaging comes in three flavors

All driven by need to provide ledges for wire bonding

Pyramid or ‘cake’

configuration

Smaller die are

placed on larger die

o Stacking traps heat

(higher junction temperatures)

o Increase in upset events, shorter lifetimes

Stacked Die Configuration


Design change: More silicon, less plastic

Increases mismatch in coefficient of thermal expansion

(CTE)

Solder Wearout

BOARD LEVEL ASSEMBLY AND RELIABILITY

CONSIDERATIONS FOR QFN TYPE PACKAGES,

Ahmer Syed and WonJoon Kang, Amkor Technology.


Hotter devices

Increases change in temperature (T)

Solder Wearout (cont.)

0

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

0 50 100 150 200

Change in Temperature (oC)

Ch

ara

cte

ris

tic

Lif

e (

Cy

cle

s t

o F

ail

ure

)

tf = Tn

n = 2 (SnPb)

n = 2.3 (SnNiCu)

n = 2.7 (SnAgCu)


o There are two fundamental forces that drive grains in polycrystalline materials to grow. Grains coarsen because grain boundaries are areas of high potential energy. This is the primary driving force in single-phase materials. During grain coarsening, as grains grow larger, the total grain boundary area decreases, which, in turn lowers the free energy of the system.

o Particles with smaller size tend to combine into a larger particle one with lower total interfacial energy. Grain growth is driven by the local boundary curvature and the presence of triple junctions, which remain in equilibrium and act as anchors to grain boundary mobility. Grain boundary mobility is highly dependent upon grain orientations across the boundary.

Solder Phase Coarsening

27


Solder Phase Coarsening

28

From the original solder joint (left) the grains will grow as the solder

joint is stressed. The growing grains will cause micro-voids to appear on the

grain boundaries. The micro-voids will connect with each other to create

micro-cracks and eventually macro-cracks. If the load is distributed evenly

across the joint this will happen everywhere at the same time. In BGA balls

this will happen in an entire layer of the bulk solder. If the load is not even then

the grain growth and micro cracks are formed in the stress concentration and

the micro-crack is advancing along a crack path.


Solder Joint Coarsening Due to Thermal Stresses

29


o The speed of crack formation and propagation in the solder can be

modeled. One way to predict the solder fatigue is to use a

modification of the Engelmaier model. The Engelmaier model is a

semi-empirical analytical approach that calculates fatigue using

energy method.

o The following equation gives the calculation to determine the strain

range (Δg) where C is a correction factor (function of activation

energy, temperature and dwell time), Δα is the CTE difference, hs

is solder joint height (defaults to 0.1016 mm or 5 mils), ΔT is the

temperature cycle and LD is the maximum diagonal distance between

solder joints

Speed of Crack Formation

30


o Next we use the following equation to determine the

shear force applied to the solder joint. The equation

considers the PCB and bond pad stiffness and

both shear and axial loads. It also considers the

lead stiffness for leaded components. Where F is

the shear force LD is length, E is elastic modulus, A is

the area, h is solder thickness, G is shear modulus, and

a is edge length of bond pad and the subscripts

are: [1] for component, [2] for board, [s] for

solder joint, [c] for bond pad, and [b] for board


31


o Using the strain range and shear force we can calculate the

strain energy dissipated by the solder joint using the following

equation

Equation: Strain energy dissipated in the solder joint

o and calculate the number of cycles-to-failure (Nf), using energy

based fatigue models for SAC developed by Ahmer Syed

(Amkor technology) or the model for SnPb

o Equation: Syed model for SAC solder fatigue model

o Equation: Energy based fatigue models for SnPb solder fatigue


32


o PCB laminates (and prepregs) are

fabricated with a variety of glass

styles

o Problem: All datasheet properties are

for laminate with 7628 glass style

o Most laminate (and prepreg) in

complex PCBs have a low volume

fraction of glass

(i.e., 1080 or 106)

Glass

Style

Resin

Volume Content

Fiber

Volume

Content

1027 0.86 0.14

1037 0.86 0.14

106 0.84 0.16

1067 0.84 0.16

1035 0.83 0.17

1078 0.82 0.18

1080 0.79 0.21

2313 0.74 0.26

2116 0.71 0.29

3313 0.71 0.29

3070 0.68 0.32

1647 0.66 0.34

1651 0.66 0.34

2165 0.66 0.34

2157 0.66 0.34

7628 0.64 0.36

Printed Circuit Board Analysis – Glass Style


PCB Parameters Affecting Thermal Performance

A realistic target for board CTE is between 15 and 17 ppm/°C.

Most laminate suppliers only provide CTE values for the in-plane

direction as shown in the following table.

These values are typical for a low resin content laminate (46%-50%

resin content by weight, 7628 glass style) however the most popular

laminates have much higher resin contents. Higher resin content

corresponds to a higher CTE and lower modulus.


x

y

& Solving for Em

Consider Positive value of Em as solution.

Printed Circuit Board Analysis - Calculations, Example Modulus


o Modulus decreases as resin content increases

o CTE increases as resin content increases

o Copper content plays a significant role

o These values can be now used to predict

solder joint fatigue

Printed Circuit Board Analysis – Effect of Glass Style


Plated Through Hole Fatigue• PTH fatigue is the circumferential cracking of the copper plating that forms the PTH wall

• It is driven by differential expansion between the copper plating (~17 ppm) and the out-of-plane CTE of the printed board (~70 ppm)

• Validated industry failure model available - IPC-TR-579

• When a PCB experiences thermal cycling the expansion/contraction in the z-direction is much

higher than that in the x-y plane. The glass fibers constrain the board in the x-y plane but not

through the thickness. As a result, a great deal of stress can be built up in the copper via barrels

resulting in eventual cracking near the center of the barrel as shown in the cross section photos

below.


Plated Through Hole FatigueWhile there is a tendency for plating to crack towards the center of the barrel it is

possible for cracks to appear in other places in the PTH. Several cross sections of

cracks in PTH are shown in the following figure. One of the difficult aspects

of finding a PTH crack is that the failure is detected when the board is at

high temperature. When the board is then tested for faults at room temperature

the fault is not found because the board has shrunk and the two sides of the crack

are touching.


Assessment of IPC-TR-579

o Based on round-robin testing of 200,000 PTHs

o Performed between 1986 to 1988

o Hole diameters (250 µm to 500 µm)

o Board thicknesses (0.75 mm to 2.25 mm)

o Wall thickness (20 µm and 32 µm)

o Advantages

o Analytical (calculation straightforward)

o Validated through testing

o Disadvantages

o No ownership

o Validation data is ~16 years old

o Unable to assess complex geometries (PTH spacing, PTH pads)

o Complex geometries tend to extend lifetime

o Difficult to assess effect of multiple temperature cycles

o Can be performed using Miner’s Rule

o Simplified assumptions (linear stress-strain above yield point)

o How does one determine the quality index in the design phase?


o It is impossible to eliminate PTH fatigue completely. Better reliability can be

achieved if the board laminate and PTH plating material have a close CTE value

for the out-of-plane direction. The board glass style and resin can be modified to

some degree. Increasing the glass content can help reduce the CTE mismatch but it

will be harder to drill the holes into the board. The plating material ductility will also

affect the life of the PTH. The predicted numbers of cycles to failure are plotted in

the figure below for different glass styles. The plating material, plating thickness,

temperature profile and drill diameters are kept the same

Assessment of IPC-TR-579


o Questions to ask yourself.

o Does the potting compound perform a thermal function?

o Does it need to protect from aggressive chemicals or

moisture?

o Does it need to protect from shock loads?

o Will the potting see high temperatures during

manufacturing?

o Are issues such as outgassing, cryogenic operation, or

medical compatibility involved?

o Ask the right questions during the design cycle to keep

problems to a minimum.

Why Use Potting Materials?


o One of the most common issues with selecting the right

potting material is understanding your thermal

requirements

o Typically selected based on min and max temperatures

o Maybe OK, but does not take ramp times and dwells

into consideration

o Failing to consider dwell and ramp times often can

lead to over specifying the materials

o For example, if you select a material with a 200C

continuous rating, it would be able to withstand a short

burst at 250C during a soldering operation

o Ignoring the short dwell time could result in selecting a

much more expensive material than you actually

require.

Know Your Thermal Situation


Tg Behavior

o Near the glass transition temperature (Tg), CTE changes more rapidly than modulus

o Changes in the CTE in polymers tend to be driven by changes in the free volume

o Changes in modulus tend to be driven by increases in translational / rotational movement of the polymer chains

o Increases in CTE tend to initiate before decreases in modulus because lower levels of energy (temperature) are required to increase free volume compared to increases in movement along the polymer chains

Polymer Science and Technology, Chapter 4: Thermal Transitions in Polymers,

Robert Oboigbaotor Ebewele, CRC Press, 2000

0.01

0.10

1.00

10.00

35 45 55 65 75 85 95 105

Temperature (oC)

Sto

rag

e M

od

ulu

s (

MP

a)

0

20

40

60

80

100

120

140

CT

E (p

pm

/ oC)

Storage Modulus

CTE

High stresses generated due to CTE increase before modulus decrease


Modeling Potting is Fastest Way to Analyze

5 mm thick coverage over entire board

5 mm coverage over the top of

2 inductors only


o Optimal design of a heatsink, meeting program targets for

cost, weight, size, and performance, is one of the more

challenging activities within most electronics engineering teams.

o In a case study, DfR worked to optimize an extruded aluminum

heat sink for an IGBT module in a low-cost, high-volume design.

Reliability requirements (10-year life), harsh environments

(vibration, elevated temperature), limited ability to perform

maintenance (consumer household), and cost constraints

eliminated forced air cooling as a practical solution. The focus

was instead to optimize the design within the dimensional

constraints provided by the end -user.

Heat Sinks


o The goal of this analysis was to reduce the thermistor temperature during operation

such that the module achieved stable operation at 60°C and shutdown at or above

65°C. To achieve this goal, the case temperature of the IGBT must be decreased.

This increase in the operating margin was achieved by modifying the relevant

heatsink parameters.

o Parameters analyzed: Base Thickness, Height, Width, length, Fin Thickness, Fin Pitch,

and Number of Fins

o Heats source (<1oC impact), Heatsink Fin Height (.25” decreased temp by 5.5oC, .5”

increase in height reduced temp by 10oC, anodization emissivity increased from .4

to .9 (3-5oC impact)

Heat Sinks

Heatsink Temp at 20C


o Difficult thermal challenges often arise with handheld electronics

o It may become apparent that the tried and true methods of increasing thermal efficiency – solid base, fin & fan – just aren’t sufficient

o Thermal solutions for these applications must be rugged, accurate, biocompatible and reliable

o Vapor Chambers

o Vacuum sealed copper chamber lined with a wick structure and a hermetically sealed working fluid to create a phase change inside the chamber with resulting 3D high thermal performance

o Considered a planar version of heat pipes – producing a natural isothermalization which reduces formation of hot spots and gradients

Vapor Chambers


Vapor Chambers (Cont’d)

https://www.mdtmag.com


o Not a new concept!

o Direct liquid immersion cooling

has been used within IBM for over

20 years to cool high powered

chips on multi-chip substrates

during electrical testing prior to

final module assembly.

o Early supercomputers relied on

liquid cooling technologies

o Cray 2 supercomputer

Liquid Immersion Cooling


Liquid Immersion Cooling


THANKSGreg Caswell and Ed Wyrwas

[email protected]

301-640-5825

mailto:[email protected]

Surviving the Heat Wave - DfR Solutions Slides for YouTube/Surv… · DfR Webinar –October 27,...

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