Surge Current Testing and Derating for Solid Tantalum

Capacitors

Alexander Teverovsky Parts, Packaging, and Assembly Technologies Office, Code

562, GSFC/ASRC Federal Space and Defense Alexander.A.Teverovsky@nasa.gov

NASA Electronic Parts and Packaging (NEPP) Program

Outline

2

Surge current testing (SCT). Mechanism of failures. History of current derating.

MIL-PRF-55635 requirements. Specifics of SCT.

Effective resistance of the circuit, Reff. Correlation between Reff and equivalent

series resistance (ESR). Effect of ESR on VBR.

Specified and real ESR values. Derating of surge currents. Conclusion.

Do we need limiting resistors in series with tantalum capacitors?

ESA Sept. 2013

Mechanisms of Surge Current Failures

3

Sustained scintillation breakdown. If current is not limited, self-healing does not have time to develop.

Electrical oscillations in circuits with high inductance.

Local overheating of the cathode. Mechanical damage to tantalum

pentoxide dielectric caused by the impact of MnO2 crystals.

Stress-induced-generation of electron traps caused by electromagnetic forces developed by high currents.

All models require high currents that correspond to high rates of voltage increase.

Ta MnO2

Ignition due to exothermic reaction in tantalum capacitors. Prymak 2006.

ESA Sept. 2013

Effect of dV/dt on Breakdown Voltage

4

Scintillation breakdown voltage, VBRscint (dV/dt ~ 1 to 5 V/sec) is always greater than the surge current breakdown voltage, VBRSCT (dV/dt ~ 105 to 106 V/sec)

The rate of voltage increase changes charges and electrical field at the interface.

A theory explains decreasing VBR with a rate of voltage increase. A resistor in series with a capacitor reduces dV/dt and failures.

Ta MnO2

40

60

80

100

120

140

160

40 60 80 100 120 140 160

VBR

_3SC

T, V

VBR_scint, V

Effect of dV/dt on VBR for 50V capacitors

ESA Sept. 2013

Fast voltage raise Slow voltage raise

Accumulation of electrons on traps at the MnO2-Ta2O5

interface with time increases the barrier, the level of electron injection, and the probability of

avalanching.

Requirements for Limiting Resistors

5

History of requirements for circuit resistance (Rac): In the 1960s: 3 Ω per each volt of operating voltage. By the 1980s: 1 Ω per each volt. From the 1990s: 0.1 Ω per volt or 1 ohm, whichever is greater. Manufacturers consider surge current failures as the major

reason for voltage derating. Do we need derating of currents in addition to voltage? The limit for acceptable surge currents is set by the SCT

conditions: the current during applications should not exceed the current during testing: Iappl.< Itest

Improvements in reliability and the need to increase the efficiency of power supply systems resulted in reduction of Rac.

Can we allow circuit designs without Rac? Need a closer look at how the Itest is specified.

“use as tested”

ESA Sept. 2013

MIL-PRF 55365 Requirements

6

SCT per MIL-PRF-55365H: Nc = 4 surge cycles. Energy storage capacitor, CB = 20×CDUT

Test voltage: VR Charge time, tch, and discharge time, tdisch, ≥ 1sec. Total DC resistance of the circuit, RC, including the wiring, fixturing, and output

impedance of the power supply should not exceed Rc = 1 Ω. Measurements after SCT: DCL, C, DF (still no requirements for ESR) Itest ≥ VR/(Rtc + ESRspec), where resistance of the test circuit, Rtc= 1 Ω. Failure condition: I = 1A after 1ms for C ≤ 330uF; 10ms for C ≤ 3.3mF, and

100ms for C > 3.3 mF. Before 12/1/2012: Nc = 10. tdisch = tch = 4 sec. Rc ≤ 1.2 Ohms. CB ≥ 50 mF. Itest was not addressed.

ESA Sept. 2013

New specification recognizes the role of ESR as a limiting factor for surge currents. Rated surge current:

No specifics on Itest verification.

1+=

spec

Rsurge ESR

VI

Verification of SCT Conditions

7

Two methods of SCT verification: measurements of voltage after

some time of spike initiation; measurements of a current

spike amplitude.

The rate of voltage increase is critical for SCT. A high current spike is a byproduct of the fast voltage raise,

rather than the major cause of failure. Even minor variations (~0.1 Ω) of Rc affect dV/dt and results

of SCT. The amplitude of the current spike is the most adequate

characteristic of the SCT conditions.

0

0.2

0.4

0.6

0.8

1

0

1

2

3

4

5

0 100 200 300 400

V/Vo

I/Vo,

A/V

time, uS

I_0.1 OhmI_0.4 OhmI_0.7 OhmV_0.1 OhmV_0.4 OhmV_0.7 Ohm

SCT simulations for 220 µF capacitor at Lc= 400 nH, ESR = 0.1Ω Rc-var

ESA Sept. 2013

Factors Affecting SCT Results

8

Rc includes resistance of wires and contacts.

The length of wires affects inductance. Type of switch. The rate of voltage increase in

case of FET.

SCT test conditions should be optimized by maximizing Isp.

-30

0

30

60

90

120

150

0 10 20 30 40 50

curr

ent,

A

time, us

0 kOhm

0.8 kOhm

1.6 kOhm

0

2

4

6

8

10

12

-15 0 15 30 45 60 75 90

gate

vol

tage

, V

time, us

0 kOhm1.6K Ohm.8 k ohm

Effect of resistance to FET gate on Vg and Isp for 47uF 20V capacitors

ESA Sept. 2013

-30

0

30

60

90

120

150

0 10 20 30 40 50

curr

ent,

A

time, us

4" wires

12" wires

24" wires

-30

0

30

60

90

120

150

0 10 20 30 40 50

curr

ent,

A

time, us

110 nH

400 nH

900 nH

47uF 20V experiment

47uF R=0.25Ohm L-var. Simulation.

Effect of wire length

Effective Resistance of the Circuit

9

Isp increases linearly with voltage allowing for calculations of the effective resistance of the circuit, Reff.

Reff corresponds to the impedance of the circuit and includes Rc, ESR, resistance of contacts, and circuit inductance, Lc.

47uF 10V

10uF 16V

220uF 6V

0

40

80

120

160

200

0 20 40 60 80

curr

ent s

pike

, A

voltage, V

0

40

80

120

160

200

0 15 30 45 60 75 90

curr

ent,

A

time, us

6V 8V10V 12V14V 16V18V 20V

220uF 6V

-40

0

40

80

120

160

200

240

-10 0 10 20 30 40 50 60 70

curr

ent,

A

time, us

20V 24V28V 32V36V

47uF 20V Test anomalies, e.g. poor contacts, can be revealed by Isp(V) curves

good contacts

poor contacts0

50

100

150

200

250

300

0 5 10 15 20 25 30 35

curr

ent s

pike

, A

voltage, V

3SCT 220uF 6V

after adjustment

ESA Sept. 2013

Effect of Reff on Breakdown Voltage

10

Different lot date codes of 22 µF 35V capacitors.

Effect of temperature Parts with larger ESR had greater VBR.

Temperature decreases ESR resulting in lower VBR.

An increase in Reff by ~0.1Ω results in increase of VBR ~10%.

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

0.24

0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34

ESR

, Ohm

Reff, Ohm

TBJD226K035LRLB0024

DC0513 DC0516

DC0824 DC0836

30

40

50

60

70

80

90

0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34

VBR

_SC

T, V

Reff, Ohm

TBJD226K035LRLB0024

DC0513 DC0516

DC0824 DC0836

0

0.1

0.2

0.3

0.4

0

20

40

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80

-60 -40 -20 0 20 40 60 80 100

Reff,

Ohm

VBR_

SCT,

V

temperature, deg.C

47uF 20V VBR220uF 6V VBR47uF 20V Reff220uF 6V Reff

ESA Sept. 2013

Correlation between ESR and Reff

11

Effective resistancde during SCT and ESR

R, Ohmcu

mulat

ive pr

obab

ility,

%0.10 0.800.24 0.38 0.52 0.661

5

10

50

99ESR\TM8A106K016CBZNormal-2PRRX SRM MED FMF=16/S=0

Data PointsProbability Line

ESR\TM8T476K010CBZNormal-2PRRX SRM MED FMF=16/S=0

Data PointsProbability Line

Reff\TM8A106K016CBZNormal-2PRRX SRM MED FMF=16/S=0

Data PointsProbability Line

Reff\TM8T476K010CBZNormal-2PRRX SRM MED FMF=15/S=0

Data PointsProbability Line

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Ref

f, O

hm

ESR, Ohm

20 lots of HV capacitors

y = 0.6118x + 0.1963

0.3

0.35

0.4

0.45

0.2 0.25 0.3 0.35 0.4

Ref

f, O

hm

ESR, Ohm

47uF 10V uchips

Effective resistance of SCT:

Optimized set-up: Rc is in the range from 0.1 Ω to 0.2 Ω.

ESRRIVR c

sp

Reff +≈=

ESA Sept. 2013

Application vs. Test Conditions

12

Typical application conditions: No limiting resistors, minimal inductance. No contact resistance. Resistance of the circuit, Rac, is minimal.

The current is limited mostly by ESR. Surge Current Test conditions: Contact resistance of fixtures. Limiting resistor (up to 1 Ω). Relatively long wires and inductance. No requirements for Itest verification.

Parts with poor contacts in the fixture can pass the testing.

There might be a substantial difference in inrush currents between application and test conditions.

Example: • A 15µF 10V CWR06 capacitor with specified ESR=2.5Ω and real ESR = 0.5Ω is used in a 5V line. • During application the part can experience a spike: Iappl = 5/0.5 = 10 A. • During the testing it will be verified to the current: Itest ≥ VR/(Rtc + ESRspec)

Itest =10/(1+2.5) = 2.8 A

ESA Sept. 2013

Real and Specified Values of ESR

13

ESR distribution can be described by a normal function. The distributions are rather tight: STD ~ 30% to 50% of ESRavr. Different lots of the same part type might have different ESR. Only a maximum value of ESR is limited. Real ESR values

might not correlate with the limit. Navr = ESRlimit/ESRavr CWR06 have Navr ~7, CWR29 ~2.

ESR, Ohm

cumu

lative

prob

abilit

y, %

0.08 0.280.12 0.16 0.20 0.241

5

10

50

99

LDC 0516

LDC 0824

LDC 0836

LDC 0513

22uF 35V ESRmax=0.4Ohm

CWR06 CWR11 CWR29

Navr 6.92 2.72 2.04 STD 2.64 0.83 1.02

Lots QTY 14 20 23

0

2

4

6

8

10

0 2 4 6 8 10 12 14 16 18

ESR

_spe

c/ES

R_a

vr

ESR_spec, Ohm

CWR06-09

CWR11

CWR29

ESA Sept. 2013

Surge Current Derating

14

SCT requirements (rated current): , Rtest = 1 Ω.

During applications, possible current spike: , derating α = Va /VR , Rac – additional resistance

Derating Criterion: Ia < β×Itest , where β ≤ 1 is the current derating coefficient.

Substitution gives: At low voltages capacitors can tolerate much higher current

spikes, so there is no need in derating currents on the top of voltage derating =>

Rac is not necessary if Ips_max < Itest at a clamping time τ ≤ 10 us.

Unless SCT is done at the optimized conditions, or additional resistance is necessary.

spectest

Rtest ESRR

VI+

=

ESRRVI

ac

Ra +

×=

α

ESRESRRR spectestac −×+×> αα

ESRESRRR spectestac −×+×>βα

βα

ESA Sept. 2013 testspec RESR

ESR+

<α

When Additional Resistor is Necessary?

15

If SCT is carried out at the optimized conditions (Rtc< 0.5 Ω, and Isp is verified at real ESR values), then

If Rac < 0.05 Ω, no resistance required.

ESRRR tcac ×−+×> )1(αα

At the existing SCT requirements per M55365, additional resistance is necessary in most cases.

If SCT is carried out at Rtc = Reff – ESR < 0.5 Ω, the additional resistor is not necessary if ( ) tcRESR ×>×− αα1

ESA Sept. 2013

0

0.1

0.2

0.3

0.4

0.5

0.6

1.E-2 1.E-1 1.E+0

Rac

, Ohm

ESR, OhmRt=1.2, a=0.5 Rt=1.2, a=0.3 Rt=1, a=0.5Rt=1, a=0.3 Rt=0.5, a=0.5 Rt=0.5, a=0.3Rt=0.2, a=0.5 Rt=0.2, a=0.3

Required series resistance at different ESR, Rtc and α

Algorithm for Surge Current Derating

16

8/ Suggestions for further actions: - experimental data for ESR, - calculate actual Rtc = Reff – ESR, - SCT at greater voltage levels, …

spectc

Rtest ESRR

VI+

=1/ , Rtc = 1 Ω

2/ In case of using power supplies (PS) with current compliance, make sure that the clamping time τ ≤ 10us. IPS = Imax PS.

5/ SCT should be carried out at a min. wire length, no limiting resistors, and Isp should be verified to be greater than Isp > VR/(0.5 + ESR)

7/ Actual derating: αd = Vapp/VR

ESA Sept. 2013

3/ Estimate ESR as ESRspec/N, where N=7, 3, 2 for CWR06/11/29 respectively. 4/ Reff = VR/Isp, where Isp is the surge current spike amplitude.

6/ Standard voltage derating: α = 0.5

Conclusion

17

Tantalum capacitors manufactured per MIL-PRF-55365 might fail because the surge current test conditions during manufacturing are less stressful compared to application conditions.

Measurements of current spike amplitudes during SCT allow for estimations of the effective resistance of the test circuit, Reff, and should be used to assure that the parts are properly stressed during the testing. Acceptable test conditions can be determined as Reff ≤ 0.5 + ESR.

An algorithm and procedures necessary for selection of limiting resistors to derate surge currents or for making a decision to use tantalum capacitors without additional resistors are suggested.

ESA Sept. 2013