SuperH RISC engine Family - BIS-EL

©2009. Renesas Technology Corp., All rights reserved.

Renesas Microcomputers General Presentation

SuperH RISC engine Family

Safety • Service • Satisfaction-Renesas Microcomputer-

4/28/2009 Rev.16.00

1

©2009. Renesas Technology Corp., All rights reserved.Renesas Microcomputers General PresentationSuperH RISC engine Family

SuperH RISC engine Roadmap

2

SH-4

SH-3,SH3-DSP

SH-2(SH2-DSP)

SH-1

SH-4A

SH-2ASH2A-FPU

ASSP

to 200 MHz

SH7720/21 SH7727 SH7729RSH7705 SH7706 SH7709S

SH7700 series

SH7710/12/13

SH7780 series

SH7780 SH7781 SH7785SH7763 SH7764 SH7722SH7723 SH7730

to 600 MHz

Dual Core

SH7786

SH7010series

to 20 MHz

28.7 MHz

SH7060series60 MHz

SH2-DSP SH7606series100 MHz

50 MHz

80 MHz

SH7147series80 MHz

SH7137series

SH7146series80 MHz

SH7125series50 MHz

SH7260series

to 200 MHz

SH7200series

to 200 MHz

160 MHz

Dual Core

SH7265200 MHz

SH7205200 MHz

SH7280series100 MHz

SH7243series100 MHz

SuperH forDigital Audio

SH-Ether

SuperH forCar Information

System,SH-Navi

SH-Mobile

SuperH withUSB

SH7750 seriesSH7750RSH7750S

SH7751RSH7751

SH7760

to 240 MHz

SH7080series

SH7020series

SH7030series20 MHz

20 MHz

SH7040series

SH7144series50 MHz

SH7047series50 MHz

SH7046series

SH7210series


SuperH Instruction SystemSH-1/2SH-3/4SH-4A

15 0

15 0

031

SH2-DSPSH3-DSP 1615SH-2A

3

68 instructionsMMU control

instruction, etc.

94 instructionsFloating-point

instruction (single/double precision), etc.

103 instructionsFloating-point

instruction,cache operation instruction, etc.

160 instructionsMMU control

instruction, etc.instruction for DSP

154 instructions for DSP

56 instructions62 instructions

32-bit multiply-and-accumulation, etc.

91 instructionsEnhanced shift, operation, bit

manipulation, and division instructions

112 instructionsFloating-point instruction (single/double precision)


Background of SH-2A Development- Demands of Automotive, Industrial, and Consumer Appliances Fields -

- High-speed, highly-functional operations dueto complex compound control

- High-speed control of mechanical sections suchas external I/O module

- Improved real-time performance

• Increased ROM capacity- Reduction of program code size• Better cycle performance- Instruction execution time (CPI)

improvement• High-speed response and improved

real-time performance- Shorter interrupt response time

4


Features of the SH-2A

5

Improved execution cycle performance- Harvard architecture (prevention of IF-MA contention)- 5-stage pipeline deferred⋅ Prevention of increase in branch penalty and data hazard

- Superscalar architecture(two instructions are issued simultaneously)

- New instructions (32-bit + 16-bit instructions) added

Improved interrupt response time- Introduction of register banks

Reduced program code size- New instructions (32-bit + 16-bit instructions) addedImproved code efficiency together with optimization by compiler


SH-2A: Most Powerful Real-Time Control Engine

6

252010

1SH-2

at 50 MHzSH-2A

at 200 MHz

Relative value

1/25

SH-2at 50 MHz

SH-2Aat 200 MHz

6

1

Relative value

6 ×

SH-2 SH-2A

1.00.5

Relative value

75%

1. Fastest interrupt response time- Shortest interrupt response time:

6 clock cycles (30 ns at 200 MHz)- On-chip memory for saving register contents

2. Significantly-improved performance- 1.5 times the performance of the SH-2

at the same operation frequency- Adoption of superscaler architecture

(two instructions are simultaneously executed)

3. Greatly-improved code efficiency- 1.3 times the code efficiency of the SH-2

Efficiency in code size: 75% comparedto the SH-2

- Addition of new instructions and improved compiler performance


SH-2A Pipeline Operation

In the SH-2A, an instructions is executed by five-stage pipeline as shown below.Two instruction are simultaneously issued by superscalar operation.

IF MA WBID EX

IF ID EX

IF MA WBID EX

IF ID EX

IF MA WBID EX

IF ID EX

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

Time

IF: Instruction fetchID: DecodeEX: ExecutionMA: Memory accessWB: Write back

7


SH-2A Interrupt Latency Improvement (1)

R0

•

R14

SP

GBR

MACH

MACL

PR

SR

PC

R0

•

R14

SP

GBR

MACH

MACL

PR

SR

PC

CPU Internal RAM

All registers

32 bits

(1) SH-2

SR

PC

CPU Internal RAM

SR and PC

32 bits

R0

•

R14

SP

GBR

MACH

MACL

PR

SR

PC

Reg

iste

r ban

ks

(2) SH-2A15banks

8

The SH-2A has memory for saving register contents according to interrupt priority level,which enables automatic and collective saving of register contents when an interrupt occurs.


SH-2A Interrupt Latency Improvement (2)

InterruptExceptionprocessing

SavingRegistercontents

Saving register contentsby software processing

9 37 Cycles

InterruptExceptionprocessing

Saving registercontents

Saving register contents by hardwareprocessing: Automatic and fast

6 37 Cycles1

1 2 3 4 5 6

(1) PR, GBR, MCL(2) R12, R13, R14, MACH

(3) R8, R9, R10, R11(4) R4, R5, R6, R7

(5) R0, R1, R2, R3

SH-2:

SH-2A:

9


Controller Type

SH7020 SeriesSH7030 SeriesSH7040 SeriesSH7010 SeriesSH7060 SeriesSH7144 Series



10

©2009. Renesas Technology Corp., All rights reserved.Renesas Microcomputers General PresentationSuperH RISC engine Family11

Roadmap of the SuperH Controllers

Under developmentIn planning

SH703020/12.5 MHz,112/120 pins

SH702020/12.5 MHz,

100 pins

SH704016.7/28.7 MHz,

112/120/144 pins

20/28.7 MHz,100/112 pins

SH7010

50 MHz,100 pins

SH7047

50 MHz,80 pins

SH7046

50 MHz,112/144 pins

SH7144SH714780/64 MHz,

100 pins

SH714680 MHz

80/100 pins

SH712550 MHz,

48/64 pins

SH713780 MHz,

80/100 pins

80 MHz, 100/112/144/176 pins

SH7080

SH-2

CAN

CAN

CAN

to 200 MHz, 176 to 240 pins

SH7210160 MHz,144 pins

100 MHz,144/176 pins

SH7280 USB, CAN

SH7243100 MHz,100 pins

200 MHz, 272 pins

Dual-core

SH-2A, SH2A-FPU

SH-1

Nextgeneration

ROM-less

On-chip ROM

SH7260

SH7200

SH7265

SH7205

SH7606100 MHz, 176 pins

60 MHz, 176 pins

SH7060

SH2-DSP


Features of the SH7280 SeriesProducts in the SH7280 Series of flash-memory-equipped microcontrollersfeature the new SH-2A CPU core and operate at a maximum frequency of100 MHz.As well as A/D converters with a 12-bit resolution and timers for motor control,on-chip peripheral modules include a USB interface.

• High performance SH-2A core- Higher CPU performance with 200 MIPS@100 MHz- Faster response to interrupts → On-chip register bank• On-chip large-capacity flash memory: 512 KB/768 KB/1 MB• Wide range of power-supply voltage: 3.0 to 5.5 V*

• Abundant peripheral modules- On-chip timers for advanced three-phase motors: MTU2 and MTU2S- High-speed A/D converters with 12-bit resolution: 1 μs/ch- Full-speed USB 2.0: 1• On-chip debugging functionality- Full ICE and on-chip debugger

Main target applications• Digital audio and visual devices, office equipment,

card readers, general-purpose inverters, AC servomotors, numerically controlled machines, sequencers

* Analog power: AVcc = 4.5 to 5.5 VUSB power: DrVcc = 3.0 to 3.6 V


Functional Overview of the SH7280 Series• CPU core

- SH-2A: SuperH RISC engine- 32-bit multiplier (32 bits × 32 bits = 64 bits)- Harvard architecture • Operating frequency

- CPU clock: 100 MHz (max.)- Bus clock: 50 MHz (max.)- Peripheral clock: 50 MHz (max.)• Power-supply voltage

- 3.0 to 5.5 V(AVcc = 4.5 to 5.5 V, DrVcc = 3.0 to 3.6 V)

• On-chip memory- Flash memory: 512 KB/768 KB/1 MB- RAM: 24 KB/32 KB• External memory interfaces

- SRAM, byte-selectable SRAM, burst ROM, SDRAM- External bus width· SH7285: 8 bits/16 bits· SH7286: 8 bits/16 bits/32 bits

- External memory space is divisible into up to 8 areas(maximum 64-MB each).

• Packages- SH7285: LQFP-144 (20 mm × 20 mm, 0.5-mm pitch)- SH7286: LQFP-176 (20 mm × 20 mm, 0.4-mm pitch),

LQFP-176 (24 mm × 24 mm, 0.5-mm pitch)• On-chip function- 16-bit multi-function PWM timers:

6 (MTU2), 3 (MTU2S)- Port output enable (POE) - 16-bit peripheral timers: 2- Watchdog timer: 1- I2C bus interface: 1- SSU interface: 1

• On-chip function- USB interface: 1, 2.0 Full Speed Function- RCAN-ET: 1 (only for the SH7286)- High-speed SCI: 1

(16-stage transmission/reception FiFo)- SCI: 4

(dual use as UART or clock synchronous)- Pins used for external interrupts: 9- DMA controller: 8 ch; DTC also included- 12-bit A/D converters· SH7285: 4 ch (with three S/H circuits) × 2 units· SH7286: 4 ch (with three S/H circuits) × 3 units

- 8-bit D/A converters: 2 ch (only for the SH7286)• On-chip debugging function

- H-UDI/AUD- User break controller (UBC)

D/A converter*

CMTDMAC/DTC

MTU2

I2C/SSU

MTU2S

Bus

inte

rface

SH-2A100 MHz

RAM

Port

SCI/SCIF

12-bit A/Dconverter

USB

Flash ROM

Block Diagram of the SH7280

32-bit multiplier

WDT

CAN*

*: SH7286 only.


Features of the SH7243 SeriesProducts in the SH7243 Series of flash-memory-equippedmicrocontrollers will feature the new SH-2A CPU core and operateat a maximum frequency of 100 MHz.The SH7243 Series is derived from the SH7280 Series by trimming functionality(less on-chip ROM and RAM, USB, SSU, and other modules removed)for an initialproduct in a 100-pin package.

• High performance with SH-2A core- Higher CPU performance with 200 MIPS@100 MHz- Faster response to interrupts → On-chip register bank• Wide range of power-supply voltage: 3.0 to 5.5 V*

• Abundant peripheral modules- On-chip timers for advanced three-phase motors: MTU2 and MTU2S- High-speed A/D converters with 12-bit resolution: 1 μs/ch• On-chip debugging functionality- Full ICE and on-chip debugger

Main target applications• AC servomotors, numerically controlled machines, sequencer,

general-purpose inverters, robots, measuring equipment

* Analog power: AVcc = 4.5 to 5.5 V


Functional Overview of the SH7243 Series• CPU core- SH-2A: SuperH RISC engine- 32-bit multiplier (32 bits × 32 bits = 64 bits)- Harvard architecture• Operating frequency- CPU clock: 100 MHz (max.)- Bus clock: 50 MHz (max.)- Peripheral clock: 50 MHz (max.)• Power-supply voltage- 3.0 to 5.5 V (AVcc = 4.5 to 5.5 V) • On-chip memory- Flash memory: 128 KB/256 KB- RAM: 8 KB/12 KB• External memory interfaces- SRAM, byte-selectable SRAM, burst ROM, SDRAM- External bus width: selectable as 8 bits/16 bits• Package- LQFP-100 (14 mm × 14 mm, 0.5-mm pitch)• On-chip peripheral function- 16-bit multi-function PWM timers:

6 (MTU2), 3 (MTU2S)- Port output enable (POE)- 16-bit cycle timers: 2- Watchdog timer: 1

• On-chip peripheral function- High-speed SCI: 1

(16-stage transmission/reception FiFo)- SCI: 2

(dual use as UART or clock synchronous)- Pins used for external interrupts: 9- DMA controller: 8 ch; DTC also included- 12-bit A/D converters:

4 ch (with three S/H circuits) × 2 units• On-chip debugging function- H-UDI/AUD- User break controller (UBC)

WDT

CMT

DMAC/DTC

32-bitmultiplier

MTU2

MTU2S

Bus

inte

rface

SH-2A100 MHz

RAM

Port

SCI/SCIF

12-bit A/Dconverter

Flash ROM



Features of the SH7210 SeriesProducts in the SH7210 Series of flash-memory-equipped microcontrollers featurethe new SH-2A CPU core and operate at a maximum frequency of 160 MHz.On-chip peripheral modules include timers for motor control, A/D converters witha 12-bit resolution, etc.

• High performance SH-2A core- Higher CPU performance with 320 MIPS@160 MHz- Faster response to interrupts → On-chip register bank• On-chip large-capacity flash memory: 512 KB/384 KB• Abundant peripheral modules- On-chip timers for advanced three-phase motors: MTU2 and MTU2S- High-speed A/D converters with 12-bit resolution: 1.25 μs/ch- SDRAM interface• On-chip debugging functionality- Full ICE and on-chip debugger

Main target applications• AC servomotors, inverters, vending machines, surveillance cameras,

video printers, bar-code readers, printers, color photocopiers


Functional Overview of the SH7210 Series• CPU core

- SH-2A: SuperH RISC engine- 32-bit multiplier (32 bits × 32 bits = 64 bits)- Harvard architecture• Operating frequency


- 1.5 V ±0.1 V (CPU), 3.3 V ±0.3 V (I/O),5.0 V ±0.5 V (A/D converter)

• On-chip memory- Flash memory: 512 KB/384 KB- RAM: 32 KB/24 KB• External memory interfaces

- SRAM, byte-selectable SRAM, burst ROM, SDRAM- External bus width: 8 bits/16 bits• Package

- LQFP2020-144 (0.5-mm pitch)• On-chip peripheral function

- 16-bit multi-function PWM timers:6 (MTU2), 3 (MTU2S)

- Port output enable (POE) - 16-bit cycle timers: 2- Watchdog timer: 1- I2C bus interface: 1- High-speed SCI: 4

(16-stage transmission/reception FiFo)- DMA controller: 8 ch- 12-bit A/D converters: 8 ch (with three S/H circuits)

• On-chip peripheral function- 8-bit D/A converters: 2 ch• On-chip debugging function

- H-UDI/AUD- User break controller (UBC)

Part no.

R5F72115D160FPV -40 to +85 °C

Range of operating temperature


SH-2A

BSCSDRAM,SRAM,

burst ROM,MPX

DMAC: 8 ch

RAM:2 KB/24 KB

Flash memory:512 KB/384 KB

WDT

SCIF: 4

MTU2:16 bits × 6

IIC: I2C bus

8-bit D/A converter: 2

12-bit A/Dconverter: 8

CMT:16 bits × 2

MTU2S:16 bits × 3

I/O Ports


Functions and Features of SH7206

• High-performance SH-2A CPU core- Equivalent to SH-4 → 480 MIPS@200 MHz- Faster response to interrupts → internal register banks• Low-power consumption and high performance: 2560 MIP software• Large-capacity RAM: 128-KB/200-MHz access• On-chip data/instruction separation cache: Total 16 KB• Abundant bus interface- SDRAM I/F, PCMCIA- Burst ROM I/F, etc.• On-chip peripheral functions for real time control- Multi-functional timer: 16 bits × 11 ch, motor control- Various analog input/output: 10-bit A/D converter, 8-bit D/A converter

18


Overview of the SH7206• CPU core

- SH-2A (SuperH RISC engine)- 32-bit on-chip multiplier (32 bits × 32 bits → 64 bits)- Harvard architecture• Operating frequency

- CPU clock: 200 MHz (max.)- Bus clock: 66 MHz (max.)- Peripheral clock: 33 MHz (max.)- Clock dedicated for the MTU2S: 100 MHz (max.)• Power supply voltage

- 3.0 to 3.6 V and 1.15 to 1.35 V (analog power supply: 3.0 to 3.6 V)

• Internal memory- 32 KB RAM × 4 mat: a total of 128 KB- Instruction cache: 8 KB- Operand cache: 8 KB• External memory interface

- SRAM, byte selectable SRAM, multiplexed I/O, PCMCIA, burst ROM

- External bus width: selectable from 8 bits, 16 bits, or 32 bits- External memory spaces can be divided into 9 spaces

(576 Mbytes at maximum)• Package

- LQFP-176 (24 mm square, 0.5 mm pitch) • Internal functions

- Multifunctional 16-bit PWM timer: 6 (MTU2) and 3 (MTU2S)- Port output enable (POE): 9

• Internal functions- 16-bit cycle timer: 2- Watchdog timer (WDT): 1- I2C bus interface: 1 - DMA controller: 8 ch- 10-bit A/D converter: 4 ch × 2- 8-bit D/A converter: 2 ch- SCIF: 4 (16-stage built-in FIFO

for transmit and receive operations)- I/O port: 81- External interrupt pin: 17 - JTAG interface

Bus

inte

rface

Por

t

128-KBRAM

SCIF

10-bit A/D converter

WDT

CMT

DMAC

32-bitmultiplier

MTU2

I2C

Cachememory

MTU2S8-bit D/A converter

SH-2A:200 MHz

19


CPU @ 200 MHz

Example: AC Servo System ConfigurationUsing SH7206

SH7206

8, 16, 32 bits* External bus @ 66 MHz

I2C bus

SCIbus

A/Dinput

A/Dinput

PWMoutput

PWMoutput

For various control

Sub-MCUsetc.

EEPROMetc.

128-KBRAM

Abundant Communications

functions• On-chip 4-ch SCIFand on-chip 1-ch I2C

Motor control• Possible to control

2 types of motors!

ROMASICUSB

Directly connectable to various memory types• High-speed execution is enabled by storing

the boot program to the Internal RAM!!*: When expanding to 32 bits,one type of motor can be controlled.

• Achieves maximum CPU performance by having programs resident in internal RAM.• On-chip cache improves the performance of externally installed programs.• Abundant functions such as three-phase PWM output timeaaar, 10-bit A/D converter,

and more.

20


SH7201 Functions and Features

• Incorporates high-performance SH-2A core- CPU performance equivalent to the SH-4 → 288 MIPS@120 MHz- High-speed response to interrupt processing → On-chip register bank• On-chip double-precision FPU- Realizes signal processing performance higher than the DSP- Enhances software development by the FPU(eliminates digit alignment processing)

• Abundant interfaces such as CAN and I2C-bus• Rich set of bus interface- SDRAM interface- Burst ROM interface, etc.• Internal peripheral functions for realtime control- Many on-chip timers: 16 bits × 11 ch, motor control is possible- Ample analog input/output 10-bit A/D converter, 8-bit D/A converter

21


Overview of the SH7201

JTAG

SH-2A120 MHz

Instruction cache8 KB

BSCROM,

SRAM/SDRAMFPU

8-bittimer

DMAC

CAN

Data cache8 KB

A/D10-bit8 ch

D/A8-bit2 ch

RTC

RAM32 KB

INTCinterruptcontroller

SCIF

MTU2UBC

I/O116 bits +8 bits

I2C

• CPU core- SH-2A (SuperH RISC engine) FPU- 32-bit multiplier (32 bits × 32 bits → 64 bits)- Harvard architecture• Operating frequency


- 3.0 to 3.6 V• Internal memory

- RAM: 32 KB- Instruction cache: 8 KB- Operand cache: 8 KB• External memory interface

- SRAM, SDRAM interface- External bus width is selectable from 8, 16 bits or 32 bits- External memory spaces can be divided into 7 areas

(64 MB max.)• Internal functions

- Multi-functional 16-bit PWM timer: 6 (MTU2)- 8-bit timer (waveform output): 2- Watchdog timer: 1- CAN interface: 2 (2.0A, 2.0B)- I2C bus interface: 3- DMA controller: 8 ch (includes 4 ch for external requests)- 10-bit A/D converter: 4 ch × 2- 8-bit D/A converter: 2 ch- SCIF: 8

(16-stage transmit/receive FIFO included)- I/O port: I/O: 116, Input: 8- External interrupt pin: 17- JTAG interface

• Package- 176-pin LQFP (24-mm square, 0.5-mm pitch)

Functions newly added to the SH7206Functions changed from the SH7206

WDT

22


Industrial Measurement Device Application Example Using the SH7201

System controllerSH7201 Microcomputer

SH-2A CPU120 MHz

FPU

DMAC

MTU2

10-bitA/D converter

8-bitD/A converter

BSC memory interface

U-RAM32 KB

CAN

Serial interface

I2C

Transmit/receive

Display microcomputer

DMAC I2C

16 bits

Monitor output

Network

Various controlInstructions from host

(1) On-chip MTU2 suitable for motor control(PWM waveform output, 2-phase encoderfunction, etc.)

(2) On-chip CAN controller suitable for interfacebetween industrial devices

(3) On-chip FPU enables highly accurate currentcontrol

6-phase PWM waveform required for inverter control

23


Functions and Features of the SH7203

• High-performance SH-2A core- Performance comparable to an SH-4 CPU → 480 MIPS@200 MHz- Highly responsive interrupt processing → incorporation of register banks• Double-precision FPU- Better signal-processing performance than a DSP- Simpler development of software using FPU (matching digits is not required.)• On-chip module for USB v.2.0 standard high-speed Host and Function

operation- Large amount of data transferable at high-speed- Switching between Host and Function• Liquid crystal display controller handles displays up to WVGA size(800 × 480 pixels)

• Abundant communications interface functions- I2C, CAN, serial with FIFO, SPI-compliant serial, serial for sound• Multifunctional timer for motor control, A/D converter, D/A converter


Overview of the SH7203

SH-2A200 MHz

BSCROM, SRAM,

SDRAM, PCMCIA

MTU2:5

A/D10-bit:8 ch

FPU

DMAC8 ch

16-bit CMT:

2

SSI:4

URAM64 KB16 KB

USB2.0H/F

(HS):1

SSU:2

CAN:2

I2C:4

FastSCIF:

4

WDT

INTC

Instructioncache:

8 KB

D/A8-bit:2 ch

RTC

Data cache:8 KB

LCDC

NANDFlash

I/F

• CPU core- SH-2A (SuperH RISC engine) FPU

• Operating frequency- CPU clock: 200 MHz (max.)- Bus clock: 66 MHz (max.)

• Power-supply voltage: dual power supply- Internal 1.2 V/external 3.3 V

• Internal memory- URAM: 64 KB- RAM with standby retention: 16 KB- Cache: I = 8 KB, D = 8 KB

• External memory interface- SRAM, SDRAM, PCMCIA interface- External data-bus width selectable as 8, 16, or 32 bits- External memory space can be divided into seven areas


- 16-bit multifunctional timer: 5 (MTU2)- 16-bit timer (CMT): 2- Watch dong timer: 1- CAN interfaces: 2 (2.0A, 2.0B)- I2C bus interfaces: 4- DMA controller: 8 ch

(includes 4 ch. that can be activated by external requests)- 10-bit A/D converter: 8 ch- SCIF: 4 (16-stage transmit/receive FIFO included)- SSI: 4- SSU: 2- USB2.0 (high speed): Host or Function selectable- NAND flash I/F- LCD controller- I/O ports- JTAG interface

• Package- 240-pin QFP

* Specifications are subject to change.

25

: Function added to the SH7201


SH7261 Functions and Featuresfor Digital Audio Systems

• Using the SH-2A CPU (120 MHz performance) and FPU, decoding and encoding WMA, AAC, MP3, ATRAC3, etc.can be achieved by software

- Eliminates external decoder chip- Multi-decoding is enabled

• Ripping an external USB memory or HDD player is possible- CPU encoding- Support for various encoder is in examination

• On-chip CD-ROM decoder- External components can be eliminated

• Various on-chip interfaces such as CAN and audio interface (SSI)

26


SH7261 Functional Outline

JTAG

SH-2A100/120 MHz

Instructioncache8 KB

BSCROM,

SRAM/SDRAMFPU

8-bittimer

DMAC

CAN

Data cache8 KB

A/D10-bit8 ch

D/A8-bit2 ch

RTC

RAM32 KB

INTCinterrupt controller

SCIF

MTU2UBC

I/O116 bits+ 8 bits

I2C

CD-ROMdecoder

WDT SSI

• CPU core- SH-2A (SuperH RISC engine)- On-chip 32-bit multiplier (32 bits × 32 bits → 64 bits)• Operating frequency


- 3.0 to 3.6 V• On-chip memory

- RAM: 32 KB- Instruction cache: 8 KB- Operand cache: 8 KB• External memory interface

- SRAM, SDRAM interface- External bus width selectable from 8, 16, or 32 bits- External memory space can be divided into 7

(64 Mbytes max.) areas• Internal functions

- Multifunctional 16-bit PWM timer: 6 (MTU2)- 8-bit timer (waveform output): 2 ch- Watchdog timer: 1 - CAN interface: 2 (2.0A, 2.0B)- I2C bus interface: 3 - DMA controller: 8 ch

(includes 4 ch which external request is enabled) - 10-bit A/D converter: 4 ch × 2- 8-bit D/A converter: 2 ch- SCIF: 8 (16-stage transmit/receive FIFO included)- SSI: 2- CD-ROM decoder (Mode0/1/2/2Form1/2Form2)- I/O port: I/O: 116, Input: 8 - External interrupt pin: 17 - JTAG interface

• Package- 176-pin LQFP (24 mm square, 0.5-mm pitch)

27

Functions added to the SH7206Functions changed from the SH7206


Configuration Example of Digital HomeAudio System Using the SH7261Supporting USB Memory

(1) Music playback from USB deviceUncompress and playback compressed audio sound withinUSB memory or portable players

(2) CD ripping to USB device Compress music CD data, and store them in USB memoryor portable audio players

28

16 bits

Key input

Playing…

AudioD/A converter

Remote controller

BSC memory interface

SDRAM Flash memory

I2C

A/D converter

Audio codec library*WMA/MP3/AAC

SSI

SCIFCD-ROMdecoder

U-RAM32 KB

SH-2ACPU/FPU

100/120 MHz SSI

INT

Tuner

USB HostM66596

Hi-Speed host1-to-1 communications

LCD panel

CD-DSP/Servo

System controllerSH7261 microcomputer

CD driverPortable audio player

USB memory

Multi-codec bysoftware


SH7263 Functions and Features for Digital Audio Systems• High-performance SH-2A core- Performance comparable to an SH-4 CPU → 480 MIPS@200 MHz- Highly responsive interrupt processing → incorporation of register banks• Double-precision FPU- Better signal-processing performance than a DSP- Decoding and encoding of WMA, AAC, and MP3 realizable in software • On-chip module for USB v.2.0 standard high-speed Host and

Function operation- Large amount of data transferable at high speeds- Switching between Host and Function• Liquid crystal display controller handles displays up to WVGA size

(800 × 480 pixels)• Abundant communications interface functions- I2C, CAN, serial with FIFO, SPI-compliant serial, serial for sound• Internal functions for digital audio- CD-ROM decoder, sampling-rate converter, SD-card interface


Functional Overview of the SH7263

USB2.0 HOST/FUNC

(HS): 1

FastSCIF:

4SSI:

4SSU:

2CAN:

2

BSCROM, SRAM,

SDRAM, PCMCIAINTCDMAC

8 ch SRCPIO

I2C:4

16-bitCMT:

2WDTMTU2:

5NANDFlash

I/FRTC

SH-2A200 MHz

Instructioncache: 8 KB

FPUURAM64 KB16 KB

Data cache:8 KB

A/D10-bit8 ch

D/A8-bit2 ch

LCDCCD-ROMDEC

SD cardIFIE-Bus

* Specifications are subject to change.

• CPU core- SH-2A (SuperH RISC engine) FPU • Operating frequency

- CPU clock: 200 MHz (max.)- Bus clock: 66 MHz (max.)• Power-supply voltage: dual power supply

- Internal 1.2 V/external 3.3 V• Internal memory

- URAM: 64 KB- RAM with standby retention: 16 KB- Cache: I = 8 KB, D = 8 KB• External memory interfaces

- SRAM, SDRAM, PCMCIA interface- External data-bus width selectable as 8, 16, or 32 bits- External memory space can be divided into seven areas


- 16-bit multifunctional timers: 5 ch (MTU2)- 16-bit timers (CMT): 2- Watchdog timer:1- CAN interfaces: 2 (2.0A, 2.0B)- I2C bus interfaces: 4- DMA controller: 8 ch

(includes 4 ch that can be activated by external requests)- 10-bit A/D converter: 8 ch- SCIF: 4

(16-stage transmit/receive FIFO included)- SSI: 4- SSU: 2- SRC (sampling-rate converter)- USB2.0 (high-speed): Host or Function selectable- SD-card interface- NAND flash I/F- CD-ROM decoder

: Function added to the SH7261

: Function changed from the SH7261

• Internal functions- LCD controller (equivalent to that of the SH7760)- I/O ports- JTAG interface• Package

- 240-pin QFP


Using the SH7263 for a USB-Supporting Audio System

CD driver

16 bits

Hi-Speed Host for 1-to-1 communications

HDD

Flash(option)

Audio codec library(*)WMA/MP3/AAC

SSI

SH7263

SSI

I2C

A/D converter

INT

LCDCURAM64 KB

BSC Memory interface

USB 2.0

PCMCIA

DMACNAND I/F

SRC

CD-ROMdecoder

USB memory

SH-2A CPU/FPU 200 MHz

Multi-codec insoftware

CD-DSP/servo

NAND Flash

Tuner

Portable audio player

Playing ... LCD panel

Flash memorySDRAM

(1) Music playback from USB devicesDecompress and playback compressed audio data from USB memory or portable players.

(2) Ripping CDs to USB devicesCompress music CD data and store them in USB memory or portable players.

Key input

Remote controller

Audio D/A converter


• AMP: Asymmetric multiprocessor• Application of the multi-layer bus (MLB), designed with an emphasis on low latency

- Bus configuration with four independent layers:two for CPU use as bus masters, two for the DMAC

- Two CPUs to act as the two bus masters- The MLB has been widely used as a standard bus for SoC (system on chip).• On-chip SH2A-FPU (200 MHz) CPU cores suit embedded control systems.

- The FPUs handle signal processing and calculations for industrial, music,and other applications.

- Concomitant usage of URAM draws out greater effective performance.- Register banks enable faster response.• Configurations that include internal flash memory will be available.• Dual ITRON and debuggers• We are working towards even better performance and power consumption.

Summary of the SH2A-DUAL Platform


• Applications- Equipment and devices for industrial and

general uses• Abundant peripheral functional modules1. Supports various storage interfaces

(ATAPI/NAND flash/USB 2.0)2. On-chip 2D engine

(input of digital video, output of analog RGB)3. On-chip multi-functional timers:

Facility for motor control• Package:

272-pin BGA (ball-grid array)

SH-2A(200 MHz)

SH-2A(200 MHz)

BSCROM, SRAM,

SDRAM

MTU2:5

10-bitA/D

Converter:8

RTC

INTC

WDT

SSU:2

SSI:6

NANDFlash IF

2DGraphics

DMAC

FPU

FPU

ATAPI

USB 2.0HOST(HS)

2 ports/FUNC(HS)1 port

URAM:32 KB

Instructioncache:8 KB


CAN:2

SCIF:6

I2C

URAM:64 KB

Datacache:8 KB

Datacache:8 KB



• Applications- Digital on-board equipment for vehicles,

including car audio and car navigation systems • Functional modules added to those of

the SH72051. SD-card interface2. IE Bus3. Handling of compressed music files (AAC format)

Encoding accelerator• Support for vehicle product quality

(-40 to 85°C)• Package

272-pin BGA (Ball Grid Array)

SH-2A(200 MHz)

SH-2A(200 MHz)

BSCROM, SRAM,

SDRAM

MTU2: 5

10-bitA/D

Converter:8

RTC

INTC

WDT

SSU: 2

SSI: 6

NANDFlash IF

2DGraphics

DMAC

FPU

FPU

AAC Enc.

SD Card IF

URAM32 KB



SCIF: 6

USB 2.0 HOST (HS): 2 ports/

FUNC (HS): 1 port

ATAPI

IE Bus

I2C

URAM64 KB

Datacache:8 KB

Datacache:8 KB

CAN: 2


: Difference from the SH7205


Example of an Application forMusic Playback and CD Encoding

ATA

AACEncoder

I2C

SD IF

Video IIS (SSI)

USB 2.0(HS)

A/D

2D Graphics

SH-2ACPU/FPU200 MHz

SH-2ACPU/FPU200 MHz

Bus I/FROM, SRAM,

SDRAM

Flash

SDRAM

TFTMonitorQVGA

A2DIC

USBConnector

USBConnector

Hub

Hub

2 Ports USB

Touch panel

RGB RGB

D/A

- A CD drives are connectable to the PC-ATA driveror the SSI interface (4 × read CD-ROM drive).

- I/O functions for video allow for display of external video.- Two USB 2.0 (HS) ports are available

Decompression and playback of compressed audio data:the SH-2A CPU is capable of decompressingand playing back compressed audio data in several formats(MP3/WMA/AAC codecs are available).Compression of audio data:The SH-2A CPU can handle software compression (MP3/AAC)or use the AAC encoder.


Features of the SH7262 and SH7264

• On-chip large-capacity SRAM (1 MB/640 KB)- Reducing requirements for external SDRAM facilitates

reducing numbers of parts and system costs.- For display sizes up to WQVGA, the SRAM is capable of

holding dual frame buffers.- External SDRAM is still connectable.• USB2.0 and graphics functions- Products incorporate a USB controller for High-Speed

USB2.0 and a display controller that handles video input.• Abundant peripheral functions- Inclusion of on-chip peripheral functions such as the FPU,

CAN, MTU2, and PWM timers for motor control makes the products suitable for industrial applications.

- Flash memory (NOR, NAND, serial flash memory etc.) is connectable.

SH7262/SH7264


UnderDevelopment

• CPU: SH2A-FPU (SuperH RISC engine)• Frequency: CPU 144 MHz/External bus 72 MHz (max.)• Power: Internal 1.2 V/External 3.3 V• Internal Memory

- URAM: 64 KB- SRAM: 1 MB (includes standby RAM: 32 KB)

640 KB (includes standby RAM: 320 KB)- Cache: Instruction = 8 KB, data = 8 KB• External memory interface

- SRAM, NOR-type flash memory, SDRAM, PCMCIA- Bus width: 8 or 16 bits, memory space: 64 MB (max.)• Peripheral modules

- DMAC: 16 ch- USB host/function: 1 - Multi function timer (MTU2): 5- 16-bit timer (CMT): 2- 10-bit PWM timer: 16- Watchdog timer (WDT): 1- Real-time clock (RTC): 1- I2C bus interface: 3- Serial communication interface with FIFO (SCIF): 8- Renesas serial peripheral interface (RSPI): 2- Clock synchronous serial interface with FIFO (SIOF): 1- RCAN: 2 (option)- Video display controller (VDC3):

D-RGB (up to WQVGA)Video IN (BT. 656)

- NAND-type flash memory controller- Serial sound interface (SSI): 4 - SPDIF: 1- Sample rate converter (SRC): 2- CD-ROM decoder- 10 bit A/D converter: 4 ch- Decompression unit

Outline of the SH7262 Specifications• Peripheral modules

- SD card host interface (SDHI): 1- IEBus: 1 (option)• Package- 176-pin QFP

SH2A-FPU:144 MHz

BSCSRAM, NOR,

SDRAM, PCMCIA

I2C: 3

SCIF: 8

10-bit A/DConverter:

4 ch

CMT:2

SSI (I2S):4

SPDIF:1

MTU2:5

RSPI:2

Inst.cache:8 KB

Datacache:8 KB

URAM:64 KB

SRAM:1 MB

or640 KB

DMAC:16 ch INTC PIO SRC: 2

10 bitPWM:

16WDT RTC

NANDflashI/F

CAN:2

SIOF:1

USB2.0host

/func.

SDHI

IEBus:1

CD-ROMdecoder

VDC3Video In (BT.656)

Display cnt. (D-RGB)

De-Compress

Unit

SH7262

Functionality added to that of the current product (SH7263)Option


UnderDevelopment

• CPU: SH2A-FPU (SuperH RISC engine)• Frequency: CPU 144 MHz/external bus 72 MHz (max.)• Power: Internal 1.2 V/external 3.3 V• Internal Memory

- URAM: 64 KB- SRAM: 1 MB (includes standby RAM: 32 KB)

640 KB (includes standby RAM: 320 KB)- Cache: Instruction = 8 KB, data = 8 KB• External memory interface

- SRAM, NOR-type flash memory, SDRAM, PCMCIA- Bus width: 8 or 16 bits, memory space: 64 MB (max.)• Peripheral modules

- DMAC: 16 ch- USB host/function: 1- Multi-function timer (MTU2): 5- 16-bit timer (CMT): 2- 10-bit PWM timer: 16- Watchdog timer (WDT): 1- Real-time clock (RTC): 1 - I2C bus interface: 3- Serial communication interface with FIFO (SCIF): 8- Renesas serial peripheral interface (RSPI): 2- Clock synchronous serial interface with FIFO (SIOF): 1- RCAN: 2 (option)- Video display controller (VDC3):

D-RGB (up to WQVGA)Video IN (BT. 656)

- NAND-type flash memory controller- Serial sound interface (SSI): 4- SPDIF: 1- Sample rate converter (SRC): 2 - CD-ROM decoder- 10-bit A/D converter: 8 ch- Decompression unit

SH7264Outline of the SH7264 Specifications

• Peripheral modules- SD card host interface (SDHI): 1- IEBus: 1 (option)• Package- 208-pin QFP

SH2A-FPU144 MHz

BSCSRAM, NOR,

SDRAM, PCMCIA

I2C:3

SCIF:8

10-bit A/DConverter:

8 ch

CMT:2

SSI (I2S):4

SPDIF:1

MTU2:5

RSPI:2

Inst.cache:8 KB

Datacache:8 KB

URAM:64 KB

SRAM:1 MB

or640 KB

DMAC:16 ch INTC PIO SRC:

2

10-bitPWM:

16WDT RTC

NANDflashI/F

CAN:2

SIOF:1

USB2.0host

/func.

SDHI

IEBus:1

CD-ROMdecoder

VDC3Video In (BT.656)

Display cnt. (D-RGB)

De-Compress

Unit

Functionality added to that of the current product (SH7263)Option


• Digital audio devicesIn-vehicle devices with USB, mini-and micro-componentaudio systems, iPod* accessories, etc.• Graphical dashboardsIn-vehicle information panels, displays on AV centers, etc.• Office automation and industrial equipmentCopying machines, printers,etc.AC servomotors, general-purpose inverters, robots, sequencers,etc.

SH7262/SH7264

Fields of Application

*: iPod is a trademark of Apple Inc., registered in the U.S. and other countries.


Development Concepts of SH7080 Series

Usage : Printers, DVD recorders, fax machines, AC servo motors, and inverters for industrial use.

Various features to achieve high-end embedded systems

Bus extension function and improvedPWM timer, high-speed A/D converter(2.5 μs/ch)*1

Feature3

On-chip debugging function, full spec. ICE,and JTAG-ICE are available.

Feature4

Upper model of SH7040/7144 Series and 3.3-V or 5-V single-power supply

Feature2

With on-chip high-speed flash memory and 80-MHz/104-MIPS high-performance CPUarithmetic operation

Feature1

Achieveshigh-performancecontrol

Reasonabledevelopment tools

No need of externalregulators

40

Peripheral functionssuitable for machineand system controls

*1: Pφ = 20 MHz


Overview of the SH7080• CPU core

- SH-2 (SuperH RISC engine)- 32-bit multiplier (32 bits × 32 bits → 64 bits)• Operating Frequency- CPU clock: 80 MHz (max.)- External bus clock: 40 MHz (max.)- Peripheral clock: 40 MHz (max.)- Clock dedicated for MTU2S: 80 MHz (max.)• Power Supply- 3.3 ±0.3 V or 5.0 ±0.5 V (5.0 ±0.5 V for analog supply)• Internal Memory [ROM/RAM]

- Flash version [512 KB/32 KB]: SH7083/84/85/86, [256 KB/16 KB]: SH7083/84/85

- Mask version [256 KB/16 KB]: SH7083/84/85- ROM less version [RAM: 16 KB]: SH7083/84/85• External Memory Interface

- SRAM, SRAM with byte selection, multiplex I/O- SDRAM, PCMCIA, burst ROM *1

• Internal Functions- Multi-function 16-bit PWM timer: 6 (MTU2), 3 (MTU2S)- Port output enable (POE)- 16-bit cyclic timer: 2- Watchdog timer: 1- I2C bus interface: 1*2

- Synchronous serial interface unit: 1- DMA controller: 4 ch- DTC (simple DMA controller)- High-speed 10-bit A/D converter:

4 ch × 2 (SH7083/84/85)4 ch × 2 + 8 ch (SH7086)

- SCI: 4 (1 ch for 16-stage transmit and receive FIFO)

• Internal Functions- I/O port: 73 (SH7083), 84 (SH7084),

108 (SH7085), 134 (SH7086)- External interrupt pins (NMI+IRQ): 9- On-Chip Debugging function (H-UDI)• Packages

- SH7083 (100-pin): TQFP1414-100 (14 mm square, 0.5-mm pitch)

- SH7083 (BGA): P-LFBGA1010-112 (112 pin, 10 mm square)

- SH7084 (112-pin):LQFP2020-112 (20 mm square, 0.65-mm pitch)

- SH7085 (144-pin)LQFP2020-144 (20 mm square, 0.5-mm pitch)

- SH7086 (176-pin)LQFP2424-176 (24 mm square, 0.5-mm pitch)

41

*1: Supported only at 3.3-V operation, and not supported at 5.0-V operation.*2: SH7083 is not supported.

Internal RAM

Internal ROM

SCI

10-bitA/D converter

SH-280 MHz

MTU2

MTU2S

DMAC/DTC

WDT

CMT

I2CBu

s in

terfa

ce

Port

32-bit multiplier


Development Concepts of SH7146 Series

With on-chip high-speed flash memory and 80-MHz and 104-MIPS high-performance CPU arithmetic operation

Feature1

Enhanced usability by 5-V singlepower supply

Feature2

Improved two-way PWM timersThree high-speed A/D converters (2.5 μs/ch)*1

Feature3

On-chip debugging functions: Full spec. ICE and JTAG-ICE

Feature4


Usage : Invertors for consumer electronics such as air-conditioning outside equipment andwashing machine, invertors for general use, and devices for industrial use.

Various features suitable for high-performance motor control.

42

Achieves vectorand PAM controlsin a single chip

Realizes one-shuntvector control.Controls fan motorand compressorin a single chip

*1: Pφ = 20 MHz


SH7146 Series Overview

SH-280 MHz

SCI

10-bitA/D converterInternal ROM

256 KBInternal RAM

8 KB

32-bitmultiplier

MTU2S

CMT

WDT

MTU2

• CPU core- SH-2 (SuperH RISC engine)- 32-bit multiplier(32 bits × 32 bits → 64 bits)

• Operating Frequency - CPU clock: 80 MHz (max.)- Bus clock: 40 MHz (max.)- Peripheral clock: 40 MHz (max.)- Clock dedicated for MTU2S: 80 MHz (max.)• Power Supply Voltage- 4.0- to 5.5-V single power supply• Internal Memory [ROM/RAM]- Flash version [256 KB/8 KB]: SH7146/SH7149- Mask version [256 KB/8 KB]: SH7146/SH7149• External Memory Interface*1

- 8-/16-bit external bus, SRAM I/F• Internal Functions- Multi-functional 16-bit PWM timer:

6 (MTU2), 3 (MTU2S)- Port output enable (POE): 9- Watchdog timer: 1- High-speed 10-bit A/D converter:

2 ch × 2 + 8 ch (A total 12 ch)- DTC (simple DMA controller)*2

- SCI: 3- I/O ports: 57 (SH7146), 75 (SH7149)

• Internal Functions- External interrupt pins (NMI+IRQ): 5- On-Chip Debugging function (H-UDI)*2

- AUD function: Available only in the flash-memoryversion (SH7149) supporting full functions of the E10A for evaluation.

• Packages- SH7146 (80-pin):

LQFP80 (14 mm square, 0.65-mm pitch)- SH7149 (100-pin):

LQFP100 (14 mm square, 0.5-mm pitch)

43

*1: For external memory Interface, only SH7149 is supported.SH7146 is not supported.

*2: Not available in Mask-ROM versions.

Bus

inte

rface

Port


Development Concept of SH7125 Series

Usage : Invertors for consumer electronics such as refrigerators and vacuum cleaners, and motor control devices such as pumps, fans, and compressors.

Various features to realize small high-performance motor control system.

50-MHz and 65-MIPS high-performanceCPU arithmetic operation

Feature2

Improved PWM timers:Two high-speed A/D converters (2 μs/ch)

Feature3

On-chip debugging functions:Full spec. ICE and JTAG-ICE

Feature4

32-bit RISC-engine microcomputerin a small package: 64 pins/48 pins

Feature1

Achieves one-shuntvector control


44

Much higher-performanceof CPU compared to thatof 8-bit/16-bit CPU



SH-250 MHz

Flash ROM

RAM

10-bitA/D converter

32-bitmultiplier

CMT

WDT

SCI

MTU2

• CPU core- SH-2 (SuperH RISC engine)- 32-bit multiplier

(32 bits × 32 bits → 64 bits)• Operating Frequency

- CPU clock and peripheral I/O clock:50 MHz, 25 MHz or 40 MHz, 40 MHz

• Power Supply Voltage- 4.0- to 5.5-V single power supply• Internal Memory (flash memory, RAM)

- Flash memory: 128 KB/64 KB/32 KB/16 KB- RAM: 8 KB/4 KB• Internal Functions

- Multi-functional 16-bit PWM timer: 6 (MTU2)- Port output enable (POE)- Watchdog timer: 1- High-speed 10-bit A/D converter: 4 ch × 2 (total 8 ch)- SCI: 3- I/O ports: 33 (SH7125), 26 (SH7124)- External interrupt pins (NMI + IRQ):

4 (SH7124), 5 (SH7125) - On-Chip Debugging function (H-UDI)*

• Packages- SH7125 (64-pin):

LQFP-64 (10 mm square/0.5-mm pitch),QFP-64A (14 mm square/0.8-mm pitch),VQFN-64 (8 mm square/0.4-mm pitch)

- SH7124 (48-pin):LQFP-48 (10 mm square/0.65-mm pitch)VQFN-52 (7 mm square/0.4-mm pitch)

45

Note *: The function is not included in the 32- and 16-KB ROM versions.


Development Concepts of SH7147 SeriesVarious features suitable for high-performance motor control.

Power steering systems, hybrid electric vehicles, general-purpose inverters,inverter control of AC servo, etc.Usage:

80-MHz and 104-MIPS high-performance CPU arithmetic operation

Feature1

Single-cycle access to high-speed flash memoryat 80 MHz

Feature2

Peripheral functionality dedicated for motor control• A 12-bit resolution A/D converter enables simultaneous

sampling of all phases of a three-phase motor. • Timers for a three-phase motor

(Multi-function timer pulse unit 2 and Multi-function timer pulse unit 2S)

Feature3

Abundant communications interface functions(RCAN-ET, Synchronous Serial Communication Unit, Serial Communication Interface)

Feature4

Achieves vector controlof a motor

A single chip cancontrol two three-phasebrushless motors.


• CPU core- SH-2 (SuperH RISC engine)- 32-bit multiplier (32 bits × 32 bits → 64 bits)• Operating Frequency- CPU clock: 80 MHz (max.) /64 MHz (max.) *1- Bus clock: 40 MHz (max.) /32 MHz (max.) *1- Peripheral clock: 40 MHz (max.) /32 MHz (max.) *1- Clock dedicated for Multi-function timer pulse unit 2S:

80 MHz (max.) /64 MHz (max.) *1

• Power-Supply Voltage- 80-MHz/5.0-V single power supply - 64 MHz/3.3 V (internal),

5.0 V (I/O, analog power supply) *1

• Internal Memory- Flash memory: 256 KB/384 KB/512 KB- Internal RAM: 16 KB/12 KB• External Memory Interface- 8-bit external bus, SRAM interface• Internal Functions- 16-bit multifunctional PWM timer:

5 (Multi-function timer pulse unit 2),3 (Multi-function timer pulse unit 2S)

- Port output enable (POE)- Advanced user debugger (RAM-monitoring function)- Data transfer controller (simplified DMA controller)- Synchronous serial interface unit (SSU): 1- Serial communications interface: 3

• Internal Functions- High-speed, 12-bit A/D converter:8 ch × 2 (total 16 ch)

- Controller Area Network (RCAN-ET) - Watchdog timer: 1- I/O ports: 57- External interrupt pins (including NMI): 5• Package- LQFP1414-100(14-mm square, 0.5-mm pitch)

Target Applications• Automobile field: power steering systems,

inverter control of hybrid electric vehicles • Industrial field: general-purpose inverters,

AC servo motors

47

Internal RAM:16 KB/12 KB *1

Internal ROM:256 KB

SCI

32-bitmultiplier

MTU2

MTU2S

CMT

WDT

SH-2:80 MHz/64 MHz*1

12-bitA/D converter

AUD

DTC

SSU

UBC

RCAN-ET

Note) *1: temperature range (-40 to 125 C)

Overview of SH7147 Series


High-performance CPU arithmeticoperation at 80 MHz/104 MIPSFeature 1:

Single-cycle access to high-speedflash memory at 80 MHzFeature 2:

On-chip peripheral functional modulesdedicated for motor control• A 12-bit resolution A/D converter enables simultaneous

sampling of all phases of a three-phase motor.• On-chip timer for a three-phase motor (MTU2 and MTU2S)

Feature 3:

Abundant communications interfacefunctions (RCAN-ET, SSU, SCI)Feature 4:

A single chip can control two

3-phase brushlessmotors.

Applications: Inverters, AC servo motors, manipulators, measuring equipment, etc. for industrial use

On-chip debugging functionsFull ICE and JTAG-ICE are available.Feature 5:

Vector control of a motor

is enabled.

Reasonable development tool

Various features to adapt to high-performance motor control system

Development Concepts of the SH7137


Functional Outline of the SH7137

49

• On-chip debugging function- H-UDI- User break controller (UBC)

• Packages- SH7136: LQFP1414-80

(14-mm square, 0.65-mm pitch) - SH7137: LQFP1414-100

(14-mm square, 0.5-mm pitch)

Note *: Only available for SH7137

• CPU core- SH-2: SuperH RISC engine• Operating frequency- CPU clock: 80 MHz (max.)- Bus clock: 40 MHz (max.)- Peripheral clock: 40 MHz (max.)• Power-supply voltage- 3.3 V±0.3 V or 5.0 V±0.5 VSingle-power supply (AVcc = 5.0 V±0.5 V)

• On-chip memory- 256-KB Flash memory- 16-KB RAM• External memory interface- SH7136: None- SH7137: External bus width is 8 bits.• Internal peripheral function- Multi-functional 16-bit PWM timer: 6 (MTU2), 3 (MTU2S)- Port output enable (POE)- Compare match timer (CMT): 2- Watchdog timer (WDT): 1- Data transfer controller (DTC)- Serial communications interface (SCI): 3- Synchronous communications interface (SSU): 1- I2C bus interface: 1- RCAN-ET: 1- A/D converter:12 bits × 16 ch (SH7137), 12 bits × 12 ch (SH7136)

SH-280 MHz

UBC

H-UDI

I2C: 1

BSC*SRAM

12-bitA/D converter

CMT(16 bits × 2)

MTU2S(16 bits × 3)

MTU2(16 bits × 6)

INTC

I/O Ports

Flash ROM256 KB

WDT

DTC

SSU: 1 RCANSCI: 3

RAM16 KB



Features• CPU core- SH-2 with an operating frequency of

50 MHz, 3.0 to 3.6 V operation- 32-bit multiplier (32 bits × 32 bits → 64 bits)• Internal memory- ROM: 256 KB (Flash/Mask/ROMless)- RAM: 8 KB• Internal functions- Multi-functional 16-bit timer (MTU): 5 - Internal DMAC and DTC- External bus: 8/16/32 bits- A/D converter: 10 bits, 8 ch (4 ch × 2 units)- SCI: 4 - I2C: 1 • Package

- QFP-112 (SH7144)/LQFP-144 (SH7145)

Main areas of application• Digital consumer appliances,

OA equipment industrial use

SH7144 Series Block Diagram

WDT

SH-250 MHz

DTC

SCI × 4

MTU16-bit× 5

A/D10-bit× 8 ch

DMAC 4 ch

CMT

Bus

inte

rface 32-bit

multiplier

Por

t

InternalRAM

Internal ROMFlash/Mask

50


SH7046 Overview

80-pin QFP

SH7046 Block Diagram

- Single-Chip Microcomputer in a Small Package -

SH7108 (Mask Version)*

SH7046F (Flash Version)ROM RAM


SH-250 MHz

SCI × 2

10-bit A/D

MMT

MTU

DTC

WDT

CMT

32-bit multiplier


Internal RAM

Features• CPU core- SH-2 (Renesas′s original SuperH 32-bit RISC)- Max. operating frequency: 50 MHz @ 4.0- to

5.5-V operation- 32-bit multiplier (32 bits × 32 bits → 64 bits)(The SH7101: 40 MHz)

• Internal functions- Powerful 16-bit timer (MTU, MMT)- Enables output of a max. 15-phase PWM waveform- Built-in DTC- A/D converter: 10 bits, 12 ch (4 ch × 3 units)- SCI: 2(SH7101: Without MMT and DTC 8 channelA/D converter (4 ch × 2 units))

Main applications• White ware goods with inverters such as air

conditioners, washing machines, and refrigerators,and industrial applications such as inverters, AC servos, FA, UPS, and FA sequencers SH7148 (Mask Version)

SH7048 (Mask Version)

SH7106 (Mask Version)*SH7101 (Mask Version)**

128 KB

256 KB256 KB

64 KB

128 KB

64 KB32 KB

4 KB

12 KB8 KB

4 KB

4 KB

4 KB2 KB

*: Without DTC **: Without DTC and MMT

51


SH7047 Overview- Microcomputer with a Built-in CAN Bus Interface -

100-pin QFP

SH7049 (Mask Version)

SH7047F (Flash Version)


SH-2

SCI × 3

10-bit A/DDTC

WDT

CMT

MMT

MTU

HCAN 2

32-bit multiplier


Internal RAM

Features• CPU core- SH-2 (Renesas original SuperH 32-bit RISC)- Max. operating frequency: 50 to 40 MHz @

4.5 to 5.5-V operation- 32-bit multiplier (32 bits × 32 bits → 64 bits)• Internal functions- Powerful 16-bit timer (MTU, MMT)- Enables output of a max. 15-phase PWM

waveform - Built-in DTC- A/D converter: 10 bits, 16 ch (8 ch × 2 units)- SCI: 3- HCAN2: 1

Main applications• Automobile applications such as EPS and

airbags, and industrial applications suchas inverters, AC servo, FA, UPS, andFA sequencers




ROM RAM256 KB 12 KB128 KB 8 KB256 KB 8 KB128 KB 4 KB64 KB 4 KB

* SCI: 2, Without DTC

52


SH7040 Series OverviewFeatures• SH-2 core high-performance single-chip RISC- 37 MIPS/28.7 MHz - Built-in 32-bit multiplier• Built-in large-capacity memory- ROM: 64 KB (mask)/128 KB (mask, OTP)/

256 KB (mask, Flash)/ROMless- RAM: 4 KB (can be used as 1-KB cache + 2-KB RAM)• Built-in cache memory- 1-KB instruction cache, 256 entries, and direct mapping• Various peripheral functions- Powerful timer: MTU, 2-ch compare-match timer- A/D converter: 10 bits × 8 ch- Serial interface: 2 - DMAC: 4 ch• Products lineup (ROMless type is also available)

Main applications• Motor controls, navigation systems,

digital cameras, PPCs, printers, faxes, and JPEG application system

Note: SH7042 (3.3-V Version): TQFP-120

SH7040/42/44 QFP-11264 KB/128 KB/256 KB

64 KB/128 KB/256 KBSH7041/43/45 QFP-144

ROM size Package

53

SH7040 Series Block Diagram

SH-2CPU

Multiplier

CPG

WDT

SCI × 2

Timer16-bit× 7A/D

10-bit× 8 ch

DMAC 4 ch

Bus

inte

rface

Por

t

Sele

ctab

le

ROM64 KB/128 KB

256 KB

RAM 4 KB

Cache 1 KBRAM 2 KB


SH7014, SH7016, and SH7017 Overview

Main applications• Video printers, liquid crystal projectors, Scanners, and electronic musical

instruments, etc.

Features• High-performance single-chip RISC with SH-2 core- 37 MIPS/28.7 MHz/5 V- Built-in 32-bit multiplier• Built-in memory- ROM: 64 KB (Mask)/128 KB (Flash)/ROMless- RAM: 3 KB/4 KB

(can be used as 1-KB cache + 1-KB/2-KB RAM)• Built-in cache memory- 1-KB instruction cache, 256 entries, and direct mapping• Peripheral functions- Powerful timer: 16 bits × 5 (MTU: 0-2, CMT: 2) - A/D* converter: 10 bits × 8 ch- Serial interface: 2- DMAC: 2 ch

• Product lineup

28.7 MHz/5 V

3 KB QFP-112SH7014 -

3 KB QFP-112SH7016 64 KB (Mask)

SH7017 4 KB QFP-112128 KB (Flash)

f/VROM size RAM Package

54

*: A/D module is different between SH7014 and SH7016/17

SH7017F Block Diagram

SH-2CPU

CPG

WDT

SCI × 2

Timer16-bit× 5

A/D10-bit× 8 ch

DMAC 2 ch

Bus

inte

rface Multiplier

Por

t

Sele

ctiv

e

ROMFlash: 128 KB

RAM 4 KB

Cache: 1 KBRAM: 2 KB


SH7020 and SH7030 Series Overview

Features• 32-bit single-chip RISC with high-performance- 26 MIPS/20 MHz• Built-in 16-bit multiplier• Various built-in large-capacity memories- ROM: 64 KB/32 KB/16 KB/ROMless- RAM: 8 KB/4 KB/1 KB• Various built-in peripheral functions- 16-bit timer, A/D converter, DMAC, SCI, INTC,

Bus state controller (BSC), etc• Package- TQFP-120, QFP-112, and TQFP-100• Product lineup- 5 types (ROMless Versions for the SH7034 and

SH7020 also available)

Main applications• Motor controls, FAs, navigation

systems, HDDs, printers, faxes, digital cameras, etc

ROM/RAM A/D Package

QFP-112TQFP-120

TQFP-100

SH7032 Yes-/8 KBSH7034 Yes64 KB/4 KB

SH7021 -32 KB/1 KBSH7020 -16 KB/1 KB

SH7034B Yes-/4 KB

- Another Low Price ROMless Version is Added to the Lineup -


RAM4 KB

SH-1CPU

Multiplier

CPG

WDT

SCI × 2

Timer16-bit× 5

A/D10-bit× 8 ch

ROM(OTP/Mask)

64 KB

Por

t

DMAC 4 ch

55

BS

C


SH7065 Overview

Features• SH-core (with an enhanced DSP function)

high-performance single-chip RISC- 60 MHz/3.3 V- All SH-2 instructions + DSP-function enhanced

instructions (SH2-DSP core)• Built-in large-capacity memory- ROM: 256 KB (Flash/Mask)- RAM: 8 KB (X-RAM: 4 KB, Y-RAM: 4 KB)• Powerful peripheral functions- Timers: TPU (6) + CMT (2) + MMT (1)- A/D converter: 10 bits × 4 ch × 2 units- D/A converter: 8 bits × 2 ch- SCIF: (FIFO) 3 - DMAC: 4 ch- INTC (interrupt controller), WDT etc• Bus state controller (BSC)- Directly connected with ROM/SRAM/DRAM/EDO• Power management unit- Can be switched between the CPU, internal peripheral,

and external bus clock- Module standby function• Endian switching of external data available• Package- LQFP-176 (24 mm × 24 mm, 0.5-mm pitch)

Main applications• MFPs, high-performance digital cameras,digital video cameras, DVD systems,communication terminals, and industrial controllers

- High-Performance Single-Chip RISC Microcomputerwith a Built-in Large-Capacity Flash Memory -


BSC

SH2-DSPCPU

DMAC: 4 ch

SCIF: 3

INTC

WDT

MMT

Timer16-bit × 8

ROM: 256 KB(Flash/Mask)

RAM:8 KB

D/A converter8-bit × 2 ch

A/D converter10-bit × 8 ch

I/O port

PLL

56


SuperH with Built-in Ether

57


SH-Ether Overview

• Target applications- LBPs (Laser Beam Printer), MFPs (Multi Function Printer) - LAN cards (PC peripherals, FA devices)- Digital home electronics, IP Phones - Amusement devices- POS systems- Monitoring systems- Others(The Ethernet required systems)

Adopted for variousembedded Ethernetsystems

The SH-Ether Series products are the SuperH microcomputersequipped with the 10/100-Mbps supporting Ethernet controllersin compliance with the IEEE802.3u standard.

58


SH-Ether Roadmap

FIFO: 2 KB

UD

MP

SH7615(SH2-DSP)

SH7618(SH-2)

SH7710(SH3-DSP)

SH7650(SH-2)

62.5 MHz

Ether: 2 IPsec

HIF

FIFO: 512 B

High PerformanceSH-Ether

Single-chip solution‘‘Simple-Ether’’

Planning

200 MHz

100 MHz

SH7712(SH3-DSP)

IPsec-less

SH7619(SH-2)

PHY

125 MHz

SH7713(SH3-DSP)

Ether: 1

DTCP-IPequipped

133 MHz

59

SH7652(SH-2A)

200 MHz

SH7670/71/72/73(SH-2A)

SH7616(SH2-DSP)

DTCP-IPequipped

Ether: 1 USB2.0

SH7764(SH-4A)

Ether: 1 USB2.0

2D Graphic

SH7763(SH-4A)

GbEther: 2PCI, IPsec


SH7615 OverviewFeatures• High performance RISC engine SuperH core

(SH2-DSP)- 81 MIPS, 125 MOPS (max.) @62.5 MHz• Instruction/data combination type cache (4 KB)- 4-way set associative, 64 entries, 16-byte line length• Internal RAM (8 KB)• SDRAM Interface- Supports high-speed access: external bus

to 62.5 MHz (max.)- Possible 16 Byte DMA dual burst access• Ethernet controller

(MAC*1: accordance with IEEE802.3u)- transmission rate: 10/100 Mbps, Full duplex transmit

and receive- Assembles/Disassembles data frame, CRC- Supports MII*2, Magic packet ™*3

- FIFO 512 Byte each for transmission and reception• Boundary Scan - Boundary Scan Function (accordance with IEEE1149.1)• Peripheral function- TPU (3), SCIF (2), DMAC (2), INTC, WDT (1), FRT (1),

SIO (3), I/O port etc• Vcc = 3.3 V (supports 5 V I/F regarding I/O and Ethernet pin)

*1 MAC:Media Access Control, *2 MII:Media Independence Interface, *3 Magic Packet is a trademark of Advanced Micro Devices, Inc.

Bus-StateController

CPGPLL

INTC

UBC: 4

16-bitfree-run

timer

SCI: 2

DMAC 2 ch

SIO: 3

Cachememory

4 KB

Ether10/100

WDT

I/Oport

SH2-DSPCPU

RAMX: 4 KBY: 4 KB

Ether FIFO = 512 BPackage: QFP-208 / CSP-240


60


SH7616 OverviewFeatures• High performance RISC engine SuperH core

(SH2-DSP)- 81 MIPS, 125 MOPS (max.) @62.5 MHz• Instruction/data combination type cache (4 KB)- 4-way set associative, 64 entries, 16-byte line length• Internal RAM (8 KB)• SDRAM Interface- Supports high-speed access:

external bus to 62.5 MHz (max.)- Possible 16 Byte DMA dual burst access• Ethernet controller

(MAC*1: accordance with IEEE802.3u)- transmission rate: 10/100 Mbps, Full duplex transmit

and receive- Assembles/Disassembles data frame, CRC- Supports MII*2, Magic packet ™*3

- FIFO 2 KB each for transmission and reception• Boundary Scan - Boundary Scan Function (accordance with IEEE1149.1)• Peripheral function- TPU (3), SCIF (2), DMAC (2), INTC, WDT (1), FRT (1),

SIO (2), I/O port etc- SIO with FIFO (16 bits × 16) for CODEC• Vcc = 3.3 V (supports 5 V I/F regarding I/O and Ethernet pin)

*1 MAC: Media Access Control, *2 MII: Media Independence Interface,*3 Magic Packet is a trademark of

Advanced Micro Devices, Inc.

Ether = 2 KBSIO with FIFO 1 chPackage: QFP-208


Bus-StateController

CPGPLL

INTC

UBC: 4

16-bitfree-run

timer

SCI: 2

DMAC 2 ch

SIO: 1w/FIFO

Cachememory

4 KB

Ether10/100

WDT

I/Oport

SH2-DSPCPU

RAMX: 4 KBY: 4 KB

SIO: 2

61


Difference Between SH7615 and SH7616

• Improve the efficiency of G.729a handling• Support for CODEC having Communication Data

e.g. Si 3000 (Silicon Laboratories), STLC7550 (SGS Thompson)

FIFO (up to 2 KB)• Possible one transaction per frame• Improve the efficiency of transmission and reception of frames

CAM match signal• Multi Address support• Useful for FA network

SIOF (SIO with FIFO)

62


Overview of SH7618/7618A Specifications

• CPU core- SH-2 (SuperH 32-bit RISC engine, 32-bit multiplier)- PVcc = 3.0 to 3.6 V, Vcc = 1.4 to 1.6 V• Operating Frequency- CPU clock: 100 MHz- Bus clock: 50 MHz• Internal Memory- RAM: 4 KB - Cache memory:

4 KB (Four-way set associative): 761816 KB (Four-way set associative): 7618A

• Host I/F- 1 KB × 2 sections- HIF boot function• Ethernet functions- EtherMAC (10/100 Mbps): 1 ch- MII is also available.- Transmit and receive FIFO: 256 bytes each (7618),

512 bytes each (7618A)- Dedicated DMA controller: 2 ch• External Memory Interfaces- SRAM, SDRAM, and PCMCIA I/F- Switchable to big/little endian- External bus can be extended up to 16 bits

- Inexpensive network controller incorporatingEtherMAC and host interface -

• Peripheral Functions - Serial communication interface: 3

Switchable to UART/clock synchronous 16-stage transmit and receive FIFO

- 16-bit interval timer: 2- Watchdog timer: 1- General-purpose I/O port: 78- JTAG interface support- External interrupt pins: 9• Package- CSP-176 (13 mm square, 0.8-mm pitch)

SCI (with FIFO):3

Host interface

Interval timer

External bus interface

EDMAC

EtherMAC: 1 ch

SH-2100 MHz

Cache: 4 KB

RAM: 4 KB

63


Overview of SH7619 Specifications- PHY in a single chip improves performance -

• CPU core- SH-2 (32-bit SuperH RISC engine, 32-bit multiplier)- PVcc = 3.0 to 3.6 V, Vcc = 1.7 to 1.9 V• Operating Frequency- CPU clock: 125 MHz- Bus clock: 62.5 MHz• Internal Memory- RAM: 16 KB- Cache memory: 16 KB (4-way set associative) • Host I/F- 1 KB × 2 sections- HIF boot function• Ethernet Functions- EtherMAC (10/100 Mbps): 1 ch- EtherPHY (10/100 Mbps): 1 (MII is also available)- Transmit and receive FIFO: 512 bytes each- Dedicated DMA controller: 2 ch• External Memory Interface- SRAM, SDRAM, and PCMCIA- Switchable to big/little endian- External bus can be extended up to 32 bits• General-Purpose DMA Controller- 4 ch

• Peripheral Functions- Serial communication interface: 3

Switchable to UART/clock synchronous16-stage transmit and receive FIFO

- 16-bit interval timer: 2 - Watchdog timer: 1- General-purpose I/O ports: 78- JTAG interface support- External interrupt pins: 9• Package- CSP-176 (13 mm square, 0.8-mm pitch)

SCI (with FIFO):3

Host interface

Interval timer

External bus interface

E-DMAC/DMAC

EtherMAC/PHY: 1 ch

SH-2125 MHz

Cache: 16 KB

RAM: 16 KB

64


SH7650 Functions and Features

• Incorporates high-performance SH-2 core- Realizes network processing and DTCP processing at 173 MIPS@133 MHz with no load on the main CPU

• On-chip functions supporting DTCP-IP*

- Authentification between systems and encryption/decryption ofcontents are achieved by hardware and supplied firmware

• Internal PCI bus controller and host interface- Facilitates connection with the main CPU• Includes wireless LAN interface and MPEG-TS port for

moving image streaming• Abundant bus interfaces- SDRAM interface- Burst ROM interface, etc.

65

*: DTCP-IP standard is a standard for protecting contents on the IP networkstandardized by DTLA (Digital Transmission Licensing Administrator)


SH7650 Overview• CPU core- SH-2(SuperH 32-bit RISC, with on-chip 32-bit multiplier)

- PVcc = 3.0 to 3.6 V, Vcc = 1.4 to 1.6 V• Operating frequency- CPU clock: 133 MHz- Bus clock: 66 MHz• Internal memory- Internal RAM: 8 KB- Cache memory: 16 KB• On-chip DTCP-IP• Host interface- 1 KB × 2 banks- Includes HIF boot function• PCI controller- 33 MHz/32 bits• Ethernet controller- EtherMAC (10/100 Mbps): 1 ch- Includes MII - Transmit/receive FIFO: each 512 bytes- Dedicated DMA controller: 2 ch- Incorporates TCP/IP checksum accelerator• Memory interface- SRAM, SDRAM interface- External bus can be extended up to 32 bits

• Encryption module- AES encryption/decryption- Dedicated DMA controller• On-chip MPEG-TS interface- Includes 3 channels• Peripheral functions- Serial communication interface: 2 - 16-bit interval timer: 2- Support for JTAG interface, external interrupt pin,

and I/O ports• Package- CSP-336 (17-mm square, 0.8-mm pitch)

SH-2133 MHz

EtherMAC: 1 ch

Interval timer × 2RAM: 8 KB

Host interface/PCI controller

SCI: 2Cache: 16 KB

Encryption module

MPEG-TS: 3

DTCP-IP

66


• Network-specialized cost performance- SH-2A core: 200 MHz

• DTCP-IP -support functions- An inter-device authentication function and content

encryption/decryption function implemented by hardware and firmware provided with the SH7652, compliant with theDTCP-IP standard.

- Network functions for IP broadcasting

• USB 2.0 High Speed and SD host interface

• Abundant bus interfaces- SDRAM I/F- Burst ROM I/F etc.

SH7652 Overview- Network processor with DTCP-IP function for DLNA(Digital Living Network Alliance) incorporated -


Functional Overview of SH7652

*The specification is subject to change.

• CPU core- SH2A-FPU (32-bit SuperH RISC, 32-bit multiplier)- PVcc = 3.0 to 3.6 V, Vcc = 1.1 to 1.3 V• Operating frequency- CPU clock: 200 MHz- Bus clock: 66 MHz• Internal memory- RAM: 32 KB - Cache memory: 16 KB• DTCP-IP• Host interface- 2 KB × 2 banks- HIF boot function• Ethernet controller- EtherMAC (10/100 Mbps): 1- Transmit/receive FIFO: 512 Bytes each- TCP/IP checksum accelerator • USB 2.0 High Speed- Host or Function: 1• Memory interface- SRAM, SDRAM interface- External bus can be extended up to 32 bits.• Encryption module- AES encryption/decryption- FIFO (independent transmit/receive)- Dedicated DMAC (AES FIFO ↔ SDRAM)

• MPEG-TS interface- PS- 2 channels included• Peripheral functions- Serial communication interface with FIFO: 2- I2C: 1 ch- SD host interface - 16-bit interval timer: 2 - JTAG interface support, external interrupt pin,

I/O port, etc. • Package- BGA-240

SH2A-FPU:200 MHz

Encryption module

RAM: 32 KB

Cache: 16 KB

DTCP-IP

Host interface

MPEG-TS: 2

16-bit Timer × 2

SCIF: 3

EtherMAC: 1 ch

USB2.0 HS SD I/F


Functional Overview ofSH7670/SH7671/SH7672/SH7673

*The specification is subject to change.

• CPU core- SH2A-FPU(32-bit SuperH RISC, 32-bit multiplier)

- PVcc = 3.0 to 3.6 V, Vcc = 1.1 to 1.3 V• Operating frequency- CPU clock: 200 MHz- Bus clock: 66 MHz• Internal memory- RAM: 32 KB - Cache memory: 16 KB• Host interface - 2 KB × 2 banks- HIF boot function• Ethernet controller- EtherMAC (10/100 Mbps): 1- Transmit/receive FIFO: 512 Bytes each- TCP/IP checksum accelerator • USB 2.0 High Speed- Host or Function: 1• Memory interface- SRAM, SDRAM interface- External bus can be extended up to 32 bits.• Encryption module (Only SH7672, 73)- AES encryption/decryption- FIFO (independent transmit/receive)- Dedicated DMAC (AES FIFO ↔ SDRAM)

• Peripheral functions- Serial communication interface with FIFO: 2- I2C: 1 - SD host interface (Only SH7671, 73)- 16-bit interval timer: 2- JTAG interface support, external interrupt pin,

I/O port, etc. • Package- BGA-256

SH2A-FPU:200 MHz

Encryption module

RAM: 32 KB

Cache: 16 KB

USB2.0 HS

Host interface

16-bit Timer × 2

SCIF: 3

EtherMAC: 1 ch

SD I/F


Host Interface (HIF)

LAN portLAN

16 bits

Main CPU bus

SH7618/SH7619/SH7650/SH7652

SH local bus

Connectablewith

general bus

HIFRAM

RAM

SH-2 Cache

EDMAC

Ether-C PHY

Boot ROM not required

70

Features:1. Connectable to the main CPU with parallel bus2. HIF boot function eliminates the need for boot ROM

Flashmemory

MainCPU

SDRAM

Flashmemory


SH7710/SH7712/SH7713 Overview


BSCSDRAM I/F

ROM,SRAM I/FPCMCIA I/F

JTAG

SIOF: 2

DMAC 6 ch

EDMAC4 ch

Bridge**

Cachememory32 KB

EtherMAC

X/YRAM16 KB

Ether**

MAC

SH3-DSP200 MHz

MMU INTC

TMU RTC SCIF:2

IPsecAccelerator*

SH7712 is IPsec-less version of SH7710SH7713 is IPsec-less, Ethernet (1) version of SH7710

*: Only SH7710**: Only SH7710 and SH7712

Features• High performance RISC engine

SH3-DSP core- 260 MIPS@200 MHz• Ethernet Controller

(MAC: IEEE802.3u compliant)- 10/100 Mbps, Full duplicate mode supported- Transfer/Receive FIFO: 2 KB each- Bridge: transfer FIFO: 3 KB each• IPsec accelerator*

- Authentication algorithm: SHA-1, MD5- Cryptography algorithm: DES, 3DES- Dedicated DMAC 4 ch• Unified Cache: 32 KB• Internal RAM: 16-KB X/Y-RAM• SDRAM interface• Power Supply Voltage: Core 1.5 V, I/O 3.3 V• Package: QFP-256, CSP-256

Main applications• Home gateway, VoIP-TA, IP phone,

IP camera, Security equipment, etc

71


SH7763 OverviewFeatures• SH4-A core (266 MHz)• Cache (instruction: 32 KB, data: 32 KB)• On-chip MMU• 2-way super scalar 7-stage pipeline• Internal RAM (16 KB)• SDRAM interfaceDouble data rate: 32-bit data bus, 133 MHz (DDR266), Class 1

• On-chip STIF (stream interface)• Ethernet controller (IEEE802.3): 2- 10/100/1000 Mbps full duplex transfer supported- Flow control (IEEE802.3x) supported - On-chip E-DMAC: 2 ch (Tx, Rx)- 2-KB send/8-KB receive FIFO• IPsec accelerator - Authentification algorithm: SHA-1, MD5- Encryption algorithm: DES, 3DES, AES- On-chip IPsec DMAC: 2 ch• PCI controller: PCI ver2.2• LCD controller: VGA full color display is supported• USB Host/Function: Ver. 2.0 Full Speed is supported• Peripheral functions- SCIF (3), DMAC (6 ch), INTC, RTC, TMU, SIOF (3),

SSI, I2C, HAC, various memory card I/Fs, I/O ports, A/D converter, D/A converter, etc.

• Vcc- Core = 1.25 V, I/O = 3.3 V, DDR I/O = 2.5 V

• Package- PBGA2121-449, ball pitch: 0.8 mm

Block diagram of the SH7763

BSC1ROM, SRAM I/F

PCMCIA I/F

JTAG

Bridge

Cache:64 KB

GbEtherMAC1

GbEtherMAC2

SH-4A:266 MHz

MMU INTC

TMU TPU RTC

U-RAM:16 KB

SIOF:3

DMAC:6 ch

SCIF:3

BSC2DDR-SDRAM-I/F

PCIC

USB2.0(H/F)

LCDC

SSI I2C Memory card I/F

IPsec Acc.A/D converter:

4 chD/A converter:

2 ch

STIF

HAC

CPG

(Part No.: R5S77630Y-266BGV)

72


SH7764 Overview

73

• CPU core- SH-4A (SuperH RISC engine) FPU• Operation frequency- CPU Clock: 324 MHz- Bus Clock: 108 MHz• Operation Voltage (double voltage)- In 1.2 V/Ex 3.3 V• Embedded memory- RAM: 16 Kbytes- Cache: I = 32 KbytesD = 32 Kbytes

• Bus Interface- SRAM, Flash, SDRAM- External bus 8 bits, 16 bits, 32 bits(SDRAM: 32 bits/64 bits)

- External bus space can be divided into 4 areas:Each 64 MB max. (Total 256 Mbytes)

• Peripheral- 32-bit Timer: 6 - Watch dog Timer: 1- Ether MAC: 1 ch- I2C bus interface: 1 - DMA controller: 6 ch- SCIF (Asynchronous serial): 3- SSI (Codec I/F): 6- SCR (Sampling rate converter): 2- NAND Flash Interface- IDE controller (UltraDMA/66 Support): 1- SD I/O (option)- 2D Graphic- LCDC/Digital RGB (VDC2)- GPIO- INTC- H-UDI (User Debag Interface)• Package- BGA404pin

SH-4A324 MHz MMU I-cache

32 KB

Datacache32 KB

RAM16 KB

MCUROM, SRAM,

SDRAMFPU INTC DRAM:

6 SRC: 2

TMU32 bits:

6WDT H-UDI

NANDFlash

I/FI2C: 1 GPIO

SCIF: 3 SSI: 6 IDE controller: 1USB2.0

host/function(HS): 1

2DGraphic

EtherMAC:1 ch

SD I/O(option)

VDC2DigitalRGB

LCDC


List of Specifications for the SH-Ethernet Products (1)

SH-2 core

DSP function enhanced version

SH7615

512 B/512 B

208LQFP (SH7615ARF)240CSP (SH7615ARBP)

FIFO expandedversion

SH7616

2 KB/2 KB

208LQFP

2 ch220

3

176CSP

Item

Operating frequencyPower supply voltageCache memory

General DMACEthernet controller

Rx/Tx FIFO

Serial I/O

CPU

Ethernet-specific DMACUser break controllerTimer unitFree-run timerSerial communication I/Fwith FIFO

Package

Internal RAM

62.5 MHz3.3 V4 KB

2 ch1

3

SH2-DSP core

2 ch431

2

8 KB

EtherMAC,PHY

125 MHz1.8 V/3.3 V

SH7619

16 KB

4 ch1, PHY

512 B/512 B

1

16 KB

EtherMAC

100 MHz1.5 V/3.3 V

SH7618/18A

4 KB/16 KB

01

SH7618: 256 B/256 BSH7618A: 512 B/512 B

0

4 KB

74


List of Specifications forthe SH-Ethernet Products (2)

75

Item

CPU SH3-DSP core SH-4A core SH-4A coreOperating frequency 200 MHz 266 MHz 324 MHzPower supply voltage 1.5 V/3.3 V 1.25 V/3.3 V/2.5 V 1.25 V/3.3 VCache memory 32 KB 64 KB 64 KBInternal RAM 16 KB 16 KB 16 KBGeneral DMAC 6 ch 6 ch 6 chEthernet controller 2 2 (Gbit) 1

Rx/Tx FIFO 8 KB/2 KB× 2 pairs

2 KB/2 KB× 1 pair

2 KB/2 KB× 2 pairs

4 chEthernet-specific DMAC

2 KB/2 KB× 1 pair

2 ch 4 ch 2 chUser break controller 2 2 2Timer unit 3 6 6Free-run timer - - -Serial communication I/Fwith FIFO 2 3 3

Serial I/O 2 (incl.FIFO) 3 + USB (1) 6 + USB (1)

Package HQFP2828-256256CSP PBGA2121-449 PBGA1919-404

EtherMAC×2,IPsec EtherMAC × 2 EtherMAC × 1 Gb EtherMAC × 2,

PCI EtherMAC × 1

SH7710 SH7712 SH7713 SH7763 SH7764


List of Specifications forthe SH-Ethernet Products (3)

76

Item

CPUOperating frequencyPower supply voltageCache memoryInternal RAMGeneral DMACEthernet controllerRx/Tx FIFOEthernet-specific DMACUser break controllerTimer unitFree-run timerSerial communication I/Fwith FIFO

Serial I/O

SH-2A core200 MHz

1.2 V/3.3 V16 KB32 KB8 ch

1512 B/512 B

2 ch22-

3

- (USB2.0 × 1)256CSPPackage

EtherMAC × 1 EtherMAC × 1,SDIO, Crypt

EtherMAC × 1,Crypt

EtherMAC × 1,SDIO

SH7670 SH7673SH7672SH7671


Processor TypeSH7700 SeriesSH7750 SeriesSH7780 Series

77


Lineup of SuperH (Processor-Type)Microcontroller Products

78

SH-2

100 MHzSH7606

125 MHzSH7619

Ether100 MHzSH7618

: In Planning: Under Development

: Mass Production: New Product

SH7700 Series (SH-3, SH3-DSP)

133 MHzSH7706

133 MHzSH7705

133 MHz LCDC, USBSH7720/21

167/200 MHzSH7709S

100/160 MHz LCDC, USBSH7727

SH7729R SH7710/12/13167/200 MHz Ether MAC

SH7200 Series (SH-2A)

120 MHzSH7201

SH7261

200 MHzSH7206

200 MHzSH7203

SH7263200 MHz

Ether

SH7670

Dual Core

SH7265

SH7205

SH7264

144 MHzSH7262

SH7780 Series (SH-4A)

SH7763266 MHzG-Ether

SH7722266/333 MHz(SH4AL-DSP)

SH7780400 MHz

SH7730200/266 MHz

Dual CoreSH7786

SH77xxSH7785600 MHz

SH7764324 MHz

Ether

SH7723400 MHz

SH7750S200 MHz

167 MHzSH7751 PCIC

SH7760200 MHz

LCDC

SH7750R240 MHz

SH7751RPCIC

SH7750 Series (SH-4)


High-Performance 32-Bit RISC Processor

Features• Low power and high performance:133 mA@133 MHz (SH7705)

• MMU (Memory Management Unit), cache on chip• Power management- Low-power mode- Frequency control- Module ON/OFF control• Compatible with SH-1 and SH-2 instruction sets

79


SH7705 Overview

Features• High-performance ultra-low power RISC CPU SH-3- Low power-consumption: 1 mA/MHz (typ.)

@1.5 V (Internal)- CPU clock: 133 MHz/bus clock: 66 MHz• Cache: Large Capacity 32 KB• On-chip USB Function Ver.2.0 (Full Speed)- On-chip USB transceiver- Control/bulk/interrupt transfer support• BSC (bus state controller)- Page mode FLASH, ROM, SRAM, SDRAM• Enriched on-chip peripheral functions- DMAC, WDT, A/D Converter, CMT, RTC, etc.• On-chip high-speed serial interface - UART/clock synchronous switchover type

(on-chip 64-byte FIFO): 2(IrDA1.0: 1)

• Powerful power management function- Sleep, standby, module standby,

hardware standby• Package: LQFP-208 (28 mm square),CSP-208 (12 mm square)

Main applications• DSC, DVC, Video printer, Faxes, Ink-jet printer, Barcode Reader, PDA, and POS terminal


32-bitmultiplier

BSCROM, SRAM I/F

SDRAM I/FBurst ROM I/F

SH-3CPU

4-waycache32 KB

RTC

INTC

CPG/PLL

MMUTPU:

16-bit × 4

TMU:32-bit x 3

UBC: 2

DMAC:4 ch

SCI: 2 IrDA1.0

USBfunction

A/D10-bit × 4 ch

Port

- SH-3 Low Power Version -

80


SH7706 Overview

Features• CPU SH-3: 133 MHz• Cache: 16 KB• Peripheral functions- 4-ch DMAC- 10-bit 4-ch A/D converter- 8-bit 2-ch D/A converter- SCI : 2 (with FIFO: 1)- 3-ch timer (32 bits)- RTC• Power management function• High-performance,

low power consumption • Package: 176-pin LQFP, 208-pin CSP

Main applications• MFP/Ink-jet printers, Faxes, scanners, DVD recorders, and DVC


32-bitmultiplier

RTCUBC: 2

BSCROM,SRAM I/FSDRAM I/FBurst ROM I/FPCMCIA I/F

SH-3CPU

PORT

4-waycache16 KB

TMU32-bit× 3

INTC

CPG/PLL

MMU

DMAC4 ch

SCI: 2A/D

10-bit4 ch

D/A8-bit2 ch

- SH-3 Compact Version -

81


SH7709S Overview

Features• Improved CPU operation performance

200 MHz (260 MIPS) MAX.Line-up is 100/133/167/200 MHzVersion

• Cache: 16 KB• Peripheral functions- 4-ch DMAC- 10-bit 8-ch A/D converter- 8-bit 2-ch D/A converter- SCI: 3 (with FIFO: 2)

(IrDA 1.0: 1)• Power management function• High-performance and low power

consumption• Package- LQFP-208, CSP-240 (100/133/167 MHz)- HQFP-208 (200 MHz)

Main applications• Portable information equipment,

internet equipment, LBP, printer, scanner, and network equipment

SH7709S Block Diagram

32-bitmultiplier

RTCUBC: 2

BSCROM,SRAM I/FSDRAM I/FBurst ROM I/FPCMCIA I/F

SH-3CPU

PORT

4-waycache16 KB

TMU32-bit× 3

INTC

CPG/PLL

MMU

DMAC4 ch

SCI: 3A/D

10-bit8 ch

D/A8-bit2 ch

- SH-3 High-speed Version -

82


Features• Supports DSP instructions (16-bit fixed points)- to 100/160 MHz- to 200/320 MOPS• MMU• Cache: 16 KB• X/Y memory (DSP core)

RAM: 2 × 8 KB (total 16 KB)• LCDC (color)• USB function Ver.2.0 (Full Speed)• USB host (Full/Low Speed),

OHCI: Ver.1.0• AFE interface• Other functions: A/D converter and PCMCIA I/F etc• On-chip debugger- JTAG interface H-UDI (subset)- User break controller (UBC)• Package- HQFP-240- CSP-240

Main applications• Faxes, printer, AV equipment terminal, webphone,

POS terminal, internet terminal, and DSC printer.

SH7727 Overview


RAM X/Ymemory2 × 8 KB

Cache16 KB

USBhost

SH3-DSPcore

TMU32-bit× 3

CMT16-bit× 1

H-UDI

LCDC

BSCROM,SRAM I/FSDRAM I/FBurst ROM I/F

INTC

AFE I/F

CPG/PLL

USBfunction

DMAC4 ch

A/D10-bit6 ch

UBC: 2

SCI: 3

83


SH7720/SH7721 Overview

Features• Supports DSP instructions (16-bit fixed points)- to 133 MHz- to 266 MOPS• MMU• Cache 32 KB• SSL accelerator• X/Y memory (DSP core)

RAM: 2 × 8 KB (total 16 KB)• LCDC (color)• USB function (Ver. 2.0 Full Speed)• USB Host (Full/Low Speed)

OHCI: Ver.1.0• I2C bus interface: • DMAC × 6 channels • TMU: 32-bit timer × 3• TPU: 16-bit timer × 4• SCIF: Serial interface with FIFO × 2• IrDA interface (Ver. 1.0)• SIOF: Audio serial interface with FIFO × 2• Smart Card Interface• AFE I/F• A/D converter 10-bit × 4 ch,

D/A converter 8-bit × 2 ch• PCMCIA I/F, MMC I/F• Package: FBGA-256

(17 mm × 17 mm, ball pitch: 0.8 mm)(11 mm × 11 mm, ball pitch: 0.5 mm)


SH3-DSPCore 4-way

Cache32 KB

InterruptControl

CMT:32-bit × 5

CPG/PLL

PCMCIAcontroller

1 slotMMC, CF

UBC: 2

TMU

TPU

I2C

DMAC6 ch

D/A8-bit

A/D10-bit

SIOF: 2:Audio

CODEC I/F

SCIF: 2

SIM: 1

AFE I/F

X/YMemory16 KB

RTC

SSL*Accelerator

USBFunction

USBHost

LCDC

MMU

BSC

32-bitMultiplier

Main applications• IP Phone, Faxes, Printer, AV equipment terminal, Webphone

POS terminal, Internet terminal, and DSC printer

84

SH7721 is SSL-less version of SH7720

*: only SH7720


SH7729R OverviewFeatures• DSP instruction (SH3-DSP)- 100 MHz/133 MHz/167 MHz/200 MHz- 200 MOPS/266 MOPS/334 MOPS/400 MOPS• MMU- MMU fully compatible with the

SH-3 (TLB)• Cache- Cache fully compatible with the

SH-3 (16 KB)• Built-in memory for DSP processing

(X/Y memory)- RAM: 2 × 8 KB (total 16 KB)• Built-in debugging function- Emulation interface that conforms to

JTAG (H-UDI)- User break controller (UBC)• Package- LQFP-208, CSP-240 (100/133/167 MHz)- HQFP-208 (200 MHz)

Main applications• Network application (VoIP), internet FAX,

webphone, DSC, and TV conference system

SH7729R Block Diagram

D/A8-bit2 ch

RAMX/Y

memory2 × 8 KB

Cache16 KB

SH3-DSPcore

TMU32-bit× 3

BSCROM,SRAM I/FSDRAM I/FBurst ROM I/F

MMU

DMAC4 ch

A/D10-bit8 ch

UBC: 2

SCI: 3

RTC

H-UDI

CPG/PLL

INTC

85


Multimedia SH-4/SH4-A RISC Processor

Features• High performance CPU that enables parallel execution of two instructions

• Ultra-high-speed 3D vector multiplier• Upwardly compatible with SH-1/SH-2/SH-3 instruction sets- 16-bit fixed-length instructions- IEEE754 floating-point instructions are supported(high-speed single precision and double precision)

86


Ultra-High-Speed Floating-Point Operation

FPU Register File2 (× 16)

FMUL FMUL FMUL FMUL

FADD

128 bits

FPU Register File1 (× 16)• 16 multiplications and 12 additions are

executed in four clock cycles

• Loading/storing to other registers duringan operation is possible

FTRV instruction XMTRX, FVn

87

× =a11 a12 a13 a14a21 a22 a23 a24a31 a32 a33 a34a41 a42 a43 a44

xyzi

x'y'z'i'


InstructionB

InstructionC

InstructionD

Features of SH-4

SH-3

SH-4SH-4A

(Superscalar)

Clock

Parallel processing

Executiontime 1/2

Execution time

InstructionA

InstructionB

InstructionC

InstructionD ••••••

•••

•••

- Superscalar -

88

InstructionA


2-Way Superscalar Method

• 2-instruction parallel execution• Improved execution efficiency with simple hardware

Floating-pointunit

Load/store andsimple op. unitInteger unitBranch unit

Instruction queue

Decoder 1 Decoder 2

89


SH7750R Overview

Features• High-performance 2-way superscalar• Operating frequency: 200/240 MHz- Internal power supply voltage: 1.5 V (typ.)• Built-in MMU• Cache: (Harvard architecture)- large-capacity cache:

16-KB instruction + 32-KB data(2-way set associative)

• DMAC: 8 channels• When bus width is 64 bits, 256-Mbit SDRAM

(× 16) is supported• Package:

BGA-256, QFP-208BGA-292 (17 mm × 17 mm, 0.8-mm pitch)

Main applications• Car navigation, image processing,

STB, digital TV, and printer

32-bitmultiplier

BSCROM,SRAM I/F

SDRAM I/FBurst ROM I/FPCMCIA I/F

MPX I/F

I-Cache16 KB

D-Cache32 KB

SH-4 CPU2-way

superscalar

FPU

3DG

CPG/PLL32-bit TMU

SCI

DMAC

MMU

UBC

INTC

RTC

- 2-way superscalar architecture -

90


SH7751R Overview

Features• High-performance 2-way superscalar• Operating frequency: 200/240 MHz- Internal power supply voltage: 1.5 V (typ.)• Built-in MMU• Cache: (Harvard architecture)- large-capacity Cache:


• DMAC: 8 channels• Package:

BGA-256, QFP-256BGA-292 (17 mm × 17 mm, 0.8-mm pitch)

Main applications• Communications- Routers, PBX, LAN/WAN, and NAS• OA/PC peripherals- Printer, scanner, and PPC

32-bitmultiplier

BSCROM,SRAM I/F


MPX I/F

I-Cache16 KB

D-Cache32 KB

SH-4 CPU2-way

superscalar

FPU

3DG

32-bit TMU

INTC

UBC

MMU

DMAC

SCI

CPG/PLL

H-UDI/AUD

RTC

PCIC

- SH-4 on-chip PCI version -

91


SH7760 Overview

Features• High-performance 2-way superscalar• Operating frequency:

200 MHz (Internal)/66 MHz (Bus)- Internal power supply voltage: 1.5 V (typ.)• Large-capacity Cache:


• Peripheral modules- LCDC: LCD controller (640 × 480: 256 colors, etc.)- USB: USB host (Full/Low Speed)- OHCI: Ver.1.0- SCIF, HAC, SSI, I2C, HSPI, SIM, MMCIF,

CMT, A/D Converter, MFI, and GPIO• Package:

BGA-256 (17 mm × 17 mm, 0.8-mm pitch)

Main applications• Car navigation, Telematics

32-bitmultiplier

INTC

BSCROM,SRAM I/F


MPX I/F

I-Cache16 KBSH-4 CPU

2-waysuperscalar

FPU

3DG

UBCMMUDMAC

CPG/PLLH-UDI/AUD

32-bit TMU

D-Cache32 KB

HCAN2I2C

USB(H)RAM

HAC/SSIHSPI/SIM/MMCIF

ADCGPIOMFILCDC

- High-performance processor with on-chip LCD controller and USB host -

92


SH7780 OverviewFeatures• CPU core- CPU core: SH-4A- Operating frequency: 400 [email protected] V• External bus interface (3-bus configuration)

Voltage Bus width Clock frequency- DDR I/F 2.5 V 32 bits 160 MHz- Local bus 3.3 V 32 bits 100 MHz- PCI 3.3 V 32 bits 33/66 MHz• Cache memory/Internal memory- Instruction cache: 32 KB (4-way set associative)- Data cache: 32 KB (4-way set associative)- LRAM(high-speed): 16 KB- Medium-speed RAM: 32 KB• Peripheral modules- DMAC: 12 ch- SCIF: 2- SIOF/SSI/HAC- NAND flash controller- MMCIF• Package:

BGA-449 (21 mm × 21 mm, 0.8-mm pitch)

Main applications• Car navigation, amusement equipment,

network terminals, laser-beam printers

SH-4A400 MHz

Superscalar CPUFPUMMU

32-KB I-Cache32-KB D-Cache

16-KB LRAM

DMAC

WDT/RTC

INTC

CPG

Medium-Speed

32-KB RAM

SCIF/HSPI

Bus interface

DDR-SDRAMcontroller

Local bus,SRAM, MPXPCMCIA, etc.

PCI bus

SCIF/MMCIF

SIOF/SSI/HAC

TMU/CMT

NAND Flash

93


SH7785 OverviewFeatures• CPU core- CPU core: SH-4A- Operating frequency: 600 [email protected] V• External bus Interface (3-bus configuration)

Voltage Bus width Clock frequency- DDR I/F 1.8 V 32 bits 300 MHz- Local bus 3.3 V 32/64 bits 100 MHz

(64-bit width when PCI bus/display unit are not in use)- PCI 3.3 V 32 bits 33/66 MHz• Cache memory/Internal memory- Instruction cache: 32 KB (4-way set associative)- Data cache: 32 KB (4-way set associative)- LRAM (high speed): 8 KB + 16 KB- URAM (middle speed): 128 KB• Peripheral modules- Display unit (DU)- Data translation accelerator (GDTA)- DMAC: 12 channels- SCIF, HSPI, and NAND Flash memory controller- SIOF, SSI, and HAC- MMCIF- H-UDI, high-speed AUD• Package: BGA-436 (19 mm × 19 mm, 0.8-mm pitch)

Main applications• Car navigation systems, amusement devices, network terminals,

LBPs (laser beam printers), etc.

SCIF/HSPI/FLCTL

DMACSH-4A

600 MHzSuperscalar CPU

FPU MMU32-KB I-Cache32-KB D-Cache

8-KB ILRAM16-KB OLRAM128-KB URAM

WDT

INTC

TMU

CPG

SIOF/SSI/HACGDTA

SCIF/MMCIF

Bus interface

H-UDI/High-speed

AUD

DDR2-SDRAMController

Local bus SRAM, MPX, PCMCIA, etc.

PCI Bus/Display Unit

94


Overview of the SH7730Features• High-performance CPU: SH-4A- Operating @ 266/200 MHz

(480/360 MIPS)- On-chip FPU, Support for MMU• On-chip cache memory- Instruction cache: 32 KB- Operand cache: 32 KB• Internal memory: 16 KB (ILRAM)• External bus: 32 bits, 66 MHz- ROM/SRAM- SDRAM• Peripheral modules- DMAC: 6 ch- Various timers (TMU, TPU, and CMT)- SCIF: 6 (IrDA: 2, SIOF: 1)- I2C: 2- A/D converter: 10 bits, 4 ch- D/A converter: 10 bits, 2 ch• Power management function- Sleep module standby- software standby • On-chip debugging• Package:

208-pin QFP (28 mm × 28 mm)

SH-4A

UBC

H-UDI

BSCROM, SRAMBurst ROM

SDRAMPCMCIA

SIM

A/D converter(10 bits × 4 ch)

D/A converter(10 bits × 2 ch)

FPU

MMU

Instruction Cache(4 ways, 32 KB)

Operand Cache(4 ways, 32 KB)

High-speed RAM(16-KB ILRAM)

DMAC (6 ch)

INTC

RTC

RWDT

CPG

SCIF (6)

SIOF

IrDA (2)

I2C bus I/F (2)

TMU (32 bits × 3)

TPU (16 bits × 6)

CMT (32 bits × 5)

I/O Ports


SH7786 OverviewFeatures• CPU Core- CPU Core: SH-4A × 2- Frequency: 533 [email protected] V• External bus Interface- DDR3 I/F: 32 bits width (max.)

: 533 MHz (max.)- Local Bus: 8/16/32 bits width

: 88.9 MHz (max.)- PCI-Express: (4 lane + 1 lane) or

(2 lane + 1 lane + 1 lane)• Cache memory/Internal RAM- I-Cache: 32 KB × 2- O-Cache: 32 KB × 2

: Cache snoop function- LRAM (High speed): (8 KB + 16 KB) × 2- L2Cache: 256 KB• Peripheral module- Display Unit (DU): 1 ch (max.)- USB2.0 High speed: 2 ch (max.) (Host/Function)- Ethernet Controller: 1 ch (max.) (MII Interface)- DMAC: 24 ch (max.)- SDIF: 2 ch (max.)- SCIF: 6 ch (max.)- I2C: 2 ch (max.)- HSPI, SSI, HAC, NAND controller, H-UDI, AUD• Package: BGA-593 (25 mm × 25 mm: 0.8 mm pitch)

Main Application• Car navigation, amusement device, Network terminals

UnderDevelopment

PCI-Express

SH-4A533 MHz

Superscalar CPUFPU MMU

32 KB I-Cache32 KB O-Cache

8 KB ILRAM16 KB OLRAM

SH-4A533 MHz

Superscalar CPUFPU MMU

32 KB I-Cache32 KB O-Cache

8 KB ILRAM16 KB OLRAM

SCIF SCIF/SD

SCIF/I2C SCIF/SSI

SCIF SCIF

H-UDI/AUD

SD/HAC/SSI

L2CacheINTCCPG

TMU

DMACWDT

GPIO

DU/EtherC/HSPI

USB2.0High speed

HostFunction

Bus Interface

DDR3-SDRAMcontroller

Local BusSRAM, MPX,PCMCIA etc.


SuperH for Car Infotainment System

97


Roadmap of SH-4/SH-4A Product for CIS

98

2003 2004 2005 2006 2007 2008 2009 2010 2011430 MIPS

SH77xx***

SH-NaviX***

SH7764324 MHz, Ether,2D, SDRAM I/F

404 pins

SH7760(BL)200 MHz, LCDC

256 pins

SH7760200 MHz, LCDC

256 pins

Aunar200 MHz, 2DG

480 pins

SH7770(SH-Navi1)

400 MHz, 2D/3D, GPS520 pins

SH7774(SH-Navi2V)600 MHz,

Image recognition, 2D,AAC encoder

554 pins

SH7786*533 MHz ×2,

PCI-e, 593 pinsSH7785600 MHz, PCI

436 pinsSH7780

400 MHz, PCI449 pinsSH7750R/51R

240 MHz, PCI256 pins

SH-4A Dual

>1000 MIPS720 MIPS

Under developmentUnder planningUnder consideration

******

SH77721(SH-NaviJ1)*

333 MHz, Map and GUI Drawing

440 pins

SH7776(SH-Navi3)*

533 MHz × 2,2/3D Processor/3DImage recognition,

PCI-e, 653 pins

SH-4A Dual

Scalable Solution

Compact Solution

High grade Integrated Solution

200 MHz 400 MHz 600 MHz Multi CPU

SH7775(SH-Navi2G)

600 MHz, 2/3D Processor/3D

GPS, 560 pins


SH7770 for Full Graphics Display Type In-Vehicle Terminal

99

• All-in-one chip with graphics accelerator• Introduction of 400-MHz SH-4A core realizes the high performance of

processing

Bus architecture that demonstrates system performances

System solution including graphics and IP

Effective use of software assets

Consistent evolution of SuperH core

AbundantIP lineup

Use of Collected

know-hows


Display Example of SH7770 2D/3D Graphics

* 3D graphics IP from Imagination Technologies, Ltd. of the United Kingdom is used as the on-chip 3D graphics engine

• SH7770 have an exclusive accelerator of 2D/3D individually.

Menu

Menu

Menu

2D Graphic

e.g.) Map-Drawing

3D Graphic

True-color blending

Translucency and reflections

Bumpmap


SH7770 Overview

101

SH7770Features• Max. internal operating frequency of SH-4A core:

400 MHz• Power supply voltage:

3.3 V (I/O), 2.5 V (DDR), 1.25 V (core)• Performance:

720 MIPS (Dhrystone) @400 MHz• 2-way superscalar, 7-stage pipeline • Cache:

32-KB 4-way set associative (I-, O-cache)• Memory: DDR SDRAM I/F• 2D Graphics Engine• 3D Graphics Engine• Display:

WVGA 854 dots × 480 dots (16-bit pixel)• Peripheral functions:

Please refer to the diagram at right.• Package: BGA-520 pins

(33 mm × 33 mm, 1.0-mm pitch)

UBC MMU

INTC

EX-Buscontroller

SH-4A400 MHz

32-KB I-cache

32-KB O-cache

DDR-SDRAMcontroller

WDT

3DGraphics

USB (H/F)

A/D converter

GPS

ATAPI

Video In

YUV

Display Out

2DGraphics

CPG

DMAC HCAN2

Remotecontrol

PWM

RTC

SCIF

TMU

I2C

SSI

SRC

SPDIF

HAC

HSPI

FPU


SoC SH-Navi2G “SH7775”for Car Navigation System

Product concept

High performance SoC equipped with Map and GUI Graphics Processor,3D Graphics Engine, and various function for car navigation system.

External memorySH-Navi2G (SH7775)

1. SH-4A CPU core operating at 600 MHz with 50% increase of current Renesas SoC products

2. Newly developed on-chip Graphics Processor optimized for Map and GUI Drawing and 3-D Graphics Engine.

3. Comprehensive range of peripheral functions for car information systems

High-Performance

SH-4Acore

ComprehensivePeripheralModules

Map and GUIDrawing

Processor and

3D Graphics

SH-4A600 MHz

MemoryController

Map and GUIDrawingGraphics

Processor

3DGraphicsEngine

GPS B/BATAPI

USB 2.0RCAN

TS-IF


SH7775 OverviewSH7775

Features• Max. internal operating frequency of

SH-4A core: 600 MHz• Power supply voltage:

3.3 V (I/O), 1.8 V (DDR), 1.1 V (Core)• Performance:

1080 MIPS@600 MHz• Cache:

32-KB 4-way set associative (I-, O-cache)• Memory: DDR2 SDRAM I/F• Renesas Graphics Processor (2D, 3D)• 3D Graphics Engine• Display:



(25 mm × 25 mm)

DDR2-SDRAM

Controller

DMAC

32 KBO-cashe

32 KBI-cashe

UBC MMU

FPU

SH-4A600 MHz

3DGraphics

GraphicsProcessor(2D/3D)

INTC

CPG

ATAPI

Video In

Display Out

RCAN

SCIF

TMU

Debug

GPIO

USB2.0(H/F)

SSI

HSPI

GPS

TS-IF


SoC for Car Navigation SystemSH-Navi2V “SH7774”

Product concept

High performance SoC equipped with the image recognitionprocessing function and various function for car navigation system.

External MemorySH-Navi2V (SH7774)

1. World’s first on-chip image recognition processing IP in a car navigation SoC.2. 600 MHz SH-4A CPU core enabling implementation of high-performance systems

for the next generation.3. Comprehensive range of peripheral functions for next -generation in-vehicle

information terminals.

AudioEncoder

2DGraphicsEngine

DISPLAY

VIDEO IN

SH-4A600 MHz

ImageRecognition

MemoryController

High-Performance

SH-4Acore

2D Graphics and

ComprehensivePeripheralModules

ImageRecognition





3.3 V (I/O), 1.8 V (DDR), 1.1 V (Core)• Performance:1080 MIPS@600 MHz

• Cache: 32-KB 4-way set associative (I-, O-cache)

• Memory: DDR2 SDRAM I/F• 2D Graphics Engine• Display:



(29 mm × 29 mm)

DDR2-SDRAM

Controller

DMAC

32 KBO-cache

32 KBI-cache

UBC MMU

FPU

SH-4A600 MHz

INTC

CPG

ATAPI

Video In(2 ch)

Display Out

RCAN

SCIF

TMU

Debug

GPIO

Ethernet

SSI

H/SPDIF

ImageRecognition

2DGraphics

AACEncoder


SH-Navi2V “SH7774” Image RecognitionEngine

106

ImageRecognition

Engine

Video In

SH-4A 600 MHz

The seamless process is available between CPU and Image Engine

Camera

Processing result of Lane Recognition by SH7774

Image Application

Software

NavigationSoftware

SHwy

2D

DDR600MCU

Brid

ge


SoC for Car Navigation System SH-Navi3“SH7776”

Product concept

High performance SoC equipped with SH-4A dual core for High-endcar navigation system.

External MemorySH-Navi3 (SH7776)

1. Dual high-performance SH-4A CPU cores for superior processing power of 1920 MIPS2. On-chip Graphics Processor optimized for Map and GUI Drawing and 3-D Graphics Engine achieving

high-speed and wide variety of drawing function.3. Comprehensive range of peripheral functions for car information systems such as Image Recognition

processing IP and Wrapping Correction module.4. On-chip DDR3-SDRAM memory interface, Serial ATA interface, and PCI Express interface for

ultrahigh-speed data transfers

Map and GUIDrawingGraphicsProcessor

3DGraphicsEngine

SH-4A533 MHz

DDR3Memory

Controller

SH-4ADual Core

Ultrahigh-speedData Transferby DDR3 and

SATA

ImageRecognition

Map and GUIDrawing

Processorand

3D Graphics

ImageRecognitionand WarpingCorrection

SH-4A533 MHz

Serial ATA

GPS B/B

PCI Express

USB2.0

SD Card Host




SH-4A core: 533 MHz × 2• Power supply voltage:

3.3 V (I/O), 1.5 V (DDR), 1.25 V (Core)• Performance:1920 MIPS (Dhrystone)@533 MHz

• 2-way superscalar, 7-stage pipeline• Cache:

32-KB 4-way set associative (I-, O-cache)• Memory: DDR3 SDRAM I/F• Renesas Graphics Processor (2D, 3D)• 3D Graphics Engine• Display:

WXGA 1280 dots × 768 dots (16-bit pixel)• Peripheral functions:


(25 mm × 25 mm, 0.8-mm pitch)

DDR3-SDRAM

Controller

CPG

SH-4A533 MHz

HSPI

GPS

SSI

I2C

TMU

RCAN

SPDIF

SRC

ImageRecognition

3DGraphicsGraphicsProcessor(2D/3D)SH-4A

533 MHz

DMAC

INTC

WDT

EX-BusController

PCIexpress

WarpingCorrectionVideo In(3 ch)

Display Out(2 ch)

SD CardHost (2 ch)

A/Dconverter IF

SATA

USB2.0(H/F)

PWM

RemoteControl

TS-IF

SCIF

DARC


SH-Navi Series Roadmap (Entry-High-End)

2008 2009 2010

Entry

Mid

HighSH-Navi series

Bus architecture

Softwarescalability

SH-Navi2V600 MHz,

2D/Image recognition600 MHz,

2D/3D

SH-Navi2G

SH-Navi1400 MHz,

2D/3D

SH-Navi2V600 MHz,

2D/Image recognition600 MHz,

2D/3D

SH-Navi2G

SH-Navi1400 MHz, 2D/3D

SH-NaviJ*Series

333 MHz, 2D/3DSH77721

* : Under Development

SH-Navi3*

533 MHz × 2, 2D/3D,Image recognition,

PCI-e SH-Navi3*533 MHz × 2, 2D/3D,Image recognition,

PCI-e


New SoC SH-NaviJ1 “SH77721” for Low-Endto Middle-Range Car Navigation Systems

1. The optimized specification for an entry CIS model• Enhanced Renesas Graphics Processor• USB 2.0 High speed• Add SD Card host Interface• CPU 333 MHz, low power consumption• Smaller package

2. Save the software development cost• Software scalability can use software property of SH-Navi series,(e.g. common 2D Graphics and peripheral modules)

3. Save the external SDRAM cost.

666 MB/s

SDRAM I/F of SH-NaviJ1SDRAM I/F of SH-Navi1

1600 MB/s

DDR1 (×16) 4 pcs (64 bit bus) DDR2 (×16) 1 pcs (16 bit bus)


SH77721

DDR2-SDRAM

Controller

DMAC

32 KBO-cache

32 KBI-cache

UBC MMU

FPU

SH-4A333 MHz

INTC

DARC

A/Dconverter

Video In

USB2.0(H/F)

RCAN

SCIF

TMU

Debug

GPIO

GPS

I2C

HSPI

GraphicsProcessor(2D/3D)

SD cardHost (2 ch)

SSI

Display Out




599 MIPS @333 MHz• Cache:

32-KB 4-way set associative(I-, O-cache)

• Memory: DDR2 SDRAM I/F• Renesas Graphics Processor (2D/3D)• Display:



(23 mm × 23 mm)

SH77721 Overview


“SH77650” Specialized SoCfor Automotive Image Recognition Processing

112

VIDEO IN

DISPLAY

1 chip solution for image recognition system

1. High-performance image recognition processing IP2. SH-4A CPU core operating at 300 MHz to enable actualization

of high-performance systems3. A variety of peripheral functions for automotive image recognition applications

Product concept

High-Performance

SH-4Acore

ImageRecognition

External MemorySH77650

SH-4A300 MHz

ImageRecognition

MemoryController


SH77650

SH77650 Overview

113




540 MIPS@300 MHz• Image recognition engine• Cache:

32-KB 4-way set associative (I-, O-cache)• Memory: DDR1 SDRAM I/F• Internal RAM 256 KB• Peripheral functions:


(19 mm × 19 mm)

DDR1-SDRAM

Controller

DMAC

32 KBO-cache

32 KBI-cache

UBC MMUFPU

SH-4A300 MHz

INTC

CPG

Display Out

RCAN

SCIF

TMU

A/Dconverter

ImageRecognition

I2C

H-UDI/AUD

WDT

Video In

SSIBoot


SuperH RISC engine System Application

114


Configuration Example of the Cable Modem

10/100 M Ethernet

Receive unit

SDRAM

Cable

FLASH

LED

SCI

MAC

SuperHSH7615*

SH7729R MAC

PHY

Transmit unit

*: SH7615 incorporates Ether MAC.

CableTuner

QAMDemod FEC

R-SEncode

QPSKModFilter

115


Configuration Exampleof the AC Servo Control System

AC motor

2-phase encoderinput

MTU2 (16-bit timer)

ROM512 KB

RAM32 KB

SH7211

Encoder

Communicationwith high-end CPU

Base driver

S

M


SCIF × 4

3-phaseAC supply

6-phase PWMoutput

MotorCurrent

detection

Pulse train input

IGBT module

116


General-Purpose Inverter:Example of System Configuration

High-versatility motor controlDual motor control by timers MTU2 and MTU2S

Inclusion of high-precision 12-bit A/D converterGreater precision of sensor measurement

General-purpose inverter

Motor

Abundant communications functionsSCI × 4, SCIF, IIC, SSU

Host PC

I2C

SCI

3-phasePWM output

3-phasePWM output

EEPROM

Sub MCU

SH7280

SH-2ACPU

(100 MHz)

peri-pheral

I/F

Flash:1 MB

RAM:32 K

USB function

MTU2

MTU2S

12-bitA/D

converter

A/D input

Input ofvarious sensors

On-chip USB controllerInterface to a host PC

High-precision and high functionality inverter system can be realized by enhanced-performance SH-2A CPU core, large-capacity flash memory with up to 1 MB, and timers(MTU2 and MTU2S) for motor control.USB controller is also included, which enables interface to a host PC.


- Controlling the external unit of air conditioner with a single chip -Application Example Using the SH7149

MTU2(Inverter control)

SH7149

SH-2 80 MHz


Base driver

6-phase PWM output

Electric current detection

MTU2S(Inverter control)

Base driver


POE

POE

10-bit A/D converter Sensor information

Compressor

MFan motor

Communication to the internal unit

SCI

Error detection signal M

3-phase inverter 6-phase PWM output

Shunt resister

Error detection signal

3-phase inverter

Shunt resister

Outside temperature Humidity

• •

• •


Configuration Example of the Page Printer System

PC/workstation

SH7709S, SH7750R, SH7780

Communicationcontroller• Parallel interface• Ethernet• Local talk etc

Receiving buffer

LBP engine

Video signal

Multiplier

SynchronousDRAM( )

ASIC

Font ROMPagememory

Mask ROM/flash memory 16 M SDRAM

CPU Cache

Peripheralfunction

DRAM

Motorcontroller

Lasercontroller

8-bit microcomputer

ASICRaster processor• Raster operation• Parallel to serial

conversion

Program ROM

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Configuration Exampleof the Compact Printer System

SH7705

Flash ROM

SDRAM

ASICPrinter engine

CCNSH-3CPU

CACHE32 KB

MMU

TLB

INTC

CPG

UBC

AUD

BSC

DMAC

External busInterface

TMU

TPU

RTC

CMT

SCIF/IrDA

SCIF

USB

H-UDI

I/Oport

ADC

Internal bus

CPU

bus

Peripheral bus

Stores the user program,high-speed JPEG middleware,and JPEG image data

PWM OUT

IrDA Communication

USBCommunication

Mobile phone

Key input

Batterymonitor

Key board

Battery

PC

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Configuration Example of thePortable Information Terminal System

CODEC

ROM SDRAM

SH7720

Color LCDC PCMCIAcontroller

USBhost

USBfunc

CODECinterface

STN/DSTN/TFT LCD

320 × 240Voice

CF card

Printer

PC Touchpanel

Battery

Music


Gateway Configuration Example Using the SH-4

10/100baseT

10/100baseT

HUB

IEEE802.11a,

etc.

PCI

SH7751R 240 MHz

IEEE802.11b

Companion chip

MD3306, etc.

SDRAM

FLASH

Storage function enhanced example

16-bit product × 2

FTTH/ADSL

PDA

PC

SH-4 core: 430 MIPS Cache: 16 KB + 32 KB

On-chip high-performance FPU

PCIC PCMCIA BSC

Linux OS

Low-cost PCIconnection chip

can be used

- FTP 80-Mbps transfer- Software IP sec enabled

- VolP achieved by using the FPU

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Example of SH7785 Application (Home Server)

SIOF CODECLANC

PCI Bus

USB

InterNet

CardBus

802.11a/b/g

MobileIP-Phone

DSC

PC

PC

HDD(iVDR)/DVD

TV DVD Rec

PrinterHomeNetwork

(EtherNet)

SCIFZigbeeorPLC

HomeElectronics

Car AudioCar Navigation

iVDR

Web CAM

Encryption

Encryption DDRPCIC

SH7785@600 MHz

LANC S-ATA

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Example of Car Navigation Systemwith SH7770

124

Fruitful peripheral interface with the separated bus structure.Improvement of the cost performance by one-chip solution.

UM(DDR-SDRAM)

Flash,SRAM

Ex Bus (32 bits)Bus Bridge DMAC: 32 ch

Mid

spe

ed b

us (

100

MH

z, 3

2 bi

ts-1

28 b

its )

Low

spe

ed b

us (

50 M

Hz,

32

bits

)xxkm

DDR- BUS (100 MHz, 64 bits)

DVD

SH-4A 400 MHz CacheI: 32 KB, O: 32 KB FPU

ATAPI

USB

Video In

2D Graphic

DisplayControl

3D Graphic

Memory cont.

Hig

h Sp

eed

Bus

( 200

MH

z, 6

4 bi

ts )

SSISPDIF

GPS B/B

HCANSCIF

I2C

Audio Codec I/F

GPSIrDASensors

AudioCodec

HDD

SuperH RISC engine Family - BIS-EL

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