New Ideas for New Materials

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stress migration control in copper (Cu) interconnects, Cubarrier integrity, and Cu electroplating and chemical-mechanical planarization (CMP).

New materials and processing technologies are contin-uously being evaluated and introduced to resolve theseissues. These include metal compounds and alloys,multilayer films and ultrathin atomic layer deposition(ALD) films (Figure 1). The introduction of these newmaterials has given rise to new process control para-meters. In addition to measuring film thickness, controlling the composition (stoichiometry) of these

Inline Process Control of Advanced ThinFilms at 65 nm and Beyond

Murali Narasimhan, KLA-Tencor Corporation

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IntroductionIC manufacturers worldwide are currentlyproducing devices at the 130-nm node with90-nm-generation products in pilot produc-tion, and 65-nm and 45-nm processes underdevelopment. Several process and integrationissues identified at the 130-nm node havebeen resolved. However, the 90-nm genera-tion has several unique problems remainingto be solved. Some of the issues that still needresolution include high leakage currents ofgate dielectrics, electromigration (EM) and

Figure 1. A key trend emerging in the semiconductor industry is the proliferation of new CMOS materials. At the 130-nm node, one

could find approximately 20 possible materials in use. By the 65-nm node, the list of materials is expected to grow to 34 or more,

with such new additions as silicon-on-insulator (SOI) and silicon germanium (SiGe) substrates, ultra-low-k dielectrics, hafnium oxide

(HfO2) and silicon oxynitride (SiON) gates, and atomic layer deposition (ALD) barrier and seed layers.

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Thin film challenges foradvanced technologynodesCu Barrier Cu barrier layers form an importantpart of the Cu interconnect byensuring that Cu does not diffuseinto the dielectric and cause line-to-line leakage or early timedependent dielectric breakdown(TDDB) failures, and create dark-level defects in the silicon substrate.The effective line resistance of Cuinterconnect increases with thethickness of the barrier layer. Inorder to maintain effective conduc-tor resistivity below 2.2 µm-cm atthe 90-nm and 65-nm technology

nodes1, barriers need to be ultra-thin, so that they con-sume less than 15 percent of the trench cross-section.Barrier thickness needs to scale from 16 nm at the 130-nm node all the way down to 70 nm for the 65-nmnode (ITRS Roadmap 2002).

Physical vapor deposition (PVD) continues to be aviable technology for barrier deposition at the 90-nmnode and can be extended to 65 nm as well2. However,PVD will not be adequate for the growth of pinhole-free conformal barriers on porous via and sidewalltrenches, which requires better control over the barrierdeposition process3. Barriers for technology nodes atand beyond 65 nm are currently being explored, with the most promising candidates being tantalum(Ta)-based ALD barriers, TiSiN metal organic chemicalvapor deposition (MOCVD) barriers and tungstennitride (WNx)-based chemical vapor deposition(CVD)/ALD barriers. MOCVD TiN has been reportedto offer better long-term reliability than Ta; however, itexhibits poor adhesion to low-k dielectrics and poor Cuwetting. The search for new barrier materials is alsodriven by the interfacial behavior between the barrierand porous low-k materials that may be introduced atthe 45-nm node.

Cu barrier process challengesAlthough PVD and CVD technologies have beenaround for many years and are well understood, thereare several parameters that need to be controlled inorder to obtain consistent on-wafer results, such as filmcomposition, step coverage, uniformity, stress, anddefectivity.

advanced thin films is recognized to be crucial for theirsuccessful implementation and integration into IC processing schemes. As feature sizes shrink, smallerdeviations in film thickness or composition, if unde-tected, could lead to short-term functional yield lossand long-term reliability issues. Regular monitoring of film composition and thickness during productionwill be necessary to alert IC manufacturers to excursionsin the process that could potentially affect reliabilityand yield (Figure 2). Therefore, an additional burden is being placed on metrology tools to measure andcharacterize new film properties during process devel-opment and to provide a solution for inline monitoringin production.

A promising new technology in the form of electronstimulated X-ray (ESX) metrology is now available onKLA-Tencor’s MetriX 100™ opaque films metrologysystem, and can be used to measure thickness and composition of a wide variety of films on product wafers.The technology is derived from electron probe micro-analysis (EPMA), which has been widely used in mate-rials analysis. MetriX 100 has been designed for bothprocess development and fast in-line production moni-toring through advances in electron-beam columns, X-ray detectors and modeling algorithms combinedwith 300 mm full-fab automation, vacuum wafer handling, and pattern recognition, and a field-provenuser interface for production metrology environments.

This paper explores the process control issues of advancedmaterials for the 90-nm and 65-nm nodes, the metrologychallenges associated with these issues, and the viabilityof the new ESX technology as the solution to these issues.

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Figure 2. Compound films will increasingly be used at sub-90-nm nodes, and new parameters have

emerged for films process control, including composition, density, and porosity. Film composition, in

particular, has materialized as a critical process control parameter in both the front-end-of-line transis-

tor processing area as well as the back-end-of-line copper interconnect processing area, as uncon-

trolled changes in film composition result in short-term functional or long-term reliability failures.

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Copper damascene interconnect reliabilityAs Cu interconnects mature, various reliability issuesand failure mechanisms of Cu interconnect are beingdiscovered and understood. The most significant relia-bility issues for Cu metallization are stress migrationand EM.

Stress migrationStress migration in Cu interconnect structures (Graphic 1)is primarily caused by two conditions:

a. Vacancies at Cu grain boundaries and micro voids arecreated during electroplating due to discontinuousbarrier and Cu seed layer.

b. Post-deposition anneals and highchip operating temperatures createconditions for these vacancies to movefrom low stress areas to higher stressareas to equilibrate stress gradientsand cause larger voids at areas withstress concentration.

These problems are further exacerbatedby large differences in the coefficient ofthermal expansion (CTE) of Cu, barrier,and dielectric materials. Void forma-tion at the via bottom has been report-ed as the most frequent failure modedue to extensive tensile stresses gener-ated at the bottom via corner due tothermal cycling1.

ElectromigrationIt has been reported that EM lifetimes drop aslinewidths narrow and barriers become thinner5. EMfailures occur as a result of Cu diffusing rapidly at theCu/barrier interface and between the Cu/silicon nitride(SiN) cap interface due to the “electron wind force”created by high current density in Cu interconnectlines. Cu/barrier interface boundaries have limitedadhesion because they lack real metallurgical or chemi-cal bonding. Bi-layer barriers such as tantalum/tanta-

lum nitride (Ta/TaN) may be requiredto provide good interface bonding inorder to improve EM lifetime (seeFigure 3, page 4). Additionally, barriercomposition (percentage nitrogen inTaN) can affect interfacial diffusion ratesof Cu, adversely impacting EM lifetime.Thinning the barrier at the base of thevia moves the EM failure mode fromthe via to the line, where the lifetimesare much longer. The composition ofthinner barriers has a more significanteffect on diffusion properties, interfacialadhesion and film stress—all of whichaffect EM (Graphic 2). Barrier composi-tion is currently measured duringdevelopment using analytical techniquessuch as Auger spectroscopy andRutherford Back Scattering. Once a process is optimized and transferred

to volume production, composition is rarely, or never,checked unless there is an issue.

Graphic 1. Improper barrier composition and thickness can cause early stress migration failures

at the Cu interface.

Graphic 2. Reliabili ty failure mechanisms of Cu interconnect tied to Cu barrier/seed fi lm

thickness and composition.

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Process and hardware design variables that could affectfilm parameters in an ionized PVD plasma chamberinclude gas flow, process pressure, gas distribution, RFand DC power levels, magnet design, target design,shielding around the plasma and bias voltage and fre-quency on the wafer. These variables control the extentof the plasma ionization or ion density, ion energy, and

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ion flux—all of which determine the direction of theions during the sputtering process and influence filmproperties and step coverage.

In CVD reactors, the deposition parameters that needto be considered are chamber pressure, wafer tempera-ture, gas flow rates, flow path of the gases across the

wafer, gas compositions and ratios, andthe role of any reaction byproducts.Using plasma in the process introducesadditional variables, such as the ion-to-neutral flux ratio, the ion energy andthe RF bias on the wafer—all of whichaffect film parameters and step coverage.

Barrier composition has emerged as animportant parameter that must be moni-tored during production. As the barriersbecome thinner, their compositionplays a larger role in their functionality(Figure 3). Changes in composition canaffect diffusion properties, interfacialadhesion and film stress—all of whichaffect stress migration and EM resistancealong with TDDB in Cu interconnects.

Figure 3. Cu barrier composition must be monitored in production. Changes in composition

can affect barrier functionality.

Cu barrier metallurgical challengesThe Cu interconnect barrier should ideally bond firmlyto both the Cu and oxide, while offering adequate dif-fusion resistance to the Cu. Barrier breakdown causes asharp increase in line-to-line leakage currents due toCu diffusion, with the added problem of time-depen-dent-dielectric breakdown (TDDB). There is usually atrade-off between barrier integrity and itsadhesion properties (Graphic 3). Ta has a hetero-epitaxial relationship with Cu andforms a thin amorphous layer at the Cu/Tainterface. This results in better adhesion andseed layer properties. It suppresses stress-induced voiding by reducing the number ofinterface defects that can act as void nucleationsites2. TaN, on the other hand, has demon-strated excellent adhesion to silicon oxide(SiO2)-based inter-layer dielectrics (ILDs).Being an amorphous film, TaN also suppressesCu migration along the grain boundaries, aleading cause of interconnect failure. Anotherconsideration for a good barrier is its electricalresistivity. Ta, in its β phase, has a resistivityof 150-200 µohm-cm, while thin film PVD TaN has a higher resistivity of

200-250 µohm-cm. CVD or ALD TaN can have muchhigher resistivity (500–1000 µohm-cm) due to thepresence of impurities such as C. The combined bene-fits of Ta and TaN to maximize adhesion and diffusionresistance with lower in-plane resistivity has led to theconsideration of the Ta/TaN bilayer barrier for highyielding, reliable, EM-resistant Cu interconnects10.

Graphic 3. Barrier and cap layer failures due to uncontrolled changes in composition

result in electromigration-induced reliability failures.

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Incorrect barrier composition can also result in high viaresistance due to changes in the resistivity and contactresistance of the barrier, thus degrading parametricyield.

Conventional metrology techniques do not offer a wayto measure composition, and, as a result, IC manufac-turers are literally flying blind in production, withrespect to controlling the composition of Cu barrierlayers. Techniques such as four-point probe sheet resis-tance or photo-acoustic metrology no longer workeffectively because they are unable to separate the indi-vidual layers of the bi-layer barrier. Nor can they mea-sure under Cu seed layers on product wafers. Promisingnew techniques, such as X-ray reflectivity (XRR),require very complex modeling algorithms and curvefitting. XRR also lacks the small spot size required forproduct-wafer monitoring.

Identifying a method that is capable of monitoring Cubarrier composition inline is therefore essential, as itoffers an early warning system for potentially expensiveIC reliability failures in the field.

Ultrathin ALD barriersTo move beyond the 65-nm technology node, ultrathinbarriers are required to minimize the barrier’s impacton line-to-line and via resistivity. It is believed thatbarriers can be thinned to as low as 10-20Å and stillprovide adequate protection against Cu diffusion intothe dielectric region1. Significant improvement in lineresistance has been observed using PVD and CVDtechniques, when the via bottom coverage was mini-mized. To achieve this improvement with conformal

sidewall coverage, IC manufacturers are beginning toexplore ALD technology for barrier deposition for the65-nm and 45-nm nodes (Figure 4). ALD has thecapability of providing conductive films at low temper-ature, with excellent step coverage, low defect densityand contamination, and good thickness uniformity andthickness control3. Ultra-thin ALD barriers can provide100 percent step coverage with less than 15Å thicknessand less than 3 percent, 1-sigma non-uniformity.Evaluation of diffusion properties has shown that even10Å of ALD TaN is a better diffusion barrier than 50Åof PVD TaN barrier. Hence, an ALD TaN barrier canreduce via resistance by up to 40 percent and line resis-tance by up to 25 percent, resulting in a significantreduction in RC delay4. Other applications of ALDinclude the tungsten (W) nucleation layer and electrodefilms in memory structures.

ALD process control challengesUltra-thin barriers are deposited in ALD reactors byalternately flowing reactant gases in short durationpulses that lead to the monolayer adsorption of reactantspecies followed by reaction on the substrate surface toform the desired film. The complexity of controllingthe ALD process is similar to that of a CVD reactor asoutlined in the previous section. In addition, gas pulseconditions and pulse time cycles in ALD reactors haveto be controlled very accurately to ensure optimalmonolayer formation and reaction. Also, the ALDprocess suffers from a variable incubation time in thereactor that can lead to fluctuations in film thickness inproduction. Surface cleanliness can change the chemistryat the interface leading to excursions in composition.Due to their atomic scale thicknesses, ALD films aremore sensitive to changes in thickness and compositioncompared to thicker films produced by PVD and CVDtechniques. Changes in film properties can seriouslyimpact device performance and must be carefully monitored in production. Ultimately, good barrier performance at every location in the device can only be guaranteed through thickness and compositionaluniformity inside the trench structures across the wafer.

Currently, the ALD process does not have a good metrol-ogy technique available for process control. Conventionalfour-point sheet resistance measurement puncturesthrough the ultra-thin ALD films and cannot be usedfor monitoring an ALD process. X-ray reflectivity canbe used to determine film thickness, but has poor signal-to-noise for high throughput measurements andsuffers from a large spot size for production monitoring.Optical techniques suffer from the problem of correlated

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Figure 4. The dark thin outline in this micro photograph represents

seven separate layers of materials deposited one layer at a time, with

a total thickness of approximately 210Å. The structure is a very high-

aspect ratio trench, and yet robust 100% conformal coverage of the

film is achieved without any buildup in the corners nor blockage of the

trench. Source: ALD2001, May 2001

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changes in thickness and optical properties for ultra-thinfilms and cannot be used to measure a barrier/seed layerfilm stack on product wafers under an opaque Cu seedlayer. Opto-acoustic techniques rely on propagation of asonic pulse through the film reflecting off the interface,and the transit time in an ultra-thin film is too smallto be detected reliably by available instruments.

ElectroplatingElectroplating is currently the process of choice for filling vias and trenches for copper interconnect fabri-cation. It will continue to be used for the 90 nm and 65-nm nodes due to its ability to uniformly andadequately fill narrow and high aspect ratio trencheswithout pinch-off at the top of the trench.

Electroplating process control challengesThe electroplating process typically uses an acceleratorand suppressor in the form of a short or long-chainpolymer to provide bottom-up fill in small vias andtrenches. Surface topography control during the electro-plating process is a key issue, since the additives requiredto ensure filling often result in so-called “super-filling,”where the thickness of the overburden of Cu is higheron densely patterned areas (Figure 5). Super-filling leadsto residual metal in the field areas due to non-uniform

removal during Cu CMP, especially indense patterned areas.

Another important parameter, globalplating thickness uniformity, dependson being able to deliver adequate cur-rent uniformly across the wafer duringplating, especially to the center of thewafer. This is a more significant issuefor larger wafers and thinner seed layersdue to the higher resistance that resultsin a drop in the plating over-potentialat the wafer surface, affecting localdeposition rates. Employing higherplating currents could result in thickerCu deposition at the electrode contactpoints, leading to residual metal orflaking during the CMP step.

Thickness and uniformity measure-ments of Cu after plating are currentlycarried out using either a contact sheetresistance method or non-contactmethods such as opto-acoustic or X-rayfluorescence. A non-contact method of

measuring Cu thickness also needs to have high spatialresolution to be able to measure die-level microvariationsof thickness due to super-filling and more global varia-tions across the wafer and very close to the edge of thewafer. A large variation in the plating current at theedge can cause a thick “edge bead” of Cu, which cancreate difficulty during CMP removal by leading toover-polishing in the center of the wafer.

Voiding of vias and trenches continues to remain anissue for electroplating due to aging of the electroplatingbath and changes in the concentration of additivescaused by the degradation effects of time and tempera-ture on the organic long-chain polymers. As featuresizes continue to shrink, voids in the vias and trenchescan migrate to the interfaces and increase the chancesof EM and stress migration failures in the Cu intercon-nect5. Therefore, it is crucial to detect sub-surface partial voids to offer an early warning system for reliability failures. Random voiding of trenches andvias, especially in known problematic structures, can bemonitored in production using electron-beam inspectionof a via chain array in a test structure.

Alloying elements such as tin (Sn) are being tried outat the 65-nm node to improve the EM resistance of Cuinterconnects, although it comes at the cost of increased

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Figure 5. “Super-filling” arises where the thickness of the overburden of Cu is higher on densely

patterned areas.

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Figure 6. Cu CMP process control is mainly focused on reducing topography caused by dishing of large features and dielectric erosion in dense arrays.

line resistance. Composition measurement and controlof the Cu alloy will become critical to achieve thedesired EM resistance while maintaining the resistanceof the Cu lines.

Cu CMPChemical mechanical planarization (CMP) of Cu is theonly viable approach for removing copper and barrierfrom the field areas after plating to leave copper-filledtrenches forming the interconnect. Although Cu CMPwas introduced at the 0.18 µm-node, it remains a rela-tively immature, highly empirical process, dependenton quality and stability of the consumables used in theprocess. Cu CMP process control issues and challengesare exacerbated at 90 nm and below due to increasingmetal line density and shrinking dimensions of theinterconnect.

Cu CMP process control challengesWhile there are several issues associated with Cu CMP,process control is mainly focused on reducing topographycaused by dishing of large features, dielectric erosion indense arrays, excessive metal loss due to over-polishing,or residual metal due to under-polishing (Figure 6).

Dishing and erosion result in copper loss in the lines and,hence, an increase in the sheet resistance. Additionally,topography generated at the lower metal layers carriesover to the upper levels and creates copper pooling thatdoes not clear even after long overpolish6. This issue ismore challenging as the number of metal levels contin-ues to increase to as many as 10 for advanced technologynodes. Beyond 90 nm and 65 nm, post-CMP topographycould also impact depth of focus during the dielectriclithography step. For the 65-nm node, the ITRS Roadmap2002 (page 75) requires erosion of a 50 percent metaldensity array to be less than 13 nm, and dishing of 100

µm lines to be less than 19 nm in order to maintainthe required sheet resistance of the Cu interconnects.

Cu CMP involves the use of several consumables, suchas slurries, pads, pad conditioners, corrosion inhibitorsand cleaning chemistries that add variables to theprocess. Changes in slurry composition, agglomerationor settling of abrasives and variations in oxidizer dos-ing can cause significant drift in dishing, erosion anduniformity. Drift in uniformity leads to longer polishtimes that, in turn, can degrade topography. The age of the polishing pad and inadequate pad conditioningcan result in underpolishing, leading to residual metal.Therefore, process qualifications, including topographyand defectivity verification, have to be made after everyconsumable change.

For these reasons, CMP is probably the fab’s mostmetrology-intensive process, with metrology timeaccounting for almost 50 percent of tool downtime.Sheet resistance measurements are currently used onblanket wafers to determine polish rates and selectivi-ties. However, in order to maintain tight control of theprocess, ideally both post-CMP topography and Cuthickness measurements on product wafers are essential.While profilometry can be used to measure topography,it cannot measure the thickness of Cu remaining in thetrenches. Topography measurements will have to becombined with oxide thickness measurements in arraysto derive the thickness of the neighboring Cu lines.Resistance measurements can be used to derive the thick-ness of Cu lines; however, they do not provide informationon dishing and erosion-related topography. Opto-acoustictechniques are being actively investigated for Cu CMPmeasurements. While they can be used for a wide rangeof film thicknesses (40Å to 3 µm), they may experienceinterference from the underlying films and, hence, havelimitations in measuring multiple metal levels.

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with the underlying or overlying interconnect. Cu linescan often fail due to line depletion EM mode and aweak interface between the Cu line and the dielectric atsome point along the long interface. With the additionof the CoWP cap layer, the failure mode shifts fromline depletion to via depletion mode, eliminating theCu/cap interface as the weakest point of interconnects.

Electroless cap layer process control challenges Thickness and composition of the cap layer impacts Cudiffusivity, interfacial adhesion and film stress of thelayer and, thereby, its effectiveness as a capping layer9.These parameters must be optimized during develop-ment and continue to be monitored during production.Pattern dependent loading effects during capping layergrowth using a selective electroless deposition processcan result in variations in thickness and compositionon lines with different feature sizes. The metrology toolused to monitor the film must be flexible enough tomeasure narrow and wide lines with equal precisionand accuracy.

Conventional techniques, such as opto-acoustic and X-ray reflectivity, have a difficult time measuring thin

Electroless capping layer depositionCopper interconnects at the 130-nm and 90-nm nodesare surrounded on three sides by a diffusion barrier andcapped on top by a silicon carbide (SiC) or SiN layerthat acts as a passivation and barrier layer to preventcopper oxidation, corrosion and diffusion, as well as anetch stop layer in Cu/low-k integration schemes. As thedimensions of the interconnect are scaled down, the ratioof Cu surface area to volume increases. This makes inter-connects more susceptible to surface diffusion-relatedEM phenomena that cause leakage and EM failures.

New capping materials (Figure 7) are being investigatedto reduce the interface diffusion of Cu, and the mostpromising candidate so far is cobalt tungsten phosphide(CoWP)7, 8. Improved EM behavior of up to a 10-foldincrease in lifetime has been demonstrated using a 10-nm electroless CoWP capping layer to achieve asignificant reduction in Cu interface diffusion.

EM failures in the form of line-opening voids can happen in two modes: line depletion, where the voidforms in the middle of an interconnect line, and viadepletion, where the void occurs at the via interface

Figure 7. Electroless capping layers enable significant reduction in Cu interface dif fusion.

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High-k materials and process controlchallengesFor high performance applications at the 65-nm nodeand below, new materials with higher dielectric con-stants (Graphic 4) will be needed to reducethe leakage currents to less than 10-7 A/cm2

for the same equivalent oxide thickness(EOT) of ~ 1.0 to 1.5 nm while maintain-ing the same gate capacitance and with no degradation of carrier mobility (ITRSRoadmap 2002, page 56). Cylindrical,stack and deep trench capacitors DRAMcapacitors are being extended to less than100 nm using new high-k dielectric mate-rials to reduce cost and yield issues (Graphic5). Advanced logic gates for low powertransistors are also being fabricated withmaterials that have several orders of magni-tude less leakage than SiON. Some of thehigh-k materials being considered for these applications are ALD Al2O3 and laminatesof Al2O3 and HfO2 to further increase thek-value for 65 nm and beyond11. Otherpromising materials under consideration are HfAlON and HfSiON. Al, Si, and Nelements help to stabilize the structure,control boron diffusion and improve carrier mobility.Hence the concentration of these elements and the filmthickness must be measured and controlled to provideconsistent gate performance.

Such hybrid and compound materials necessitate the useof ALD technology for controlled thin-film deposition.A benefit of ALD is that it provides the ability to engi-neer the composition throughout the thickness of thefilm to provide the right properties at each interface. In addition to thickness and composition control toachieve EOT scaling, composition control is also criticalto tune band-gap and mobility which remains a majorchallenge. Gate composition also affects thermal stability and boron penetration through the gate andother integration issues.

Along with the benefits come several processing andprocess control challenges, such as finding the rightprecursor and controlling the impurities in the film.Since ALD is a slow, low temperature process, it is easier to introduce impurities that can significantlychange the composition and properties of the film, considering that the films themselves are only a fewatomic layers thick. The only techniques currently usedto monitor thickness and composition of ALD films are

X-ray reflectivity and X-ray fluorescence, both of whichare not available for inline measurements with thespot-size, throughput and precision required for pro-duction monitoring.

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Graphic 4. Promising materials for consideration at the 65-nm node and below are

HfAlON and HfSiON. The concentration of Al, Si, and N and film thickness are important

parameters for ensuring consistent gate performance.

Graphic 5. New high-k dielectric materials extend DRAM stack

capacitors to beyond 100 nm.

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CoWP layers on Cu interconnects due to the low den-sity contrast between the Co alloy and the underlyingCu, which provides a weak return pulse to the surfaceor does not reflect enough X-rays at this interface,resulting in a poor detected signal. Furthermore, thesetechniques cannot measure the composition of theCoWP layer, which has an important effect on its EM-enhancing capability.

FEOL considerations — new gate materialsAs feature sizes shrink and gate oxides get thinner, gateleakage current increases exponentially. Currently,lightly-doped silicon oxynitride (SiON) is being usedin production at the 130-nm node. SiON with higheramounts of nitrogen (N) incorporated through plasma

nitridation is the choice of gate dielectric material forthe 90-nm node (Figure 8). The amount and distribu-tion of N that is incorporated into the gate oxide is akey factor in controlling electrical performance. Someof the process parameters that could cause a drift in theN concentration include RF power, gas pressure, andflow ratio of the plasma nitridation reactor.

Process control challenges of monitoring N distributionAlthough optical techniques offer a fast non-contactmethod of monitoring thickness and N dose on productwafers, they do not independently resolve changes inthickness and N concentration. Required is an inde-pendent method of monitoring N dose and thicknessfor process development and excursion recovery in pro-duction. X-ray photoelectron spectroscopy (XPS) canbe applied to measure N dose in ultrathin SiON gatedielectrics, but it has been mostly used as an off-lineanalytical reference technique due to its requirementsof very high levels of vacuum and a large spot size. Thesurface selectivity of XPS also makes it susceptible tounder-estimation of the N dose when the N is piled upat the interface (as in RTNO processes) or an over-esti-mation of the N dose when it is piled up at the surface,as in high-density plasma nitridation processes.

A new metrology solution for opaquefilms A new electron stimulated X-ray (ESX) metrologytechnique now available on KLA-Tencor’s Metrix 100platform addresses the needs of the 90-nm node andbeyond for measuring thickness and composition of awide variety of films on product wafers.

The tool’s incident electron beam causes characteristicX-rays of the elements present in the measured filmstack to be emitted from the material (Figure 9). Filmthickness is calculated by measuring the intensity ofthe elemental X-rays. For a compound film, the com-position can be calculated by the ratio of the X-rayintensities of the elements that make up the com-pound. The electron beam column of the MetriX 100delivers high beam current (up to 2 mA) with a broadrange of landing energies (0.5-30 kV) and a selectablespot size from 10-30 mm, suitable for product wafermetrology. The electron beam has a high beam currentto generate sufficient photons for enhanced precision athigh throughput, since the measurement precisionerror is inversely proportional to the square root of thephoton count (Poisson statistics). The landing energy isselected based on the materials and film thickness beingFigure 8. The amount and distribution of N that is incorporated into

the gate oxide is a key factor in controlling electrical performance.

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measured and can be tuned for a wide range of ele-ments and film thickness (Figure 10). Typically a land-ing energy of two-and-a-half to three times that of thehighest energy line being measured is selected to maximize the generation of X-rays for high precision.Thicker films may require higher energy, because theelectrons lose energy as they travel through the filmdue to collisions with the atoms of the film.

The X-rays from the different elements in the filmstack can be discriminated through an X-ray detectorby their characteristic wavelengths or energies. While asingle solid-state energy dispersive detector can be usedto quickly identify all the elements present in the film,this type of detector has relatively poor spectral resolu-tion and a low signal-to-noise ratio, resulting in spec-tral interference and poor sensitivity. The MetriX 100uses multiple wavelength dispersive X-ray detectors, orspectrometers, to measure the X-ray counts emitted byeach of the elements in the measured film stack (Figure11). Each spectrometer is designed to detect a specificwavelength of an elemental X-ray line and quantify it.The MetriX 100 incorporates up to six customizedspectrometers, thus allowing a range of elements to becovered by the system.

Wavelength dispersive X-ray detectors, or spectrometers,have a very good signal-to-noise ratio and spectral reso-lution of the X-ray peaks and are, therefore, excellentquantitative detectors. The superior signal-to-noiseratio provides higher sensitivity to lighter elementssuch as O and N. High measurement precision and

Figure 11. The MetriX 100 uses multiple wavelength dispersive X-ray

spectrometers to measure the X-ray counts emitted by each of the

elements in the measured film stack.

Figure 9. The MetriX 100 has an incident electron beam that causes

characteristic X-rays of the elements present in the measured film stack

to be emitted from the material.

Figure 10. The MetriX 100 has a broad range of landing energies,

which can be tuned for a wide range of elements and film thickness.

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throughput can be obtained due to the high count ratesof the detectors and low detector dead time. As a result,the MetriX 100 provides a thickness measurementrepeatability of <1% 1-sigma for ultrathin films down to20Å thickness and a composition repeatability of <1-2%1-sigma, even for a light element such as N. These features make the MetriX 100 highly suitable for fast,non-contact measurement for monitoring product wafers.

Case studies TaN Cu Barrier excursion: An excursion in the viaresistance of a TaN/Cu 130-nm Cu barrier seed metallayer was observed at end of line (EOL) electrical prob-ing. The thickness profile of the TaN was measuredusing a conventional opto-acoustic measurement system,and did not reveal any difference inthickness compared to a known goodbaseline wafer with normal via resis-tance distribution. The wafers were thenmeasured using the MetriX 100 systemfor thickness and composition andcompared to the baseline wafer. Figure12 clearly shows the difference in thecomposition of the barrier compared tothe baseline that is not detectable inthe comparison of the thickness profile.The percentage N composition mea-surement capability of the MetriX 100system thus proved essential in detectingthis excursion in-line. The excursion inpercentage N in the TaN barrier wasthen traced back to the PVD reactordue to an improperly installed processkit that was subsequently rectified.

Gate SiON dielectric plasmanitridation design of experimentA design of experiment (DOE) on aSiON plasma nitridation reactor wasperformed to characterize the percentageN incorporated in the gate dielectric.The percentage N in SiON controls theleakage of the film and, therefore, thestandby power consumption of thetransistor. An excess of N results in adegradation of channel mobility and,hence, transistor speed. The optimumconditions for a plasma nitridationprocess—RF power, pressure andtime—were characterized by the per-centage N dose that gives the optimum

transistor performance (Figure 13). The N dose wascorrelated to an existing lab baseline of XPS for a vari-ety of processes (Figure 14). The MetriX 100 systemalso measured the oxygen content of the gate SiON,which correlated well to the existing baseline of mea-sured optical thickness. This combination of N and Omeasurements allowed inline monitoring of thicknessand leakage of the gate dielectric. Optical measurementsare faster and sensitive to monitor excursions; however,they do not provide the capability to independentlymeasure N concentration—which allows the plasmanitridation process to be “re-centered” after an excursion.

Figure 13. The optimum conditions for a plasma nitridation process—RF power, pressure, and

time—were characterized by the percentage N dose that gives the optimum transistor performance.

Figure 12. Process excursion of Cu barrier layer due to improperly installed process kit resulted

in high via resistance.

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Cu CMP process control The MetriX 100 system can be used to measureremaining Cu thickness in interconnect structures aftera Cu CMP process. Residual Cu or barrier thickness inthe field due to under-polish can also be measured.Over-polish can result in a drastic reduction in inter-connect Cu thickness, resulting in a drop in line resis-tance. In addition to Cu thickness, thickness of thebarrier under the Cu can also be measured. Figure 15shows measurements of remainingCu using the MetriX 100 that cor-relate well to a profilometric mea-surement of dishing. Figure 16shows measurement of the Cuthickness in an array and the barri-er thickness under the Cu for M1.Figure 17 shows measurements atMetal 3, which pointed to exces-sive dishing and non-uniform bar-rier deposition for a new 90-nmprocess. The information was thenused to optimize the PVD barrierdeposition process and the CuCMP polish uniformity.

ALD TaN Cu barrier characterizationThe MetriX 100 system was used tostudy the growth rates and composi-tion of ALD TaN barriers on varioussubstrates. Figure 18 shows the changein composition with thickness. As theALD TaN film grows thicker, it incor-porates more nitrogen. Figure 19 showsthe variation in ALD TaN growth ratesand composition on different sub-strates. An ultrathin sub-20Å TaN filmon Si has significantly lower N contentthan the same film grown on a SiO2

underlayer. Using this information, theALD process with the right thicknessand composition was selected for fur-ther process integration studies.

Process control of CoWPelectroless passivation layersSince MetriX 100 was the only tool

that could provide independent thickness and composi-tion measurements on features with different patterndensities, an IC manufacturer used the tool to optimizea CoWP selective electroless deposition process forthickness and composition. Optical, photo-acoustic andother analytical techniques had achieved little success.A CoWP cap layer was deposited using a selective elec-troless deposition process on a blanket Cu wafer. Figure20 shows a simultaneous six-parameter measurement

S U B S T R A T E S

Figure 15. Cu thickness profile measured by MetriX 100 matches HRP profile results.

Figure 14. This combination of N and O measurements allowed inline monitoring of thickness

and leakage of the gate dielectric.

Established N% correla-tion to XPS.

Good N-dose agreementwith XPS.

N-dose precision is < 1%1σ.

0 counts show goodthickness agreementwith the KLA-TencorSpectraFx 100 spectro-scopic ellipsometry-based optical thin filmmetrology system.

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with the MetriX 100 system with thickness of CoWP,Cu and TaN barrier and CoWP composition reported.The measurements were used to optimize the process,

and then repeated on a patterned wafer with several testsites of varying pattern density. Because the selectiveelectroless process is affected by pattern loading, the

Figure 17. Remaining Cu thickness increases and TaN/Ta thickness decreases from wafer center to wafer edge.

S U B S T R A T E S

Figure 16. Post Cu CMP interconnect Cu and barrier thickness measurements in an array.

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thickness and composition ofthe CoWP layer couldpotentially change due topattern density effects. Threesites on each die were mea-sured for thickness and com-position of the CoWP film asshown in Figure 21. Furtheradjustments were made tothe process until an accept-able within-wafer variationin composition was achieved.By using the MetriX 100,the fab was able to quicklyoptimize their process toprovide uniform thicknessand composition on areas ofvarying pattern density.These measurements can bemade inline on productwafers to identify excursionsin composition within waferand from wafer to wafer fordifferent pattern densities.

ConclusionThe introduction of newmaterials and processing atthe 90-nm and 65-nm nodeshas given rise to severalunique problems. This hasresulted in new process control parameters. Of these,controlling the compositionof advanced thin films is recognized to be crucial forassuring high yield and

Figure 20. A simultaneous six-parameter measurement with the MetriX 100 system with thickness of CoWP,

Cu and TaN barrier, and CoWP composition reported.

S U B S T R A T E S

Figure 19. An ultrathin sub-20Å TaN film on Si has significantly lower N content than the same film grown

on a SiO2 underlayer. Using this information, the ALD process with the right thickness and composition was

selected for fur ther process integration studies.

Figure 18. Composition of ALD barriers depends on substrate type, film thickness and process conditions. MetriX 100 measures thickness and com-

position independently, enabling ALD process control.

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device reliability. Current metrology technologies lackthe full capability to monitor both film thickness andcomposition in production. A promising new technologyin the form of electron stimulated X-ray metrology is nowavailable on KLA-Tencor’s MetriX 100 system. Designedfor both process development and fast inline productionmonitoring, this system helps chipmakers achieve controlof advanced materials and associated processes.

References1. H. Chung et al., “An Ultra-thin ALD TaN Barrier for High-

Performance Cu Interconnects,” pp 454-456, ISSM 2003.2. L. Peters, “Making a Better Copper Barrier,” Semiconductor

International, March 2003.3. G. Beyer and M. Van Bavel, “Using Atomic Layer

Deposition to Prepare Future-Generation Copper DiffusionBarriers,” Micro, October 2002.

4. J. Gelatos et al., “ALD for sub-90-nm Device Node Barriers,Contacts and Capacitors,” Solid State Technology,February 2003.

5. J. A. Cunningham, “Copper Interconnects: Reaching for107A/cm2,” Solid State Technology, September 2003.

6. M. Colgan et al., “An Ultrasonic Laser Sonar Technique forCopper Damascene CMP Metrology,” Solid StateTechnology, February 2001.

7. T. Ko et al., “High Performance/Reliability Cu Interconnectwith Selective CoWP Cap,” Symposium on VLSI Technology,2003.

8. C. K. Hu et al., “Reduced Cu Interface Diffusion by CoWPSurface Coating,” Microelectronic Engineering, Vol. 70,Issue 2-4, November 2003.

9. A. Kohn et al., “Copper Grain Boundary Diffusion inElectroless Deposited Cobalt-based Films and Its Influenceon Diffusion Barrier Integrity for Copper Metallization,”Journal of Applied Physics, Vol. 94, No.5, September 1,2003.

10. D. Edelstein et al., “A High-Performance Liner for CopperDamascene Interconnects,” IEEE International InterconnectTechnology Conference, 2001, pp 9-11.

11. T. Seidel et al., “Progress and Opportunities in AtomicLayer Deposition,” Solid State Technology, May 2003.

S U B S T R A T E S

Figure 21. By using the MetriX 100, the fab was able to quickly optimize their process to provide uniform thickness and composition on areas of

varying pattern density.

Summer 2004 Yield Management Solutions