Summary of last lecture - University of California, Berkeleyee247/fa04/fa04/lectures/L10_f04.pdf ·...

EECS 247 Lecture 10: SC Filters © 2004 H. K.

EE247Lecture 10

Switched-Capacitor Filters• Summary of last lecture• Switched-capacitor filter design

considerations• Switched-capacitor filters utilizing

double sampling technique • Effect of non-idealities• Bilinear switched-capacitor filters• Filter design summary

EECS 247 Lecture 10: SC Filters © 2004 H. K. Page 2

Summary of last lectureSwitched-Capacitor Filters

• LDI integrators– Effect of parasitic capacitance– Bottom-plate integrator topology

• Resonators• Bandpass filters• Lowpass filters

– Termination implementation– Transmission zero implemention


LDI SC Integrator

( )

( )

1/ 2s1I

j T / 2s e s 1j T j T / 2 j T / 2I I

sI

sI

C j TC 1

in

C CC C1

CC

CC j T

Vo Z( Z ) , Z eZV

e e e

1j 2sin T / 2

T / 21sin T / 2

ωω ω ω

ω

ω

ωω ω

−−

−− − +

−

− −

= − × =

= − × = ×

= − ×

= − ×

CI

Ideal Integrator) Magnitude Error

No Phase Error! For signals at frequency <<sampling freq.

àMagnitude error negligible

-

+

Vin

Vo

φ1 φ2

CI

Cs

φ2

LDI

LDI (Lossless Discrete Integrator) àsame as DDI but output is sampled ½clock cycle earlier


Parasitic InsensitiveBottom-Plate SC Integrator

Sensitive parasitic cap. à Cp1à rearrange circuit so that Cp1 does not charge/discharge

φ1=1à capacitor grounded

φ2=1 à capacitor at virtual ground

Solution: Bottom plate capacitor integrator

Vi+

Cs-

+ Vo

CI

Cp1

Cp2

φ1 φ2

Vi-


Bottom Plate S.C. Integrator

12

12

1

1 1

1 1

z z1 z 1 z

z 11 z 1 z

−−

− −

−

− −

− −

−− −

Input/Output z-transformNote: Delay from Vi+ and Vi- to output is differentà Special attention needed to input/output connections

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Vi+on φ1

Vi-on φ2

Vo1on φ1

Vo2on φ2

φ1

φ2

Vo2

Vo1


Bottom Plate S.C. Integratorz-Transform Model

12

12

1

1 1

1 1

z z1 z 1 z

z 11 z 1 z

−−

− −

−

− −

− −

−− −

12

1z

1 z

−

−−

12z

−

Input/Output z-transform

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

φ1

φ2

Vo2

Vo1

Vi+

Vi- 12z

+ Vo2

Vo1

LDI

s IC C

s IC C−


LDI Switched Capacitor Ladder Filter

CsCI

12

1z

1 z

−

−−

-+

+ - + -3

1sτ 4

1sτ 5

1sτ

12z

−

12z

+

12z

+12z

+

12z

−

CsCI

−

CsCI

−CsCI

−CsCI

CsCI

Delay around integ. Loop is (Z-1/2 x Z+1/2 =1)è LDI function

12

1z

1 z

−

−−

12

1z

1 z

−

−−12z

−


Switched Capacitor LDI Resonator

2s

ω

1s

ω−

C1 1f1 sR C Ceq1 2 2C1 3f2 sR C Ceq3 4 4

ω

ω

= = ×

= = ×

Resonator Signal Flowgraph

φ1 φ2

φ1 φ2


Switched Capacitor LDI Bandpass FilterContinuous-Time Termination

0s

ω

0s

ω−

C C3 1f0 s sC C4 2C4Q CQ

ω = × = ×

=

Bandpass FilterSignal Flowgraph

CQ

Vi

Vo-1/QVoVi

Vo2


Fifth Order All-Pole LDI Low-Pass Ladder FilterComplex Conjugate Terminations

Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).

•Complex conjugate terminations (alternate phase switching)

Termination Resistor

Termination Resistor


Sixth Order Elliptic LDI Bandpass Filter


TransmissionZero


Use of T-Network

High Q filter à large cap. ratio for Q & transmission zero implementationTo reduce large ratios required à T-networks utilized



Sixth Order Elliptic Bandpass FilterUtilizing T-Network


•T-networks utilized for:• Q implemention• Transmission zero implementation

Q implemention

Zero


S.C. Resonator

Regular samplingEach opamp busy settling only during one of the clock phasesà Idle during the other clock phase


S.C. Resonator Using Double-Sampling

Double-sampling:

•2nd set of switches & sampling caps added to all integrators

•While one set of switches/caps sampling the other one transfers charge into the intg. cap

•Opamps busy during both clock phases

•Effective sampling freq. twice clock freq. while opamp bandwidth stays the same


Double-Sampling Issues

fclockfs

Issues to be aware of:- Jitter in the clock - Unequal clock phases -Mismatch in sampling caps.

à parasitic passbands Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical

Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).


Double-Sampled Fully Differential S.C. 6th Order All-Pole Bandpass Filter



Double-Sampled Fully Differential 6th Order S.C. All-Pole Bandpass Filter

Ref: B.S. Song, P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF Applications," IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 924-933, Dec. 1986.

-Cont. time termination (Q) implementation-Folded-Cascode opamp with ft = 100MHz used-Center freq. 3.1MHz, filter Q=55-Clock freq. 12.83MHz à effective oversampling ratio 8.27-Measured dynamic range 46dB (IM3=1%)


Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour

• Opamp finite gain• Opamp finite bandwidth• Finite slew rate of the opamp


Effect of Opamp Non-IdealitiesFinite DC Gain


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

DC Gain = asI s 1

I

1

Cs C C

s C a

o

o a

o

1H( s ) f

s f

H( s )s

aQ

Q a

ω

ω

ω

ω

≈ −+ ×

−≈

+ ×

×≈

⇒ ≈ àFinite DC gain same effect in SC filterscompared to CT filters


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft

Vo

φ2

T=1/fs

settlingerror

time

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Assumption-Opamp à does not slewOpamp has only one pole à exponential settling


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

actual idealIk k 1

I s

I t

I s s

t s

C1 e e ZH ( Z ) H ( Z )

C C

C fwhere k

C C ff Opamp unity gain frequency , f Clock frequency

π

− − − − + ×≈ +

= × ×+

→ − − →


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft

Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Vo

φ2

T=1/fs

settlingerror

time


Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Magnitude deviation due to finite opamp unity-gain-frequency

Example: 2nd

order bandpass with Q=25

fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Example:For 1dB magnitude response deviation:1- fc/fs=1/12

fc/ft~0.04à ft>25fc

2- fc/fs=1/32fc/ft~0.022à ft>45fc

3- Cont.-Timefc/ft~1/700à ft >700fc fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

Max. allowable biquad Q for peak gain change <10%

C.T. filters



Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft


C.T. filters

Example:For Q of 20 required Max. allowable biquad Q for peak gain change <10%

1- fc/fs=1/32fc/ft~0.022à ft>45fc

2- fc/fs=1/12fc/ft~0.04à ft>25fc

3- fc/fs=1/6fc/ft~0.062à ft >16fc


Effect of Opamp Finite Bandwidth on Filter Critical Frequency

Critical frequency deviation due to finite opamp unity-gain-frequency

Example: 2nd

order filterfc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Critical Frequency

fc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC

C.T. filters

Example:For maximum critical frequency shift of <1%

1- fc/fs=1/32fc/ft~0.028à ft>36fc

2- fc/fs=1/12fc/ft~0.046à ft>22fc

3- Active RCfc/ft~0.008à ft >125fc



Sources of Distortion in Switched-Capacitor Filters

• Opamp gain non-linearity• Capacitor non-linearity• Distortion incurred by finite setting time

of the opamp• Distortion induced by finite slew rate of

the opamp• Distortion due to switch clock feed-

through and charge injection


What is Slewing?

oV

Vi+Vi-

φ2

Cs

-

+

Vin

Vo

φ2

CI

CsCI

CL

Assume opamp is of a simple differential pairclass A transconductance type

Iss


Why Slew?

oV

Vi+Vi-

φ2

Cs

CI

CLIo

Vin

Vmax

Imax =Iss

slope~ gm

Vcs> Vmax à Output current constant Io=Issà SlewingAfter Vcs is discharged enough to have Vcs<Vmax à Linear settling

Iss

Io


Distortion Induced by Finite Slew Rate of the Opamp


Ideal S.C.Output Waveform

φ1

φ2

Vin

Vo

Vs

Clock-

+

Vin

Vo

φ1

CI

Cs

-

+

Vin

Vo

φ2

CI

Cs

φ2 High àCharge transferred from Cs to CI


Slew Limited Switched-CapacitorOutput Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing LinearSettling




Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).



• Error due to exponential settling changes linearly with signal amplitude

• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)

àFor high-linearity need to have either high slew rate or non-slewing opamp

( )( )

( )

o s

o s

2T2ok 2r s

2T2o3

r s

8 sinVHD S T k k 4

8 sinVHD S T 15

ω

ω

π

π

=−

→ =

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Finite Slew Rate of the OpampExample

-120

-100

-80

-60

-40

-20

1 10 100 1000

HD

3 (d

B)

[Slew-rate / fs ] (V)

f / fs =1/32

f / fs =1/12

Vo =1V V

o =2V

Vo =1V V

o =2V



• Note that for a high order switched capacitor filter à only the last stage slewing will affect the output linearity (as longas the previous stages settle to the required accuracy)à Can reduce slew limited linearity by using an amplifier with a

higher slew rate only for the last stageà Can reduce slew limited linearity by using class A/B amplifiers

• Even though the output/input characteristics is non-linear the significantly higher slew rate compared to class A amplifiers helps improved slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) à no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2

CI

Cs

At the instant Cs connects to input of opampàOpamp not yet active at t=0+ due to finite opamp delayàFeedforward path from input to output generates a voltage spike at the outputàEventually, opamp becomes active- slewing starts

CL

Vo

φ2

CI

CsCL


More Realistic SC Slew Scenario

Vo-realIncluding t=0+spike


Slewing

Spike generated at t=0+

Vo-real

Vo-ideal



Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. 1984 (ERL Memorandum No. UCB/ERL M84/67).


Sources of Noise in Switched-Capacitor Filters

• Opamp Noise– Thermal noise– 1/f noise

• Thermal noise associated with the switching process (kT/C)– Same as continuous-time filters

• Precaution regarding aliasing of noise required


S.C. Filters versus Continuous-Time FilterLimitations

Considering overall effects:-Opamp finite unity-

gain-bandwidth- Opamp settling issues-Opamp finite slew rate- Clock feedthru- Switch+ sampling

cap. Time-constant

Filter bandwidthAssuming constant opamp ft

MagnitudeError

5-10MHz

S.C. Filter

Cont. Time Filter

à Limited S.C. filter performance frequency range


Bilinear Transform

• Bilinear integrator

• Frequency translation

( ) ( ) ( ) ( )

( )

1 1

1

1

2

1 ( ) 1 ( )2

( ) 1( ) 2 1

o o i i

o i

o

i

Tv kT v kT T v kT v kT T

Tz V z z V z

V z T zH z

V z z

− −

−

−

= − + + −

− = +

+= =

−

( ) 2

2

1

tan

jf TSC

RC

SC z es jf

s SCRC

s

H zs

f ff

f

π

π

ππ

==

=

=

=

s

SCsRC f

fff π

πsin

Bilinear LDI


Bilinear Integrator

sI

j Tsj TI

sI s

1CC 1

CC 1

C sC Ts

2

1 ZH( Z )1 Z1 e

eT1

j T tan

ωω

ωω

ω

−+−

−−

−

+= − ×−

=− ×

=

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequency <<sampling freq.

àMagnitude error negligible

Ref: R. Gregorian, G. Temes, “Analog CMOS Integrated Circuits," Wiley, 1986, pp 277 .

-Not implemented by “standard” SC integrators-Synthesis:

Biquads: direct coefficient comparisonExample: SC integrator:


LDI & Bilinear TransformationFrequency Warping

LDI :

Bilinear

1/ 21 s

s

j Tj T s

s

sT

2T

2s

1 s1 T1

2T

2s

T 11 Z21 Z js in

2 js inT

T 11 e1 1 Z2e1 Z jtan

2 j tanT

s

s

s

s

ωω

ω

ω

ω

ω

−−

−+−

−

−− −

⇒ =

⇒

+⇒ = =−

⇒


Bilinear Transform

• Entire jω axis maps onto the unit circle

• Mapping is nonlinear (tan distortion)à prewarp specifications of RC prototype Matlab filter design automates this (see, e.g. bilinear)

=

s

SCsRC f

fff π

πtan

0 0.5 1 1.5 2 2.5 3

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f sc /f

s

fRC /fs


Bilinear & LDI Transformation Frequency Warping

As long as f<<fs error negligible


“Bilinear” Bandpass

fs = 100kHzfc = fs/8Q = 10

Matlab:

0.0378 z^2 - 0.0378H(z) = ----------------------

z^2 - 1.362 z + 0.9244

zero at fs/2

Pole-Zero Map

Real Axis

Imag

Axi

s

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1


( )( )

( ) ( )( ) ( )656554

252352513

23

122

KKzKKKKzKKKzKKKKKzK

zVzV

i

o

−+++−+−+++−+

=

phi1phi1 phi1

phi2 phi2

K1 CA = 0F

-1M-1M

CA = 1pFCA = 1pFCA = 1pFCA = 1pF

phi1phi1 phi2

phi2 phi1

K5 CB = 500fF

-1M-1M-1M-1M

CB = 1pF

phi1phi1 phi1

phi2 phi2

K4 CA = 1.125pF

K3 CB = 37.8fF

K2 CA = 151.2fF

K6 CA = 151.2fF

VoVi

Martin-Sedra Biquad

Periodic AC Analysis PAC1log sweep from 1k to 50k (300 steps)

fs = 100kHzCLK1

V1ac = 1V

Ref: K. Martin and A. S. Sedra, “Strays-insensitive switched-capacitor filters based on the bilinear z transform,” Electron. Lett., vol. 19, pp. 365-6, June 1979.


Magnitude Response

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 105

-70

-60

-50

-40

-30

-20

-10

0

Frequency [Hz]

Mag

nitu

de [

dB]


LD vs Bilinear Transform• LDI transform:

– Realized by “standard” SC integrators– Some high frequency zeros are lost– Simple filter synthesis:

• Replace RC integrators with SC integrators• Ensure that inverting and non-inverting integrators alternate in loops

• Bilinear transform– Maps entire jω axis onto unit circle (nonlinear mapping)– Not implemented by “standard” SC integrators– Synthesis:

• Biquads: direct coefficient comparison• Ladders: see

R. B. Datar and A. S. Sedra, “Exact design of strays-insensitive switched capacitor high-pass ladder filters”, Electron. Lett., vol. 19, no 29, pp. 1010-12, Nov. 1983.


SC Filter Summary

ü Pole and zero frequencies proportional to – Sampling frequency fs– Capacitor ratiosØ High accuracy and stability in responseØ Long time constants realizable without large R, C

ü Compatible with transconductance amplifiers– Reduced circuit complexity, power

ü Amplifier bandwidth requirements less stringent comparable to CT filters (low freqs only)

L Issue: Sampled data filter à require anti-aliasing prefiltering


SummaryFilter Performance verus Topology

_

1-5%

1-5%

1-5%

1-5%

Freq. tolerance+ tuning

<<1%40-90dB~ 10MHzSwitched Capacitor

+-30-50%40-70dB~ 100MHzGm-C

+-30-50%50-90dB~ 5MHzOpamp-MOSFET-RC

+-30-50%40-60dB~ 5MHzOpamp-MOSFET-C

+-30-50%60-90dB~10MHzOpamp-RC

Freq. tolerance w/o tuning

SNDRMax. Usable Bandwidth

Summary of last lecture - University of California, Berkeleyee247/fa04/fa04/lectures/L10_f04.pdf ·...

Documents

Transcript of Summary of last lecture - University of California, Berkeleyee247/fa04/fa04/lectures/L10_f04.pdf ·...