Performed byGreenberg Oleg

Kichin Dima

Winter 2010

Supervised by Moshe Mishali

Inna Rivkin

General Algorithm Scheme

1. Expand block: Recieves 4 channels from A/D and expands

them to 12 channels 2. CTF block: Discovers supports out of 12 channels

3. DSP & Detector block**: Reconstructs the Initial Signal

** Implemented in the same FPGA

Objective

Designing system architecture

Creating debug environment

Architecture implementation on FPGA

FPGA Environment1x BOARD: ProcStar||| GiDEL

4x FPGA: Stratix||| EP3SE110 Altera

Overview

Single FPGA Overview

Buses on Board

•FPGA to FPGA Bits Max.Freq.(MHz)

L/R (I/O) : 100 250 // exp. IC4 V18_L/R : 10 300 Main : 40 300 // global

•FPGA to PSDB Bits Max.Freq.(MHz)

L/R_IO : 20 300 // 7 to IC1 L_IN : 8 300 // PSDB to IC L2_IO : 85 300 // only to IC1

Memories

• External from FPGA Bank A:256 MB DDR2 DRAM

Bank B,C: 2 x 1 GB SODIMM

• Internal inside FPGA

MLAB 640-bit (639 blocks)

Filter delay lines, small FIFO buffers and shift registers M9K Blocks 9,216-bit (16 blocks)

General purpose memory applications M114K Blocks 147,456-bit (2150 blocks)

Processor code storage, packet and video frame buffering.

Total Internal Memory:

Max.Freq.=333MHz

Max.Freq.=166MHz

Max.Freq.=500MHz

1MByte

Proposal Architecture

Data Flow

CTFExpander DSP

Main Controller

DDR CTF&DSP(Debug)

24bit (160MHz) + 1bit Valid

84bit (160MHz)+1bit Valid

1bit (160MHz) Initiate

DDR DSP(Debug)

Memory(A/D)

Memory(Out)

60MHz48 bit+valid

Reset

24bit (160MHz) + 1bit Valid

4bit #Iteration

PciExp.

PciExp.

FIFO DDR DSP

Reset Reset

Main Controller 1bit (160MHz)

Req_Pulse

4bit #Iteration

Detector

Memory_1(Debug)

Memory_2(Debug)

A/D

Expander

Main Controller

1Interface

4Interface

CTF

Interface5

2Interface

6Interface

DSP

Detector

3Interface

Interface7

Filter Coefficients

Matrix Coefficients

Matrix Coefficients

Proposal Architecture

Multiple CTF iterations Data Flow

CTF DSP

Main Controller

DDR CTF&DSP(Debug)

24bit (160MHz) + 1bit Valid+

88bit (160MHz)+1bit Valid

1bit (160MHz) Initiate

DDR DSP(Debug)

Memory(A/D)

Memory(Out)

60MHz48 bit

Reset

24bit (160MHz) + 1bit Valid

4bit #Iteration

PciExp.

PciExp.

FIFO DDR DSP

Reset Reset

1bit (160MHz) Req_Pulse

4bit #Iteration

Detector

Memory_1(Debug)

Memory_2(Debug)

A/D

Expander

Main Controller

Interface

Interface

Interface

Interface Interface

Interface

Interface

CTF

Expander

DSP

_12 7 841 , 250MHz

90

Col Number bit bitCycle

BandWidth bit

12 12 144

. 20Chanels bit bit

Freq MHz

246

. 120

BandWidth bitCycles

Freq MHz

12 16 192

. 20Chanels bit bit

Freq MHz

248

. 160

BandWidth bitCycles

Freq MHz

OR

2563 , 250MHz (2Cycle in DDRmode)

90

bitCycle

BandWidth bit

Data Flow Options

OR

Interface Interface

EntitiesAccording the design

EntitiesAccording the design

EntitiesAccording the design

EntitiesAccording the design

Proposal Architecture

Debug Data Flow

Expander DSP

DDR(Debug)

Memory(A/D)

Memory(Out)

60MHz48 bit 24bit (160MHz)

FIFO DDR DSP

Main Controller 1bit (160MHz)

Req_Pulse

Detector

Memory_1(Debug)

A/D

CTF modelValid

DDR DSP(Debug)

Support

24bit (160MHz) + 1bit Valid

Exp&CTF model

Initiate

Proposal Architecture

Debug Data Flow

CTF

DDR CTF&DSP(Debug)

24bit (160MHz) + 1bit Valid+

88bit (160MHz)+1bit Valid

1bit (160MHz) Initiate

24bit (160MHz) + 1bit Valid

4bit #Iteration

1bit (160MHz) Req_Pulse

Expander Model

Memory_2(Debug)

Reserved Signals

CTFExpander DSP

10bit (300MHz)

74bit (250MHz)

10bit (300MHz) 14bit (250MHz)

Memory_3DDR(FiFo)

Main Controller

Detector10 bit(300MHz)

Protocols•EXPANDER

While(Data) Valid=1

Write Data Every Clock

Valid=0

•EXPANDER (Multiple CTF Cycles)

While(#Iterations!=0) Wait Until (Req_Pulse=1) While(Data)

Valid=1

Write Data Every ClockValid=0#Iterations--

•CTF & DSP & Detector

While(Valid==1) Read Data Every Clock

•CTF (Multiple CTF Cycles)

While(#Iterations!=0) Req_Pulse=1 While(Valid)

Read Data Every Clock

Calculate Support #Iterations--

Protocols•CTF

If (Supports) Valid=1

Write #Supports Write Data

Valid=0

•Detector

If(Support Changes) Initiate_Pulse=1

• DSP

If (Valid==1) Read Data

Read #Support

•CTF

If (Initiate_Pulse==1)Calculate Support

FIFO & DSP

DSP

FIFO

FiFo Small

Detector

CTFSupport

Initiate

Look_Ahead Data

ExpanderData

X Cycles Depth

X Cycles Depth

Support ID

New Support buffer

ID

Support buffer

IDData Out

• The small fifo will be implemented in internal FPGA memory• The FIFO will be implemented in external memory

Milestones

Algorithm understanding Environment learning Defining System Data Flow Defining Blocks Interfaces Defining Blocks Protocols Architecture Implementation

In progress

Yes

In progress

In progress

No

In progress

What’s Next?

1. Architecture: Receiving final requirements from all groups - 16/12/09 Creating generic debug environment – 20/12/09 Ending Interfaces between the components/memories – 27/12/09 Final recheck of the design/week off – 8/01/10

2. Implementation: Control Units Interfaces Memories Architecture

Starting 8/01/10

Questions

Thank You For Listening.