Sub 10 nm CNT transistor
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Transcript of Sub 10 nm CNT transistor
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7/27/2019 Sub 10 nm CNT transistor
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Paper reading report
Sub-10 nm Carbon NanotubeTransistor
Qing Shi
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistorFinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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7/27/2019 Sub 10 nm CNT transistor
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistorFinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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7/27/2019 Sub 10 nm CNT transistor
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Background information
key problems in small transistors
Good transistor:
1. High Ion/Ioff ratio
high on state current and small off state current
2. Low inverse threshold slope(SS factor)
=
()
voltage change when drain current decreases to 1/10
arising problems:Size of transistor
leakage current high Ioff and low ratio
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Background information
key problems in small transistors
Paths far from the gate cannot be neglected (short channel)
This means: the drain current can no longer be controlled bygate voltage!
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistor
FinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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7/27/2019 Sub 10 nm CNT transistor
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Background information
key problems in small transistors
Goal:
kill the leakage current
Besides:
satisfy other conditions to be a good transistor
(high Ion and low threshold slope)
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistor
FinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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How to solve them
silicon nanowire transistor
purple: metal gate (M)
blue: dieletric layer (O)
orange: si nanowire (S)
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How to solve them
FinFET
tri-gate and double gate:
dieletric layer between channel and gate.
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How to solve them
ETSOI/UTBSOI
Keypoint: thin layer as channel
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How to solve them
CNT transistor
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistor
FinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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Numerical calculation and results
What the auther do in this paper:1. fabricate the 9nm carbon nanotube transistor
2. measure curve of Id-Vgs
3. SS is much smaller thantheoretical projection got before
SS=94mV/dec SS(proj)=170mV/dec
4. why past projection is wrong?
5. using a new method to do the simulation work
6. also compare result with other new transistors
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistor
FinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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Numerical calculation and results
old method
Ref: Nanotechnology 2006, 17, 4699-4750semiclassical self-consistent method
use it to calculate sub-10 nm CNT
answer: 170mV/dec as mentioned before
not identical with experimental data.(94mV/dec)
Key: channel becomes less significant than the contacts sincethe channel is extremely short.
in old method, we treat the contact part as very small.
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Outline
Background informationa) key problems in small transistors
b) how to solve them?
some new schemes:
Si nanowire transistor
FinFET
ETSOI/UTBSOI
CNT tansistor
Numerical calculation and results
a) old method
b) new method
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Numerical calculation and results
new method
use the Greens function methodso called bottom-gate structure
My question:
how he deal with the contact
![Chap. 7 Nanoelectronics Nanoengineering (8).pdf- Using the “top-down” photolithographic technology, the transistor size will reach a limit of ~ 16 nm [currently, ~8 nm]. 7.3.2](https://static.fdocuments.in/doc/165x107/6135909e0ad5d20676477524/chap-7-nanoelectronics-nanoengineering-8pdf-using-the-aoetop-downa-photolithographic.jpg)
