STT-RAM Test Chip #1

Amr Amin Preeti Mulage

UCLA

CKY Group

Weekly Status Report

Date: Wed Oct-21-2009

Previous Action Items

• Cell Design:– Investigating LVT devices, 1.2V supply, boosted WL

voltage Done– Sensitivity analysis In progress (need data about

MTJ variations)

• Memory Array– Reference cells for current sensing Done– Array schematic and layout Done– Column MUX schematic Done– Sense amp and “write” driver schematic Done– Connecting Top Cell In progress

MTJ Design Space

Available Sensing Signal

• I-Sense: ΔISIG vs. TMR for different values of RON

0 20 40 60 80 100 120 140 160 180 2000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

TMR (%)

I S

IG /

I REA

D

RON

/RP = 2

RON

/RP = 1

RON

/RP = 0.5

RON

/RP = 0.25

RON

/RP = 0

P

ONREAD

SIG

ONAP

PAPREADSIG

R

RTMR

TMR

I

I

RR

RRII

1

Available Sensing Signal• I-Sense: Contours of constant ΔISIG in the

MTJ Space

0

0

0

0

0.1

0.1

0.1

0.1

0.2

0.2

0.2

0.2

0.3

0.3

0.3

0.4

0.4

0.4

0.5

0.5

0.5

0.6

0.6

0.6

0.7

0.7

0.8

0.8

RP / R

ON

RA

P / R

ON

(ISIG

/ IREAD

) in the MTJ Space

0 1 2 3 4 5 6 7 8 9 100

1

2

3

4

5

6

7

8

9

10

Available Sensing Signal

• V-Sense: ΔVSIG vs. TMR for different values of RP

0 20 40 60 80 100 120 140 160 180 2000

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

TMR (%)

V

SIG

/ I R

EAD (

mV

/A

)

RP = 200

RP = 400

RP = 600

RP = 800

RP = 1000

TMRRI

V

RRIV

PREAD

SIG

PAPREADSIG

Available Sensing Signal• V-Sense: Contours of constant ΔVSIG in the

MTJ Space

0

0

0

00.2

0.2

0.2

0.2

0.4

0.4

0.4

0.6

0.6

0.6

0.8

0.8

0.8

1

1

1.2

1.2

1.4

1.6

RP()

RA

P()

(VSIG

/ IREAD

) (mV/A) in the MTJ Space

0 200 400 600 800 1000 1200 1400 1600 1800 20000

200

400

600

800

1000

1200

1400

1600

1800

2000

Sense Amp Schematic