STEVAL-IME011V1 evaluation board based on the STHV748 ......The STEVAL-IME011V1 is an evaluation...
Transcript of STEVAL-IME011V1 evaluation board based on the STHV748 ......The STEVAL-IME011V1 is an evaluation...
November 2015 DocID028424 Rev 1 1/28
www.st.com
UM1957 User manual
STEVAL-IME011V1 evaluation board based on the STHV748 ultrasound pulser
Introduction The STEVAL-IME011V1 is an evaluation board designed around the STHV748 ultrasound pulser IC, a state of the art product in ultrasound imaging applications. The system drives four transducers as 4-channel transmitters, and can output waveforms directly to an oscilloscope by connecting the scope probe on the relative BNCs. Four preset waveforms are available to test the HV pulser under different conditions.
Figure 1: STEVAL-IME011V1 evaluation board
Contents UM1957
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Contents
1 Board features ................................................................................. 3
2 Getting starting ................................................................................ 4
3 Hardware layout and configuration ................................................ 5
3.1 Power supply ..................................................................................... 5
3.2 MCU .................................................................................................. 6
3.3 Stored patterns .................................................................................. 8
3.4 STHV748 stage ............................................................................... 16
3.5 Operating supply conditions ............................................................ 17
4 Connectors .................................................................................... 19
4.1 Power supply ................................................................................... 19
4.2 MCU ................................................................................................ 20
5 Schematic ...................................................................................... 23
6 PCB layout ..................................................................................... 24
7 Revision history ............................................................................ 27
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1 Board features
Suitable for ultrasound imaging applications
4 monolithic channels, 5 level high voltage pulser
Integrated T/R switch
On-board equivalent piezoelectric load implemented through an R/C equivalent network
USB interface available for uploading customized output waveforms
Embedded Microcontroller Flash memory available for storing customized waveforms
High voltage screw connectors to power the STHV748
Automatic lockout overvoltage protection
7 LEDs to signal EVAL BOARD status and proper operation
Human Machine Interface to select, start and stop the stored output waveforms
Getting starting UM1957
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2 Getting starting
The STEVAL-IME011V1 is shipped by STMicroelectronics ready to use. The user only needs to:
1. Plug the right power supply to the board (see Section 1: "Board features" for further details)
2. Connect the BNC to the oscilloscope 3. Check that LED PROGRAM 1 (LD1) turns on 4. Select the waveform with the PROGRAM button. The corresponding PROGRAM LED
(LD1-LD4) turns on 5. Press the START button to run the selected program; the START LED L5 turns on.
When the program ends, the microcontroller returns to the IDLE state (LED L5 off) 6. If a continuous wave program is selected, the STOP button must be pressed to stop
program execution. The microcontroller returns to the IDLE state and the STOP led (L5) turns off
7. To run the same program again, restart from step 5. To run another program, restart from step 4
8. An overvoltage protection mechanism suspends pattern generation if the HV supply exceeds 90 V and the red L6 LED switches on. Pattern generation will restart once the HV supply voltage falls back into the allowed range.
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3 Hardware layout and configuration
The STEVAL-IME011V1 evaluation board is designed around the STHV748. The hardware block diagram below illustrates the main connection between STHV748 and the STM32F4. Figure 3: "STEVAL-IME003V1 board layout" will help you to locate connectors, LEDs and features on the board.
Figure 2: Hardware block diagram
Figure 3: STEVAL-IME003V1 board layout
3.1 Power supply
The low voltage block of the STEVAL-IME011V1 board is designed to be powered:
during programming and when the board is connected to the PC:
5V DC through USB Mini B connector to supply the STM32F4
During pattern generation and when high voltage is powered on:
5V DC connected to VDD to supply STM32F4 and STHV748 through an LDO
-5V DC connected to VSS to supply STHV748 through an LDO
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the USB link must be removed when high voltage is connected to the board
The high voltage block of the STEVAL-IME011V1 is designed to be powered:
VDD: Positive supply voltage, 5 V (2 - VDD conn.)
GND: Ground (1 – VDD conn. And 2 – VSS conn)
VSS: Negative supply voltage 5 V (1 - VSS conn.)
GND: Ground (1 – HVP0 conn.)
HVP0: TX0 High voltage positive supply (2 - HVP0 conn.)
GND: Ground (1 – HVP1 conn.)
HVP1: TX1 High voltage positive supply (2 - HVP1 conn.)
HVM1: TX1 high voltage negative supply (1 - HVM1 conn.)
GND: Ground (2 - HVM1 conn.)
HVM0: TX0 high voltage negative supply (1 - HVM0 conn.)
GND: Ground (2 – HVM0 conn.)
Figure 4: STEVAL-IME011V1 board connections
3.2 MCU
The STM32F427 is fully dedicated to generating the bitstream on its GPIO pins to drive the pulser’s output channels. It is already pre-programmed as a DFU (device firmware upgrade) device with the ability to upgrade internal FLASH memory. The STM32F427 manages all the DFU operations, such as the authentication of product identifier, vendor identifier and Firmware version. The MCU drives the pulser channels through the use of different General Purpose IO (GPIO) pins. You can simulataneously drive from 1 to 16 different pins by simply writing a 16-bit word into the GPIO Output Data Register (ODR). The board can be connected to a PC via USB. The required pattern is sent as a sequence of states for each pulser channel and of durations for each state. Here, all durations are expressed in units of MCU system clock cycles. Once the information is received, the channel states are converted into 16-bit words for the GPIO peripheral and they are stored in the embedded Flash, together with the timing information. After programming, the PC is
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no longer required, so the board can act as a stand-alone device. Different patterns can be stored and the user can select which one to use at run-time. The same MCU can implement two different solutions for real-time execution.
The first solution involves the use of the STM32 Direct Memory Access (DMA) peripheral. The DMA is able to transfer data from memory to any peripheral register, GPIO included, without the intervention of the MCU core.
To trigger DMA transfer, a general purpose TIMER is used. The timer works at the system clock frequency and basically acts as a counter and the reload value (the value at which the counter returns to zero) is stored in the Auto Reload Register (ARR). The timer triggers two different DMA channels in two different moments:
the first channel is triggered at each reload event and transfers the new GPIO word into the ODR;
the second is triggered at a constant time after reload and transfers the new duration information into the ARR
The timer preload feature is enabled, so that the new ARR value is effective only at the next reload. Since the time needed by the first DMA channel to update the ODR is a constant, considering the reload trigger as the starting point, the time between two different GPIO updates is simply given by the ARR value. The Circular buffer feature of the DMA can be enabled to allow the automatic regeneration of the same pattern at each end. This solution has the advantage of being fully managed by hardware. The MCU core is completely free for any user requirement.
The main drawback is that each timing value between two subsequent states cannot be lower than a minimum value in order to guarantee enough time for both DMA channels to perform their transfers.
Figure 5: Solution 1
The second solution is designed to overcome the minimum duration requirement of the DMA solution and involves the MCU core directly.
During run-time, the core generates the binary assembly code it needs to load and store each word in the ODR. Any unnecessary instructions like control loops are avoided; the code is only a succession of simple load/store instructions.
To adapt the timing to the pattern needs, dummy instructions are inserted in the assembly code. To avoid wasting time to load each word from memory, the word is inserted as a literal in the assembly instruction itself, which means that a 32-bit instruction is needed instead of a 16-bit equivalent.
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In order to avoid any latency due to the instruction fetch from Flash, the code is executed from the embedded RAM. Moreover, the RAM is configured to be accessed by the core through a different bus to the one used to access the ODR.
Thanks to all these solutions, it is possible to achieve a minimum time of two system clock cycles before two updates and maintain a one system clock cycle resolution. For instance, if you consider a STM32F4 clocked at 168 MHz, the minimum timing you can achieve is 12 ns and you can set the duration of each state with a resolution of 6 ns. For a repetitive pattern, a branch instruction is added at the end of the routine to restart the pattern generation. In this case, the clock cycles needed for the branch instruction has to be considered for the last state.
The main drawback of this solution is that the MCU core is 100% involved in the pattern generation even though it can still be called by peripheral interrupts and stop pattern generation to perform other tasks.
Figure 6: Solution 2
3.3 Stored patterns
The STEVAL-IME011V1 can memorize four patterns in the MCU FLASH memory in order to demonstrate the achievable performance at the pulser outputs. Four selectable patterns already stored into STM32 flash memory form the default set which is available and ready to use. A detailed description of the programs is listed below.
Programmed waveform description, flagged by LED L1 to L4.
Program “1” (see Figure 7: "Scheme of program “1”")
XDCR_A: Pulse Wave mode, TX0 switching, 5 pulses, time-period TP=400ns and PRF=150µs
XDCR_B: Pulse Wave mode, TX0 switching, 5 pulses in counter phase respect to XDCR_A, time-period TP=400ns and PRF=150µs
XDCR_C: Pulse Wave mode, TX1 switching, 5 pulses, time-period TP=200ns and PRF=150µs
XDCR_D: Pulse Wave mode, TX1 switching, 5 pulses in counter phase respect to XDCR_C, time-period TP=200ns and PRF=150µs
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TX0 means H-Bridge supplied by HVP/M0, while TX1 means H-Bridge supplied by HVP/M1.
Figure 7: Scheme of program “1”
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Table 1: Program "1"
PW 5pulses - HV0/1=±60 V; LOAD: 270 pF//100 Ω
Mode
Frequency (MHz)
Number of pulses
Initial pulse H-bridge PRF
Ch A PW 2.5 5 positive TX0 150 µs
Ch B PW 2.5 5 negative TX0 150 µs
Ch C PW 5 5 positive TX1 150 µs
Ch D PW 5 5 negative TX1 150 µs
Figure 8: Acquisition by Program “1”
Program "2" (see Figure 9: "Scheme of program “2”")
XDCR_A: Pulse Wave mode, TX0 switching, 5 pulses, time-period TP=200ns and PRF=150 µs
XDCR_B: Pulse Wave mode, TX0 switching, 5 pulses in counter phase respect to XDCR_A, time-period TP=200ns and PRF=150 µs
XDCR_C: Pulse Wave mode, TX1 switching, 5 pulses, time-period TP=100ns and PRF=150 µs
XDCR_D: Pulse Wave mode, TX1 switching, 5 pulses in counter phase respect to XDCR_C, time-period TP=100ns and PRF=150 µs
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Figure 9: Scheme of program “2”
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Table 2: Program "2"
PW TX0&TX1 5pulses - HV0/1=±60 V; LOAD: 270 pF//100 Ω
Mode
Frequency (MHz)
Number of pulses
Initial pulse H-bridge PRF
Ch A PW 5 5 positive TX0 & TX1 150 µs
Ch B PW 5 5 negative TX0 & TX1 150 µs
Ch C PW 10 5 positive TX0 & TX1 150 µs
Ch D PW 10 5 negative TX0 & TX1 150 µs
Figure 10: Acquisition by Program “2”
Program "3" (see Figure 11: "Scheme of program “3”")
XDCR_A: Continuous Wave mode, TX-CW switching, time-period TP=400 ns
XDCR_B: Continuous Wave mode, TX-CW switching in counter-phase respect to XDCR_A, time-period TP=400 ns
XDCR_C: Continuous Wave mode, TX-CW switching, time-period TP=200 ns
XDCR_D: Continuous Wave mode, TX-CW switching in counter-phase respect to XDCR_C, time-period TP=200 ns
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Figure 11: Scheme of program “3”
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Table 3: Program "3"
Continuous Wave - HV1=±10V; LOAD: 270 pF//100 Ω
mode
Frequency (MHz)
Number of pulses
Initial pulse H-Bridge
Ch A CW 2.5 continuous wave
positive TX-CW
Ch B CW 2.5 continuous wave
negative TX-CW
Ch C CW 5 continuous wave
positive TX-CW
Ch D CW 5 continuous wave
negative TX-CW
Figure 12: Acquisition by Program “3”
Program “4” (see Figure 13: "Scheme of program "4"")
XDCR_A: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs
XDCR_B: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs
XDCR_C: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs
XDCR_D: Pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns and consequently TX1 switching, 5 pulses, time-period=200 ns and PRF=150 µs
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Figure 13: Scheme of program "4"
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Table 4: Program "4"
Pulse Cancellation - HV0/1=±60 V; LOAD: 270 pF//100 Ω
Mode
Frequency (MHz)
Number of pulses
Initial pulse H-bridge PRF
Ch A PW 2.5 - 5 3 half pulse then 4 pulse
positive TX0 then TX1
150 µs
Ch B PW 2.5 - 5 3 half pulse then 4 pulse
negative TX0 then TX1
150 µs
Ch C PW 5 3 half pulse then 4 pulse
positive TX0 then TX1
150 µs
Ch D PW 5 3 half pulse then 4 pulse
negative TX0 then TX1
150 µs
Figure 14: Acquisition by Program “4”
The board can be connected to a PC via USB cable and patterns can be edited by means of a user interface.
the USB link must be removed when a high voltage is connected to the board
3.4 STHV748 stage
The STHV748 high-voltage, high-speed ultrasound pulser IC features four independent channels. It is designed for medical ultrasound applications, but can also be used for other piezoelectric, capacitive, or MEMS transducers. The device contains a controller logic interface circuit, level translators, MOSFET gate drivers, noise blocking diodes, and high-power P-channel and N-channel MOSFETs as output stages for each channel. There is also clamping-to-ground circuitry, anti-leakage, an anti-memory effect block, a thermal sensor, and a HV receiver switch (HVR_SW), which guarantees strong decoupling during the transmission phase. Moreover, the STHV748 includes self-biasing and thermal
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shutdown blocks (see Figure 15: "STHV748 single channel block diagram"). Each channel can support up to five active output levels with two half bridges. The output stage of each channel is able to provide a ±2 A peak output current. In order to reduce power dissipation during continuous wave mode, the peak current is limited to 0.6 A (a dedicated half bridge is used).
For further information, please refer to the STHV748 datasheet.
Figure 15: STHV748 single channel block diagram
The STHV748 output waveforms can be displayed directly for each channel Ch A/B/C/D using an oscilloscope by connecting the scope probe to the XDCRA, XDCRB, XDCRC, and XDCRD SMB connectors. Moreover, the pulser outputs are connected to the onboard equivalent load, a 270 pF 200 V capacitor paralleled with a 100 Ω, 2 W resistor. A coaxial cable can also be used to easily connect the user transducer; in this case, the equivalent load should be removed from the board. Furthermore, four low voltage outputs are available to receive the echo traduced signal coming from the piezo-element through HVR_SW (LVOUTA, LVOUTB, LVOUTC, LVOUTD).
The main issues in this PCB design are the capacitance values necessary to ensure good filtering and the effective decoupling between the low voltage inputs (IN1, IN2, IN3, IN4, and EN for each channel) and the HV switching signals (XDCR, HVOUT, etc.,), which is ensured by the implemented layer separation.
3.5 Operating supply conditions
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Table 5: DC working supply conditions
Operating supply voltages
Symbol Parameter Min. Typ. Max. Value
VDD Positive supply voltage 5 6 10 V
VSS Negative supply voltage -5 6 -10 V
HVP0 TX0 high voltage positive supply
95 V
HVP1 TX1 high voltage positive supply
95 V
HVM0 TX0 high voltage negative supply
-95
V
HVM1 TX1 high voltage negative supply
-95
V
The high voltage pins must be HVP0 ≥ HVP1 and HVM1 ≥ HVM0
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4 Connectors
4.1 Power supply
The STEVAL-IME011V1 board is powered through the screw connectors as shown in the following figures.
Figure 16: Power supply connector VDD (+5V - GND)
Figure 17: Power supply connector VSS (GND - -5V)
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Figure 18: Power supply connector HVP0 – HVP1 and HVM0 – HVM1
4.2 MCU
Figure 19: USB mini-B connector (CN1)
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Table 6: USB mini B connector pin out
Pin number Description
1 Vbus (power)
2 DM (STM32 PA11)
3 DP (STM32 PA12)
4 N.C.
5 Ground
Figure 20: JTAG connector
Table 7: JTAG connector
1 DVDD
2 JTDI
3 JTMS
4 JTCK
5 JTDO
6 JRST
7 GND
8 NRST
Connectors UM1957
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Figure 21: Boot connector
Table 8: Boot connector
1 GND
2 BOOT0 (boot from flash memory)
3 DVDD (DFU mode)
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5 Schematic
Figure 22: STEVAL-IME011V1 circuit schematic
U1
PE
21
PE
32
PE
43
PE
54
PE
65
VBAT 6
PC13 7
PC14 8
PC15 9
VSS510
VDD511
OSC_IN12
OSC_OUT13
NRST14
PC0 15
PC1 16
PC2 17
PC3 18
VSSA19
VREF-20
VREF+21 VDDA22
PA
023
PA
124
PA
225
PA
326
VSS427
VDD428
PA
429
PA
530
PA
631
PA
732
PC4 33
PC5 34
PB
035
PB
136
PB
237
PE
738
PE
839
PE
940
PE
10
41
PE
11
42
PE
12
43
PE
13
44
PE
14
45
PE
15
46
PB
10
47
PB
11
48
VSS149
VDD150
PB
12
51
PB
13
52
PB
14
53
PB
15
54
PD
855
PD
956
PD
10
57
PD
11
58
PD
12
59
PD
13
60
PD
14
61
PD
15
62
PC6 63
PC7 64
PC8 65
PC9 66
PA
867
PA
968
PA
10
69
PA
11
70
PA
12
71
PA
13
72
NC73
VSS274
VDD275
PA
14
76
PA
15
77
PC10 78
PC11 79
PC12 80
PD
081
PD
182
PD
283
PD
384
PD
485
PD
586
PD
687
PD
788
PB
389
PB
490
PB
591
PB
692
PB
793
BOOT94
PB
895
PB
996
PE
097
PE
198
VSS399
VDD3100
U2
STHV748
AG
ND
11
RE
F1_H
VM
12
HV
M1_A
3
HV
M0_A
4,6
5
HVOUT_A 5
HV
P0_A
6
RE
F1_H
VP
17
HV
P1_A
8
HV
P1_B
9
RE
F1_H
VP
010
HV
P0_B
11
HVOUT_B 12
HV
M0_B
13
HV
M1_B
14
RE
F1_H
VM
015
D_CTR16 IN417
IN1_B18
IN2_B19
IN3_B20
VD
DP
121
GND_PWR_B 22
XDCR_B 23
LVOUT_B 24
LVOUT_C 25
XDCR_C 26
GND_PWR_C 27
VD
DM
128
IN3_C29 IN2_C30 IN1_C31
THSD32
AG
ND
233
RE
F2_H
VM
134
HV
M1_C
35
HV
M0_C
36
HVOUT_C 37
HV
P0_C
38
RE
F2_H
VP
139
HV
P1_C
40
HV
P1_D
41
RE
F2_H
VP
042
HV
P0_D
43
HVOUT_D 44
HV
M0_D
45
HV
M1_D
46
RE
F2_H
VM
047
DG
ND
48
DV
DD
49
IN1_D50
IN2_D51
IN3_D52
VD
DP
253
GND_PWR_D 54
XDCR_D 55
LVOUT_D 56
LVOUT_A 57
XDCR_A 58
GND_PWR_A 59
VD
DM
260
IN3_A61 IN2_A62 IN1_A63
INT_B
IAS
64
RF1107k
RF262k
RF4107k
RF362k
REG2
LT3032
OUTP1
ADJP 2BYPP 3
GND4,5
INN
6,9
OUTN
7
ADJN 8
BYPN 11
SHD10,12INP
14
X1
8MHz
Cosc222pF
Rosc
1M
OSC_INOSC_OUT
OSC_INOSC_OUT
REG1 LD1117
GNDOUTIN
CF210FCB1
100nF
+5V
DVDD
DVDD
SHD
AVDD
AVSS
CC1
10nF
CC2
10nF
Cosc122pF CR5
3.9nF
CR1
22nF
CR6
3.9nF
CR7
3.9nF
CR8
3.9nF
CR2
22nF
CR3
22nF
CR4
22nF
CB25
220nF
CB27
220nF
CB26
220nF
CB21
220nF
CB23
220nF
CB24
220nF
CB22
220nF
HVM1
CB28
220nF
CF10
10F
CF9
10F
SHD
XDCRA
XDCRB
XDCRC
XDCRD
HVP1
HV+HV-
HVM1
HV+HV-
SP
I_C
LK
SP
I _C
LK
SP
I1_M
ISO
SP
I2_M
ISO
SP
I_C
LK
SP
I3_M
ISOS
PI_
CLKU
SB
DP
US
BD
MJT
MS
JT
CK
JT
DI SP
I_JT
AG
_1
SP
I_JTA
G_2
JT
DO
JRS
T
STR PRG STP USRCP1
100nF
CP2
100nF
CP3
100nF
CP4
100nF
P1
P2
P3
P4
RP110k
RP210k
RP310k
RP410k
P1 P2 P3 P4
DVDD
L1 L2 L3 L4
RL156
RL256
RL356
RL456
L1 L2 L3 L4
L1
L2
L3
L4
AD
C_IN
0A
DC
_IN
1A
DC
_IN
2
VDD
LV+LV-
VSS
LV+LV-
-5V
CF310F
CF410F
-5V
CF610F
CF510F
CF110F
+5V
GND_PWR
GN
D_P
WR
HVP1
RLA100
RLB100
RLC100
RLD100
CLA
270pF
CLB
270pF
CLC
270pF
CLD
270pF
GND_PWR
USB
1734035-1
VBUS 1
D+ 3
D- 2
GND 5Shell
ID 4
PC0PC1PC2PC3PC4PC5PC6
PC15PC14PC13
PC10PC11PC12
PC0PC1PC2PC5PC4PC3PC10PC11PC12PC6
UF1
USBUF01W6
D1 1
GND
2
D2 3D34VDD
5
D46
DVDD
USBDPUSBDM
D2
BAT20J
+5V
D1BAT20J
CB2
100nF
CB3
100nF
CB4
100nF
CB5
100nF
CB6
100nF
DVDD
SPI2_MISO
SPI3_MISO
SPI1_MISO SPI1
SPI2
SPI3
PC11
PC10
PC12
CB7
100nF
CB8
100nF
CB9
100nF
CB10
100nF
AVDD
AVSS
CB11
100nF
CB12
100nF
RSTCRST
100nF
NRST
NRST
JTMS
JTCK
JTDI
JTDO
JRST
USB_PWR
R18 330
RSHD330
RAD3100k
RAD42.7k
ADC_IN2
RAD12.7k
RAD2100k
ADC_IN0
HVP1
HVM1
AVDD
JTAG
DVDD
POT150 %
ADC_IN1
L5
RL556
L6
RL656
L5 L6
L5
L6
RE056
RE156
RE256
RE356
RE456
RE556
RE656
RE756
THSD
THSD
RTHSD10k
HVP1HVP0
HVP1HVP0
HVM1HVM0
HVM1HVM0
CB17
220nF
CB19
220nF
CB18
220nF
CB13
220nF
CB15
220nF
CB16
220nF
CB14
220nF
HVM0
CB20
220nF
CF8
10F
CF7
10F
HVP0
HV+HV-
HVM0
HV+HV-
GND_PWR
HVP0
ZAD2
DZ2S033
CAD2100nF
CAD1
100nF
RHVP
0
HVP0HVP1
RHVM
0
HVM0HVM1 RGND
0
GND_PWR
BOOT0
ZAD1DZ2S033
NRST
DVDD
C2_F2_F4
2.2F
C1_F2_F4
2.2F
R3_F10
R2_F10
R1_F1_F4
0
R2_F2_F40
R1_F20
DVDD
AU
X1
AU
X2
AU
X3
AU
X0
AU
X4
AU
X5
AU
X6
AU
X7
AUX1 AUX2 AUX3AUX0 AUX4 AUX5 AUX6 AUX7
PC13
PC
PC14PC15
LVOUTA
LVOUTB
LVOUTC
LVOUTDRRA100
RRB100
RRC100
RRD100
CRA
270pF
CRB
270pF
CRC
270pF
CRD
270pF
USR_RX
AN_SUPPLY
AVDD
AVSS
STM32F427
GSPG2807151415SG
PCB layout UM1957
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6 PCB layout Figure 23: Top layer
Figure 24: Inner 1
UM1957 PCB layout
DocID028424 Rev 1 25/28
Figure 25: Inner 2
Figure 26: Inner 3
PCB layout UM1957
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Figure 27: Inner 4
Figure 28: Bottom layer
UM1957 Revision history
DocID028424 Rev 1 27/28
7 Revision history Table 9: Document revision history
Date Version Changes
26-Nov-2015 1 Initial release.
UM1957
28/28 DocID028424 Rev 1
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