Stellaris LM4F120H5QR Microcontroller

TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION

Stellaris LM4F120H5QR MicrocontrollerD ATA SHE E T

D S -LM4F 120H5 Q R- . S P M S 294E

C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated

CopyrightCopyright 2007-2013 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

2 Texas Instruments-Advance Information

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Stellaris LM4F120H5QR Microcontroller

Table of ContentsRevision History ............................................................................................................................. 34 About This Document .................................................................................................................... 41Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 41 41 41 42 44 45 48 48 50 52 56 62 64 64 65

11.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.4

Architectural Overview .......................................................................................... 44Stellaris LM4F Series Overview ..................................................................................... LM4F120H5QR Microcontroller Overview ....................................................................... LM4F120H5QR Microcontroller Features ........................................................................ ARM Cortex-M4F Processor Core .................................................................................. On-Chip Memory ........................................................................................................... Serial Communications Peripherals ................................................................................ System Integration ........................................................................................................ Analog .......................................................................................................................... JTAG and ARM Serial Wire Debug ................................................................................ Packaging and Temperature .......................................................................................... LM4F120H5QR Microcontroller Hardware Details ...........................................................

22.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 2.5.4

The Cortex-M4F Processor ................................................................................... 66Block Diagram .............................................................................................................. 67 Overview ...................................................................................................................... 68 System-Level Interface .................................................................................................. 68 Integrated Configurable Debug ...................................................................................... 68 Trace Port Interface Unit (TPIU) ..................................................................................... 69 Cortex-M4F System Component Details ......................................................................... 69 Programming Model ...................................................................................................... 70 Processor Mode and Privilege Levels for Software Execution ........................................... 70 Stacks .......................................................................................................................... 71 Register Map ................................................................................................................ 71 Register Descriptions .................................................................................................... 73 Exceptions and Interrupts .............................................................................................. 89 Data Types ................................................................................................................... 89 Memory Model .............................................................................................................. 89 Memory Regions, Types and Attributes ........................................................................... 91 Memory System Ordering of Memory Accesses .............................................................. 92 Behavior of Memory Accesses ....................................................................................... 92 Software Ordering of Memory Accesses ......................................................................... 93 Bit-Banding ................................................................................................................... 94 Data Storage ................................................................................................................ 96 Synchronization Primitives ............................................................................................. 97 Exception Model ........................................................................................................... 98 Exception States ........................................................................................................... 99 Exception Types ............................................................................................................ 99 Exception Handlers ..................................................................................................... 103 Vector Table ................................................................................................................ 103

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Table of Contents

2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8

Exception Priorities ...................................................................................................... Interrupt Priority Grouping ............................................................................................ Exception Entry and Return ......................................................................................... Fault Handling ............................................................................................................. Fault Types ................................................................................................................. Fault Escalation and Hard Faults .................................................................................. Fault Status Registers and Fault Address Registers ...................................................... Lockup ....................................................................................................................... Power Management .................................................................................................... Entering Sleep Modes ................................................................................................. Wake Up from Sleep Mode .......................................................................................... Instruction Set Summary ..............................................................................................

104 105 105 108 109 109 110 110 111 111 111 112

33.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 3.4 3.5 3.6 3.7

Cortex-M4 Peripherals ......................................................................................... 119Functional Description ................................................................................................. 119 System Timer (SysTick) ............................................................................................... 120 Nested Vectored Interrupt Controller (NVIC) .................................................................. 121 System Control Block (SCB) ........................................................................................ 122 Memory Protection Unit (MPU) ..................................................................................... 122 Floating-Point Unit (FPU) ............................................................................................. 127 Register Map .............................................................................................................. 131 System Timer (SysTick) Register Descriptions .............................................................. 134 NVIC Register Descriptions .......................................................................................... 138 System Control Block (SCB) Register Descriptions ........................................................ 153 Memory Protection Unit (MPU) Register Descriptions .................................................... 182 Floating-Point Unit (FPU) Register Descriptions ............................................................ 191

44.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2

JTAG Interface ...................................................................................................... 197Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. 198 198 199 199 201 201 202 204 204 205 207 209 209 209 210 215 215 216 223 226 227

55.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.4

System Control ..................................................................................................... 209


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5.5 5.6

System Control Register Descriptions ........................................................................... 231 System Control Legacy Register Descriptions ............................................................... 390

66.1 6.2 6.3

System Exception Module ................................................................................... 447Functional Description ................................................................................................. 447 Register Map .............................................................................................................. 447 Register Descriptions .................................................................................................. 447

77.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.6

Hibernation Module .............................................................................................. 455Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Register Access Timing ............................................................................................... Hibernation Clock Source ............................................................................................ System Implementation ............................................................................................... Battery Management ................................................................................................... Real-Time Clock .......................................................................................................... Battery-Backed Memory .............................................................................................. Power Control Using HIB ............................................................................................. Power Control Using VDD3ON Mode ........................................................................... Initiating Hibernate ...................................................................................................... Waking from Hibernate ................................................................................................ Arbitrary Power Removal ............................................................................................. Interrupts and Status ................................................................................................... Initialization and Configuration ..................................................................................... Initialization ................................................................................................................. RTC Match Functionality (No Hibernation) .................................................................... RTC Match/Wake-Up from Hibernation ......................................................................... External Wake-Up from Hibernation .............................................................................. RTC or External Wake-Up from Hibernation .................................................................. Register Map .............................................................................................................. Register Descriptions .................................................................................................. 456 456 457 457 458 459 460 461 463 463 463 463 464 464 464 465 465 466 466 466 467 467 468

88.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.4 8.5 8.6

Internal Memory ................................................................................................... 486Block Diagram ............................................................................................................ 486 Functional Description ................................................................................................. 487 SRAM ........................................................................................................................ 487 ROM .......................................................................................................................... 488 Flash Memory ............................................................................................................. 490 EEPROM .................................................................................................................... 495 Register Map .............................................................................................................. 501 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 502 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 520 Memory Register Descriptions (System Control Offset) .................................................. 536

99.1 9.2 9.2.1 9.2.2 9.2.3

Micro Direct Memory Access (DMA) ................................................................ 545Block Diagram ............................................................................................................ 546 Functional Description ................................................................................................. 546 Channel Assignments .................................................................................................. 547 Priority ........................................................................................................................ 548 Arbitration Size ............................................................................................................ 548


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9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 9.5 9.6

Request Types ............................................................................................................ Channel Configuration ................................................................................................. Transfer Modes ........................................................................................................... Transfer Size and Increment ........................................................................................ Peripheral Interface ..................................................................................................... Software Request ........................................................................................................ Interrupts and Errors .................................................................................................... Initialization and Configuration ..................................................................................... Module Initialization ..................................................................................................... Configuring a Memory-to-Memory Transfer ................................................................... Configuring a Peripheral for Simple Transmit ................................................................ Configuring a Peripheral for Ping-Pong Receive ............................................................ Configuring Channel Assignments ................................................................................ Register Map .............................................................................................................. DMA Channel Control Structure ................................................................................. DMA Register Descriptions ........................................................................................

548 549 551 559 559 559 560 560 560 561 562 564 566 566 568 575

1010.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.4 10.5

General-Purpose Input/Outputs (GPIOs) ........................................................... 609Signal Description ....................................................................................................... 609 Functional Description ................................................................................................. 611 Data Control ............................................................................................................... 613 Interrupt Control .......................................................................................................... 614 Mode Control .............................................................................................................. 615 Commit Control ........................................................................................................... 616 Pad Control ................................................................................................................. 616 Identification ............................................................................................................... 616 Initialization and Configuration ..................................................................................... 616 Register Map .............................................................................................................. 618 Register Descriptions .................................................................................................. 620

1111.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6

General-Purpose Timers ...................................................................................... 663Block Diagram ............................................................................................................ 664 Signal Description ....................................................................................................... 665 Functional Description ................................................................................................. 666 GPTM Reset Conditions .............................................................................................. 667 Timer Modes ............................................................................................................... 668 Wait-for-Trigger Mode .................................................................................................. 677 Synchronizing GP Timer Blocks ................................................................................... 678 DMA Operation ........................................................................................................... 678 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 679 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 679 Initialization and Configuration ..................................................................................... 681 One-Shot/Periodic Timer Mode .................................................................................... 681 Real-Time Clock (RTC) Mode ...................................................................................... 682 Input Edge-Count Mode ............................................................................................... 682 Input Edge Timing Mode .............................................................................................. 683 PWM Mode ................................................................................................................. 683 Register Map .............................................................................................................. 684 Register Descriptions .................................................................................................. 685


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1212.1 12.2 12.2.1 12.3 12.4 12.5

Watchdog Timers ................................................................................................. 733Block Diagram ............................................................................................................ Functional Description ................................................................................................. Register Access Timing ............................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 734 734 735 735 735 736

1313.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.4.1 13.4.2 13.5 13.6

Analog-to-Digital Converter (ADC) ..................................................................... 758Block Diagram ............................................................................................................ 759 Signal Description ....................................................................................................... 760 Functional Description ................................................................................................. 761 Sample Sequencers .................................................................................................... 761 Module Control ............................................................................................................ 762 Hardware Sample Averaging Circuit ............................................................................. 765 Analog-to-Digital Converter .......................................................................................... 766 Differential Sampling ................................................................................................... 769 Internal Temperature Sensor ........................................................................................ 771 Digital Comparator Unit ............................................................................................... 772 Initialization and Configuration ..................................................................................... 776 Module Initialization ..................................................................................................... 776 Sample Sequencer Configuration ................................................................................. 777 Register Map .............................................................................................................. 777 Register Descriptions .................................................................................................. 779

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Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 849850 850 851 851 852 853 853 854 855 856 857 857 858 859 859 859 861 862 913 913 914 914 915

14.1 Block Diagram ............................................................................................................ 14.2 Signal Description ....................................................................................................... 14.3 Functional Description ................................................................................................. 14.3.1 Transmit/Receive Logic ............................................................................................... 14.3.2 Baud-Rate Generation ................................................................................................. 14.3.3 Data Transmission ...................................................................................................... 14.3.4 Serial IR (SIR) ............................................................................................................. 14.3.5 ISO 7816 Support ....................................................................................................... 14.3.6 Modem Handshake Support ......................................................................................... 14.3.7 LIN Support ................................................................................................................ 14.3.8 9-Bit UART Mode ........................................................................................................ 14.3.9 FIFO Operation ........................................................................................................... 14.3.10 Interrupts .................................................................................................................... 14.3.11 Loopback Operation .................................................................................................... 14.3.12 DMA Operation ........................................................................................................... 14.4 Initialization and Configuration ..................................................................................... 14.5 Register Map .............................................................................................................. 14.6 Register Descriptions ..................................................................................................

1515.1 15.2 15.3 15.3.1 15.3.2

Synchronous Serial Interface (SSI) .................................................................... 912Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ...........................................................................................................


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15.3.3 15.3.4 15.3.5 15.4 15.5 15.6

Interrupts .................................................................................................................... Frame Formats ........................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions ..................................................................................................

915 916 923 924 925 926

1616.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.4 16.5 16.6 16.7 16.8

Inter-Integrated Circuit (I2C) Interface ................................................................ 955Block Diagram ............................................................................................................ 956 Signal Description ....................................................................................................... 956 Functional Description ................................................................................................. 957 I2C Bus Functional Overview ........................................................................................ 957 Available Speed Modes ............................................................................................... 961 Interrupts .................................................................................................................... 963 Loopback Operation .................................................................................................... 964 Command Sequence Flow Charts ................................................................................ 964 Initialization and Configuration ..................................................................................... 972 Register Map .............................................................................................................. 974 Register Descriptions (I2C Master) ............................................................................... 975 Register Descriptions (I2C Slave) ................................................................................. 990 Register Descriptions (I2C Status and Control) ............................................................ 1000

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Controller Area Network (CAN) Module ........................................................... 1003

17.1 Block Diagram ........................................................................................................... 1004 17.2 Signal Description ..................................................................................................... 1004 17.3 Functional Description ............................................................................................... 1005 17.3.1 Initialization ............................................................................................................... 1006 17.3.2 Operation .................................................................................................................. 1006 17.3.3 Transmitting Message Objects ................................................................................... 1007 17.3.4 Configuring a Transmit Message Object ...................................................................... 1008 17.3.5 Updating a Transmit Message Object ......................................................................... 1009 17.3.6 Accepting Received Message Objects ........................................................................ 1009 17.3.7 Receiving a Data Frame ............................................................................................ 1010 17.3.8 Receiving a Remote Frame ........................................................................................ 1010 17.3.9 Receive/Transmit Priority ........................................................................................... 1010 17.3.10 Configuring a Receive Message Object ...................................................................... 1011 17.3.11 Handling of Received Message Objects ...................................................................... 1012 17.3.12 Handling of Interrupts ................................................................................................ 1014 17.3.13 Test Mode ................................................................................................................. 1015 17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1017 17.3.15 Bit Time and Bit Rate ................................................................................................. 1017 17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1019 17.4 Register Map ............................................................................................................ 1022 17.5 CAN Register Descriptions ......................................................................................... 1023

1818.1 18.2 18.3 18.3.1

Universal Serial Bus (USB) Controller ............................................................. 1053Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Operation .................................................................................................................. 1054 1054 1054 1054


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18.3.2 18.4 18.4.1 18.5 18.6

DMA Operation ......................................................................................................... 1059 Initialization and Configuration .................................................................................... 1060 Endpoint Configuration .............................................................................................. 1061 Register Map ............................................................................................................ 1061 Register Descriptions ................................................................................................. 1064

1919.1 19.2 19.3 19.3.1 19.4 19.5 19.6

Analog Comparators .......................................................................................... 1110Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Internal Reference Programming ................................................................................ Initialization and Configuration .................................................................................... Register Map ............................................................................................................ Register Descriptions ................................................................................................. 1111 1111 1112 1113 1115 1115 1116

20 2121.1 21.2 21.3 21.4 21.5 21.6

Pin Diagram ........................................................................................................ 1125 Signal Tables ...................................................................................................... 1126Signals by Pin Number .............................................................................................. Signals by Signal Name ............................................................................................. Signals by Function, Except for GPIO ......................................................................... GPIO Pins and Alternate Functions ............................................................................ Possible Pin Assignments for Alternate Functions ....................................................... Connections for Unused Signals ................................................................................. 1127 1132 1137 1141 1144 1146

22 23

Operating Characteristics ................................................................................. 1148 Electrical Characteristics .................................................................................. 1149

23.1 Maximum Ratings ...................................................................................................... 1149 23.2 Recommended Operating Conditions ......................................................................... 1150 23.3 Load Conditions ........................................................................................................ 1152 23.4 JTAG and Boundary Scan .......................................................................................... 1153 23.5 Power and Brown-Out ............................................................................................... 1155 23.6 Reset ........................................................................................................................ 1156 23.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1158 23.8 Clocks ...................................................................................................................... 1159 23.8.1 PLL Specifications ..................................................................................................... 1159 23.8.2 PIOSC Specifications ................................................................................................ 1161 23.8.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1162 23.8.4 Hibernation Clock Source Specifications ..................................................................... 1163 23.8.5 Main Oscillator Specifications ..................................................................................... 1164 23.8.6 System Clock Specification with ADC Operation .......................................................... 1168 23.8.7 System Clock Specification with USB Operation .......................................................... 1169 23.9 Sleep Modes ............................................................................................................. 1170 23.10 Hibernation Module ................................................................................................... 1171 23.11 Flash Memory and EEPROM ..................................................................................... 1172 23.12 Input/Output Pin Characteristics ................................................................................. 1173 23.12.1 GPIO Module Characteristics ..................................................................................... 1173 23.12.2 Types of I/O Pins and ESD Protection ......................................................................... 1173 23.13 Analog-to-Digital Converter (ADC) .............................................................................. 1176 23.14 Synchronous Serial Interface (SSI) ............................................................................. 1178 23.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1180


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23.16 Universal Serial Bus (USB) Controller ......................................................................... 23.17 Analog Comparator ................................................................................................... 23.18 Current Consumption ................................................................................................. 23.18.1 Preliminary Current Consumption ...............................................................................

1181 1182 1184 1184 1186 1186 1186 1187

AA.1 A.2 A.3 A.4

Ordering and Contact Information ................................................................... 1186Ordering Information .................................................................................................. Part Markings ............................................................................................................ Kits ........................................................................................................................... Support Information ...................................................................................................

BB.1 B.1.1

Package Information .......................................................................................... 118864-Pin LQFP Package ............................................................................................... 1188 Package Dimensions ................................................................................................. 1188


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List of FiguresFigure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 8-1. Figure 8-2. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Figure 11-7. Stellaris Blizzard-class Block Diagram ................................................................ 45 Stellaris LM4F120H5QR Microcontroller High-Level Block Diagram ........................ 47 CPU Block Diagram ............................................................................................. 68 TPIU Block Diagram ............................................................................................ 69 Cortex-M4F Register Set ...................................................................................... 72 Bit-Band Mapping ................................................................................................ 96 Data Storage ....................................................................................................... 97 Vector Table ...................................................................................................... 104 Exception Stack Frame ...................................................................................... 107 SRD Use Example ............................................................................................. 125 FPU Register Bank ............................................................................................ 128 JTAG Module Block Diagram .............................................................................. 198 Test Access Port State Machine ......................................................................... 201 IDCODE Register Format ................................................................................... 207 BYPASS Register Format ................................................................................... 207 Boundary Scan Register Format ......................................................................... 208 Basic RST Configuration .................................................................................... 212 External Circuitry to Extend Power-On Reset ....................................................... 212 Reset Circuit Controlled by Switch ...................................................................... 213 Power Architecture ............................................................................................ 216 Main Clock Tree ................................................................................................ 219 Module Clock Selection ...................................................................................... 226 Hibernation Module Block Diagram ..................................................................... 456 Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 458 Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 459 Using a Regulator for Both VDD and VBAT ............................................................ 460 Internal Memory Block Diagram .......................................................................... 486 EEPROM Block Diagram ................................................................................... 487 DMA Block Diagram ......................................................................................... 546 Example of Ping-Pong DMA Transaction ........................................................... 552 Memory Scatter-Gather, Setup and Configuration ................................................ 554 Memory Scatter-Gather, DMA Copy Sequence .................................................. 555 Peripheral Scatter-Gather, Setup and Configuration ............................................. 557 Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 558 Digital I/O Pads ................................................................................................. 612 Analog/Digital I/O Pads ...................................................................................... 613 GPIODATA Write Example ................................................................................. 614 GPIODATA Read Example ................................................................................. 614 GPTM Module Block Diagram ............................................................................ 664 Reading the RTC Value ...................................................................................... 671 Input Edge-Count Mode Example, Counting Down ............................................... 673 16-Bit Input Edge-Time Mode Example ............................................................... 674 16-Bit PWM Mode Example ................................................................................ 676 CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 676 CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 677


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Figure 11-8. Figure 11-9. Figure 12-1. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 13-13. Figure 13-14. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Figure 15-10. Figure 15-11. Figure 15-12. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 16-5. Figure 16-6. Figure 16-7. Figure 16-8. Figure 16-9. Figure 16-10. Figure 16-11. Figure 16-12. Figure 16-13. Figure 16-14.

CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 677 Timer Daisy Chain ............................................................................................. 678 WDT Module Block Diagram .............................................................................. 734 Implementation of Two ADC Blocks .................................................................... 759 ADC Module Block Diagram ............................................................................... 760 ADC Sample Phases ......................................................................................... 763 Doubling the ADC Sample Rate .......................................................................... 764 Skewed Sampling .............................................................................................. 764 Sample Averaging Example ............................................................................... 766 ADC Input Equivalency Diagram ......................................................................... 767 ADC Voltage Reference ..................................................................................... 768 ADC Conversion Result ..................................................................................... 769 Differential Voltage Representation ..................................................................... 771 Internal Temperature Sensor Characteristic ......................................................... 772 Low-Band Operation (CIC=0x0) .......................................................................... 774 Mid-Band Operation (CIC=0x1) .......................................................................... 775 High-Band Operation (CIC=0x3) ......................................................................... 776 UART Module Block Diagram ............................................................................. 850 UART Character Frame ..................................................................................... 852 IrDA Data Modulation ......................................................................................... 854 LIN Message ..................................................................................................... 856 LIN Synchronization Field ................................................................................... 857 SSI Module Block Diagram ................................................................................. 913 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 917 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 917 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 918 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 918 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 919 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 920 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 920 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 921 MICROWIRE Frame Format (Single Frame) ........................................................ 922 MICROWIRE Frame Format (Continuous Transfer) ............................................. 923 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 923 I2C Block Diagram ............................................................................................. 956 I2C Bus Configuration ........................................................................................ 957 START and STOP Conditions ............................................................................. 958 Complete Data Transfer with a 7-Bit Address ....................................................... 958 R/S Bit in First Byte ............................................................................................ 959 Data Validity During Bit Transfer on the I2C Bus ................................................... 959 High-Speed Data Format ................................................................................... 963 Master Single TRANSMIT .................................................................................. 965 Master Single RECEIVE ..................................................................................... 966 Master TRANSMIT of Multiple Data Bytes ........................................................... 967 Master RECEIVE of Multiple Data Bytes ............................................................. 968 Master RECEIVE with Repeated START after Master TRANSMIT ........................ 969 Master TRANSMIT with Repeated START after Master RECEIVE ........................ 970 High Speed Mode Master Transmit ..................................................................... 971


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Slave Command Sequence ................................................................................ 972 CAN Controller Block Diagram .......................................................................... 1004 CAN Data/Remote Frame ................................................................................. 1005 Message Objects in a FIFO Buffer .................................................................... 1014 CAN Bit Time ................................................................................................... 1018 USB Module Block Diagram ............................................................................. 1054 Analog Comparator Module Block Diagram ....................................................... 1111 Structure of Comparator Unit ............................................................................ 1112 Comparator Internal Reference Structure .......................................................... 1113 64-Pin LQFP Package Pin Diagram .................................................................. 1125 Load Conditions ............................................................................................... 1152 JTAG Test Clock Input Timing ........................................................................... 1153 JTAG Test Access Port (TAP) Timing ................................................................ 1154 External Reset Timing (RST) ............................................................................ 1156 Software Reset Timing ..................................................................................... 1156 Watchdog Reset Timing ................................................................................... 1156 MOSC Failure Reset Timing ............................................................................. 1157 Hibernation Module Timing ............................................................................... 1171 ESD Protection on Fail-Safe Pins ...................................................................... 1174 ESD Protection on Non-Fail-Safe Pins .............................................................. 1175 ADC Input Equivalency Diagram ....................................................................... 1177 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................. 1178 Figure 23-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1179 Figure 23-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1179 Figure 23-15. I2C Timing ....................................................................................................... 1180 Figure B-1. Stellaris LM4F120H5QR 64-Pin LQFP Package ............................................... 1188

Figure 16-15. Figure 17-1. Figure 17-2. Figure 17-3. Figure 17-4. Figure 18-1. Figure 19-1. Figure 19-2. Figure 19-3. Figure 20-1. Figure 23-1. Figure 23-2. Figure 23-3. Figure 23-4. Figure 23-5. Figure 23-6. Figure 23-7. Figure 23-8. Figure 23-9. Figure 23-10. Figure 23-11. Figure 23-12.


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List of TablesTable 1. Table 2. Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 8-1. Table 8-2. Revision History .................................................................................................. 34 Documentation Conventions ................................................................................ 42 Stellaris LM4F Device Series ................................................................................ 45 Stellaris LM4F120H5QR Microcontroller Features ................................................. 46 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 71 Processor Register Map ....................................................................................... 72 PSR Register Combinations ................................................................................. 78 Memory Map ....................................................................................................... 89 Memory Access Behavior ..................................................................................... 92 SRAM Memory Bit-Banding Regions .................................................................... 94 Peripheral Memory Bit-Banding Regions ............................................................... 94 Exception Types ................................................................................................ 100 Interrupts .......................................................................................................... 101 Exception Return Behavior ................................................................................. 108 Faults ............................................................................................................... 109 Fault Status and Fault Address Registers ............................................................ 110 Cortex-M4F Instruction Summary ....................................................................... 112 Core Peripheral Register Regions ....................................................................... 119 Memory Attributes Summary .............................................................................. 123 TEX, S, C, and B Bit Field Encoding ................................................................... 125 Cache Policy for Memory Attribute Encoding ....................................................... 126 AP Bit Field Encoding ........................................................................................ 126 Memory Region Attributes for Stellaris Microcontrollers ........................................ 127 QNaN and SNaN Handling ................................................................................. 130 Peripherals Register Map ................................................................................... 131 Interrupt Priority Levels ...................................................................................... 161 Example SIZE Field Values ................................................................................ 189 JTAG_SWD_SWO Signals (64LQFP) ................................................................. 198 JTAG Port Pins State after Power-On Reset or RST assertion .............................. 199 JTAG Instruction Register Commands ................................................................. 205 System Control & Clocks Signals (64LQFP) ........................................................ 209 Reset Sources ................................................................................................... 210 Clock Source Options ........................................................................................ 217 Possible System Clock Frequencies Using the SYSDIV Field ............................... 220 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 220 Examples of Possible System Clock Frequencies with DIV400=1 ......................... 221 System Control Register Map ............................................................................. 227 RCC2 Fields that Override RCC Fields ............................................................... 253 System Exception Register Map ......................................................................... 447 Hibernate Signals (64LQFP) ............................................................................... 456 Counter Behavior with a TRIM Value of 0x8003 ................................................... 462 Counter Behavior with a TRIM Value of 0x7FFC .................................................. 463 Hibernation Module Clock Operation ................................................................... 466 Hibernation Module Register Map ....................................................................... 467 Flash Memory Protection Policy Combinations .................................................... 491 User-Programmable Flash Memory Resident Registers ....................................... 495


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Table 8-3. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12.

Flash Register Map ............................................................................................ 501 DMA Channel Assignments .............................................................................. 547 Request Type Support ....................................................................................... 549 Control Structure Memory Map ........................................................................... 550 Channel Control Structure .................................................................................. 550 DMA Read Example: 8-Bit Peripheral ................................................................ 559 DMA Interrupt Assignments .............................................................................. 560 Channel Control Structure Offsets for Channel 30 ................................................ 561 Channel Control Word Configuration for Memory Transfer Example ...................... 561 Channel Control Structure Offsets for Channel 7 .................................................. 562 Channel Control Word Configuration for Peripheral Transmit Example .................. 563 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 564 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 565 Table 9-13. DMA Register Map .......................................................................................... 567 Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 610 Table 10-2. GPIO Pins and Alternate Functions (64LQFP) ..................................................... 610 Table 10-3. GPIO Pad Configuration Examples ..................................................................... 617 Table 10-4. GPIO Interrupt Configuration Example ................................................................ 617 Table 10-5. GPIO Pins With Non-Zero Reset Values .............................................................. 619 Table 10-6. GPIO Register Map ........................................................................................... 619 Table 10-7. GPIO Pins With Non-Zero Reset Values .............................................................. 630 Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 636 Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 638 Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 641 Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 647 Table 11-1. Available CCP Pins ............................................................................................ 665 Table 11-2. General-Purpose Timers Signals (64LQFP) ......................................................... 665 Table 11-3. General-Purpose Timer Capabilities .................................................................... 667 Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 668 Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 669 Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 670 Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 670 Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 672 Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 673 Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 675 Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 678 Table 11-12. Timers Register Map .......................................................................................... 685 Table 12-1. Watchdog Timers Register Map .......................................................................... 736 Table 13-1. ADC Signals (64LQFP) ...................................................................................... 760 Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 761 Table 13-3. Differential Sampling Pairs ................................................................................. 769 Table 13-4. ADC Register Map ............................................................................................. 777 Table 14-1. UART Signals (64LQFP) .................................................................................... 851 Table 14-2. Flow Control Mode ............................................................................................. 855 Table 14-3. UART Register Map ........................................................................................... 861 Table 15-1. SSI Signals (64LQFP) ........................................................................................ 914 Table 15-2. SSI Register Map .............................................................................................. 925


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Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 22-1. Table 22-2. Table 22-3. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 23-14. Table 23-15. Table 23-16.

I2C Signals (64LQFP) ........................................................................................ 956 Examples of I2C Master Timer Period versus Speed Mode ................................... 962 Examples of I2C Master Timer Period in High-Speed Mode .................................. 963 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 974 Write Field Decoding for I2CMCS[3:0] Field ......................................................... 980 Controller Area Network Signals (64LQFP) ........................................................ 1005 Message Object Configurations ........................................................................ 1010 CAN Protocol Ranges ...................................................................................... 1018 CANBIT Register Values .................................................................................. 1018 CAN Register Map ........................................................................................... 1022 USB Signals (64LQFP) .................................................................................... 1054 Remainder (MAXLOAD/4) ................................................................................ 1060 Actual Bytes Read ........................................................................................... 1060 Packet Sizes That Clear RXRDY ...................................................................... 1060 Universal Serial Bus (USB) Controller Register Map ........................................... 1061 Analog Comparators Signals (64LQFP) ............................................................. 1111 Internal Reference Voltage and ACREFCTL Field Values ................................... 1113 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1114 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1114 Analog Comparators Register Map ................................................................... 1115 GPIO Pins With Default Alternate Functions ...................................................... 1126 Signals by Pin Number ..................................................................................... 1127 Signals by Signal Name ................................................................................... 1132 Signals by Function, Except for GPIO ............................................................... 1137 GPIO Pins and Alternate Functions ................................................................... 1141 Possible Pin Assignments for Alternate Functions .............................................. 1144 Connections for Unused Signals (64-Pin LQFP) ................................................. 1146 Temperature Characteristics ............................................................................. 1148 Thermal Characteristics ................................................................................... 1148 ESD Absolute Maximum Ratings ...................................................................... 1148 Maximum Ratings ............................................................................................ 1149 Recommended DC Operating Conditions .......................................................... 1150 GPIO Current Restrictions ................................................................................ 1150 GPIO Package Side Assignments ..................................................................... 1150 JTAG Characteristics ....................................................................................... 1153 Power Characteristics ...................................................................................... 1155 Reset Characteristics ....................................................................................... 1156 LDO Regulator Characteristics ......................................................................... 1158 Phase Locked Loop (PLL) Characteristics ......................................................... 1159 Actual PLL Frequency ...................................................................................... 1159 PIOSC Clock Characteristics ............................................................................ 1161 Low-Frequency internal Oscillator Characteristics .............................................. 1162 Hibernation Oscillator Input Characteristics ........................................................ 1163 Main Oscillator Input Characteristics ................................................................. 1164 Crystal Parameters .......................................................................................... 1165 Supported MOSC Crystal Frequencies .............................................................. 1166


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Table 23-17. Table 23-18. Table 23-19. Table 23-20. Table 23-21. Table 23-22. Table 23-23. Table 23-24. Table 23-25. Table 23-26. Table 23-27. Table 23-28. Table 23-29. Table 23-30. Table 23-31.

System Clock Characteristics with ADC Operation ............................................. 1168 System Clock Characteristics with USB Operation ............................................. 1169 Sleep Modes AC Characteristics ....................................................................... 1170 Hibernation Module Battery Characteristics ....................................................... 1171 Hibernation Module AC Characteristics ............................................................. 1171 Flash Memory Characteristics ........................................................................... 1172 EEPROM Characteristics ................................................................................. 1172 GPIO Module Characteristics ............................................................................ 1173 Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1175 ADC Electrical Characteristics .......................................................................... 1176 SSI Characteristics .......................................................................................... 1178 I2C Characteristics ........................................................................................... 1180 Analog Comparator Characteristics ................................................................... 1182 Analog Comparator Voltage Reference Characteristics ...................................... 1182 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1182 Table 23-32. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1183 Table 23-33. Preliminary Current Consumption ..................................................................... 1184 Table A-1. Part Ordering Information ................................................................................. 1186


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List of RegistersThe Cortex-M4F Processor ........................................................................................................... 66Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 74 Cortex General-Purpose Register 1 (R1) ........................................................................... 74 Cortex General-Purpose Register 2 (R2) ........................................................................... 74 Cortex General-Purpose Register 3 (R3) ........................................................................... 74 Cortex General-Purpose Register 4 (R4) ........................................................................... 74 Cortex General-Purpose Register 5 (R5) ........................................................................... 74 Cortex General-Purpose Register 6 (R6) ........................................................................... 74 Cortex General-Purpose Register 7 (R7) ........................................................................... 74 Cortex General-Purpose Register 8 (R8) ........................................................................... 74 Cortex General-Purpose Register 9 (R9) ........................................................................... 74 Cortex General-Purpose Register 10 (R10) ....................................................................... 74 Cortex General-Purpose Register 11 (R11) ........................................................................ 74 Cortex General-Purpose Register 12 (R12) ....................................................................... 74 Stack Pointer (SP) ........................................................................................................... 75 Link Register (LR) ............................................................................................................ 76 Program Counter (PC) ..................................................................................................... 77 Program Status Register (PSR) ........................................................................................ 78 Priority Mask Register (PRIMASK) .................................................................................... 82 Fault Mask Register (FAULTMASK) .................................................................................. 83 Base Priority Mask Register (BASEPRI) ............................................................................ 84 Control Register (CONTROL) ........................................................................................... 85 Floating-Point Status Control (FPSC) ................................................................................ 87 SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 135 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 137 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 138 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 139 Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 139 Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 139 Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 139 Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 140 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 141 Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 141 Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 141 Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 141 Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 142 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 143 Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 143 Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 143 Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 143 Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 144 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 145 Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 145 Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 145

Cortex-M4 Peripherals ................................................................................................................. 119


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Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69:

Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 145 Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 146 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 147 Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 147 Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 147 Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 147 Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 148 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 149 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 149 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 149 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 149 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 149 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 149 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 149 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 149 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 149 Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 149 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 149 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 149 Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 149 Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 149 Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 149 Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 149 Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 151 Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 151 Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 151 Interrupt 76-79 Priority (PRI19), offset 0x44C ......................................................

Stellaris LM4F120H5QR Microcontroller

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