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Steiner RoutingECE6133
Physical Design Automation of VLSI Systems
Prof. Sung Kyu LimSchool of Electrical and Computer Engineering
Georgia Institute of Technology
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Routingplacement
Generates a "loose" route for each net.
Assigns a list of routing regions to each net withoutspecifying the actual layout of wires.
global routing
compaction
Finds the actual geometric layout of each net withinthe assigned routing regions.
detailed routing
Global routing
Detailed routing
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Routing Constraints
100% routing completion + area minimization, under a set of constraints: Placement constraint: usually based on xed placement Number of routing layers Geometrical constraints: must satisfy design rules Timing constraints (performance-driven routing): must satisfy delay
constraints Crosstalk? Process variations?
Twolayer routing
ws
Geometrical constraint
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Graph Models for Global Routing: Grid Graph
Each cell is represented by a vertex.
Two vertices are joined by an edge if the corresponding cells are adjacentto each other.
The occupied cells are represented as lled circles, whereas the others
are as clear circles.
a b
c
d a b
c
d
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Graph Model: Channel Intersection Graph
Channels are represented as edges.
Channel intersections are represented as vertices.
Edge weight represents channel capacity.
Extended channel intersection graph: terminals are also represented asvertices.
channelintersectiongraph
extendedchannelintersectiongraph
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Global-Routing Problem
Given a netlist N= {N 1 , N 2 , . . . , N n }, a routing graph G = ( V, E ), nd aSteiner tree T i for each net N i , 1 i n , such that U ( e j ) c( e j ), e j E and ni=1 L ( T i ) is minimized,where
c( e j ): capacity of edge e j ;
x ij = 1 if e j is in T i ; x ij = 0 otherwise; U ( e j ) = ni=1 x ij : # of wires that pass through the channel corre-
sponding to edge e j ;
L ( T i ): total wirelength of Steiner tree T i .
For high-performance, the maximum wirelength (max ni=1 L ( T i )) is mini-mized (or the longest path between two points in T i is minimized).
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Classication of Global-Routing Algorithm
Sequential approach: Assigns priority to nets; routes one net at a timebased on its priority (net ordering?).
Concurrent approach: All nets are considered at the same time (com-plexity?)
globalrouting algorithm
sequential approach
twoterminal multiterminal
linesearch maze Steinertree based
Lee Hadlock Soukup
concurrent approach
hierarchical integer programming
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j
A l g o r i t h m s f o r V L S I P h y s i c a l D e s i g n A u t o m a t i o n
c S h e r w a n i 9 2
3 . 6
D a t a S t r u c t u r e s a n d B a s i c A l g o r i t h m s
S p a n n i n g T r e e
~
P r o b l e m F o r m u l a t i o n :
G i v e n a g r a p h G = ( V E ) , s e l e c t a s u b s e t V
0
V ,
s u c h t h a t V
0
h a s p r o p e r t y P .
~
M i n i m u m S p a n n i n g T r e e
~
P r o b l e m F o r m u l a t i o n :
G i v e n a n e d g e - w e i g h t e d g r a p h G = ( V E ) , s e l e c t a s u b s e t
o f e d g e s E
0
E s u c h t h a t E
0
i n d u c e s a t r e e a n d t h e
t o t a l c o s t o f e d g e s
P
e
i
2 E
0
w t ( e
i
) , i s m i n i m u m o v e r
a l l s u c h t r e e s , w h e r e w t ( e
i
) i s t h e c o s t o r w e i g h t o f
t h e e d g e e
i
.
{ U s e d i n r o u t i n g a p p l i c a t i o n s .
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j
A l g o r i t h m s f o r V L S I P h y s i c a l D e s i g n A u t o m a t i o n
c S h e r w a n i 9 2
3 . 1 3
D a t a S t r u c t u r e s a n d B a s i c A l g o r i t h m s
S t e i n e r T r e e s
~
1 . P r o b l e m f o r m u l a t i o n :
G i v e n a n e d g e w e i g h t e d g r a p h G = ( V E ) a n d a s u b s e t D V ,
s e l e c t a s u b s e t V
0
V , s u c h t h a t D V
0
a n d V
0
i n d u c e s a t r e e o f m i n i m u m c o s t o v e r a l l s u c h t r e e s .
T h e s e t D i s r e f e r r e d t o a s t h e s e t o f d e m a n d p o i n t s a n d
t h e s e t V
0
; D i s r e f e r r e d t o a s S t e i n e r p o i n t s .
U s e d i n t h e g l o b a l r o u t i n g o f m u l t i - t e r m i n a l n e t s .
Demand Point
B
CD
FJ
H
7
7
54
9
5 6
12
8
6 5 5
2 3
5
6
66
A
I
E
G
(a) (b)
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j
A l g o r i t h m s f o r V L S I P h y s i c a l D e s i g n A u t o m a t i o n
c S h e r w a n i 9 2
3 . 1 4
D a t a S t r u c t u r e s a n d B a s i c A l g o r i t h m s
U n d e r l y i n g G r i d G r a p h
~
T h e u n d e r l y i n g g r i d g r a p h i s d e n e d b y t h e i n t e r s e c t i o n s o f t h e
h o r i z o n t a l a n d v e r t i c a l l i n e s d r a w n t h r o u g h t h e d e m a n d p o i n t s .
Hanan's Thm (69'):There exists an optimal RST with all Steiner points (set S) chosen
from the intersection points of horizontal and vertical lines drawn from points of D.
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j
A l g o r i t h m s f o r V L S I P h y s i c a l D e s i g n A u t o m a t i o n
c S h e r w a n i 9 2
3 . 1 5
D a t a S t r u c t u r e s a n d B a s i c A l g o r i t h m s
D i e r e n t S t e i n e r t r e e s c o n s t r u c t e d f r o m a M S T
(a) (b)
(c) (d)
(e)
Hwang's Thm (76'):The ratio of the cost of a rectilinear MST to that of an optimal RST is no greater than 3/2.
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
The 1-Steiner ProblemDefinition
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
Why 1-Steiner Insertion?Can Reduce Wirelength
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
1-Steiner by Kahng/Robins
Iterative 1-Steiner Insertion AlgorithmKeep adding 1-Steiner point one-by-one until no more gain
Nave implementation: O(n 2 n log n n)Sophisticated implementation: O(n 3)
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
1-Steiner by Borah/Owens/Irwin
Interesting Observation
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
Gain Computation
Things to do
Thus, the gain is
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
Overall Algorithm
Multi-pass HeuristicEntire algorithm can be repeated
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Routing Practical Problems in VLSI Physical CAD 1-Steiner Algorithms
Comparison
Kahng/Robins vs Borah/Owens/IrwinKahng/Robins tends to give better results
Borah/Owens/Irwin runs much faster: O(n 4 log n) vs O(n 2)
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (1/17)
1-Steiner Routing by Kahng/RobinsPerform 1-Steiner Routing by Kahng/Robins
Need an initial MST: wirelength is 2016 locations for Steiner points
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (2/17)
First 1-Steiner Point InsertionThere are six 1-Steiner points
Two best solutions: we choose (c) randomly
beforeinsertion
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (3/17)
First 1-Steiner Point Insertion (cont)
beforeinsertion
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (4/17)
Second 1-Steiner Point InsertionNeed to break tie again
Note that (a) and (b) do not contain any more 1-Steiner point: sowe choose (c)
beforeinsertion
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (5/17)
Third 1-Steiner Point InsertionTree completed: all edges are rectilinearized
Overall wirelength reduction = 20 16 = 4
beforeinsertion
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (6/17)
1-Steiner Routing by Borah/Owens/IrwinPerform a single pass of Borah/Owens/Irwin
Initial MST has 5 edges with wirelength of 20Need to compute the max-gain (node, edge) pair for each edge inthis MST
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (7/17)
Best Pair for ( a,c )
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (8/17)
Best Pair for ( b,c )Three nodes can pair up with ( b,c )
l(a,c ) l( p,a ) = 4 2
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (9/17)
Best Pair for ( b,c ) (cont)All three pairs have the same gain
Break ties randomly
l(b,d ) l( p,d ) = 5 4
l(c,e ) l( p,e) = 4 3
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (10/17)
Best Pair for ( b,d )Two nodes can pair up with ( b,d )
both pairs have the same gain
l(b,c ) l( p,c) = 4 3
l(b,c ) l( p,e) = 4 3
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (11/17)
Best Pair for ( c,e )Three nodes can pair up with ( c,e )
l(b,c ) l( p,b) = 4 3
l(b,d ) l( p,d ) = 5 4
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (12/17)
Best Pair for ( c,e ) (cont)
l(e,f ) l( p,f ) = 3 2
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (13/17)
Best Pair for ( e,f )Can merge with c only
l(c,e ) l( p,c) = 4 3
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (14/17)
SummaryMax-gain pair table
Sort based on gain value
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (15/17)
First 1-Steiner Point InsertionChoose { b, (a,c )} (max-gain pair)
Mark e1 = (a,c ), e2 = (b,c )Skip { a , (b,c )}, { c, (b,d )}, { b, (c,e )} since their e1 / e2 are alreadymarkedWirelength reduces from 20 to 18
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (16/17)
Second 1-Steiner Point InsertionChoose { c, (e,f )} (last one remaining)
Wirelength reduces from 18 to 17
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Practical Problems in VLSI Physical Design 1-Steiner Algorithm (17/17)
ComparisonKahng/Robins vs Borah/Owens/Irwin
Khang/Robins has better wirelength (16 vs 17) but is slower
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Bounded Radius Routing
Why Radius?Longest source-sink path length among all sinks
Smaller path resistance: better performanceBoth Radius and Cost?
Cost = wirelength
Radius (= R) and wirelength (= C) are both important for RC-delay reduction
Bounded PRIM vs Bounded Radius/Cost J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, "Provably good performance-driven global routing", TCAD, 1992.
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Radius vs Wirelength
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Bounded PRIM Algorithm
Variation of PRIMs MST algorithm
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Bounded PRIM Algorithm
Comparison (e = 0, 0.5, infinity)Radius bound/value increase
Wirelength decreases
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Practical Problems in VLSI Physical Design Bounded Radius Routing (1/16)
Bounded Radius RoutingPerform bounded PRIM algorithm
Under = 0, = 0.5, and =
Compare radius and wirelengthRadius = 12 for this net
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Practical Problems in VLSI Physical Design Bounded Radius Routing (2/16)
BPRIM Under = 0Example
Edges connecting to nearest neighbors = ( c,d ) and ( c,e)We choose ( c,d ) based on lexicographical order
s-to- d path length along T = 12+5 > 12 (= radius bound)First appropriate edge found = ( s,d )
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Practical Problems in VLSI Physical Design Bounded Radius Routing (3/16)
BPRIM Under = 0 (cont)Radius bound = 12
edges connecting tonearest neighbors
s-to- y path lengthalong T
ties brokenlexicographically
should be 12;otherwise
appropriate used
first feasibleappr-edge
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Practical Problems in VLSI Physical Design Bounded Radius Routing (4/16)
BPRIM Under = 0 (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (5/16)
BPRIM Under = 0 (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (6/16)
BPRIM Under = 0.5Radius bound = 18
edges connecting tonearest neighbors
s-to- y path lengthalong T
ties brokenlexicographically
should be 18;otherwise
appropriate used
first feasibleappr-edge
should be 12
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Practical Problems in VLSI Physical Design Bounded Radius Routing (7/16)
BPRIM Under = 0.5 (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (8/16)
BPRIM Under = 0.5 (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (9/16)
BPRIM Under =
Radius bound = = regular PRIM
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Practical Problems in VLSI Physical Design Bounded Radius Routing (10/16)
BPRIM Under = (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (11/16)
ComparisonAs the bound increases (12 18 )
Radius value increases (12 17 22)Wirelength decreases (56 49 36)
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Bounded Radius Spanning Tree
Shallow Light Algorithm
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Bounded Radius Spanning Tree
Bounded-radius Spanning Tree Construction Augmentation of Q: added edges shown in dotted lines
Final BR-MST is SPT on Q
h C k ?
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Why BRBC Works?
Wh BRBC W k ?
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Routing Practical Problems in VLSI Physical CAD BRBC Algorithm
Why BRBC Works?
B d d R di B d d C t
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Practical Problems in VLSI Physical Design Bounded Radius Routing (12/16)
Bounded Radius Bounded CostPerform BRBC under = 0.5
defines both radius and wirelength boundPerform DFS on rooted-MST
Node ordering L = { s, a, b, c, e, f, e, g, e, c, d, h, d, c, b, a, s }We start with Q = MST
MST A g t ti
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Practical Problems in VLSI Physical Design Bounded Radius Routing (13/16)
MST AugmentationExample: visit a via ( s,a )
Running total of the length of visited edges, S = 5Rectilinear distance between source and a, dist ( s,a ) = 5We see that dist ( s,a ) = 0.5 5 < S Thus, we reset S and add ( s,a ) to Q (note ( s,a ) is already in Q)
MST Augmentation (cont)
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Practical Problems in VLSI Physical Design Bounded Radius Routing (14/16)
MST Augmentation (cont)
dotted edges are added
visit nodes based on L
Last Step: SPT Computation
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Practical Problems in VLSI Physical Design Bounded Radius Routing (15/16)
Last Step: SPT ComputationCompute rooted shortest path tree on augmented Q
BPRIM vs BRBC
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Practical Problems in VLSI Physical Design Bounded Radius Routing (16/16)
BPRIM vs BRBCUnder the same = 0.5
BPRIM: radius = 18, wirelength = 49BRBC: radius = 12, wirelength = 52
BRBC: significantly shorter radius at slight wirelength increase
A tree Algorithm
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Practical Problems in VLSI Physical Design
A-tree AlgorithmMinimum Shortest Path Steiner Arborescence (MSP-SA)
Given: edge-weighted undirected graph G(V , E ), sink set N (=subset of V ), and root node r
MSP-RA of N : Steiner tree T rooted at r that spans N Every source-sink path in T is shortest in GTotal wirelength is minimized
Minimum Rectilinear Steiner Arborescence (MRSA)Rectilinear version of MSP-SACan use Hanan or grid graph as underlying graph GBoth MSP-SA and MRSA are NP-hardMRSA vs BR-MRT: similarity and difference?
A-tree algorithm [Cong et al, 1993]: computes MRSA
Overview of A-tree Algorithm
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Practical Problems in VLSI Physical Design
Overview of A-tree AlgorithmOverall flow
Starts with initial forest F 0, where each sink becomes a rootGoal: make a sequence of moves
Move: either grow an existing tree or merge two treesContinue making moves until only one tree remains
Notation
F k : forest after k -th moveR(F k ): set of root nodes in F k
Types of moves
Safe (3 types): keep the forest wirelength-optimalHeuristic (2 types): use [Rao et at, 1992], non-WL-optimal
dx/dy/df Computation
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Practical Problems in VLSI Physical Design
dx/dy/df ComputationThree types of neighboring nodes of p in F x
NW ( p): set of nodes with their x-coordinate < x( p) and y-coordinate > y( p)
SE ( p): set of nodes with their x-coordinate > x( p) and y-coordinate < y( p)D( p , F k ): set of nodes with both x/ y-coordiates p. we call thesenodes are dominated by p
Node Blockage
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Practical Problems in VLSI Physical Design
Node BlockageTwo ways that q is blocked from p
If q is in NW ( p): draw vertical line from q to p until y( p)If q is in SE ( p): draw horizontal line from q to p until x( p)
Computing dx
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Practical Problems in VLSI Physical Design
Computing dx
Computing dy
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Practical Problems in VLSI Physical Design
Computing dy
Computing df
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Practical Problems in VLSI Physical Design
Computing df
Example
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Practical Problems in VLSI Physical Design
a p e
Safe Move Type 1
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Practical Problems in VLSI Physical Design
yp
Safe Move Type 2
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Practical Problems in VLSI Physical Design
yp
Safe Move Type 3
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Practical Problems in VLSI Physical Design
yp
Heuristic Moves
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Practical Problems in VLSI Physical Design
From [Rao et al, 1992]Used only when safe (= optimal) moves are not possible
Overall Algorithm
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Practical Problems in VLSI Physical Design
A-tree Routing Algorithm
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Practical Problems in VLSI Physical Design A-tree Algorithm (1/13)
Compute dx(c, F 0), dy(c, F 0), df (c, F 0)We begin with root set R(F 0) = { a,b,c,d,e,f } for initial forest F 0
Recall that
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Practical Problems in VLSI Physical Design A-tree Algorithm (2/13)
mx = a, dx = 3
my = d, dx = 2
Recall that (cont)
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Practical Problems in VLSI Physical Design A-tree Algorithm (3/13)
MF = { f, i } , df = 4 , mf w = i, mf s = f
Computing dx/dy/df for Node c
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Practical Problems in VLSI Physical Design A-tree Algorithm (4/13)
Computing dx/dy/df Values
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Practical Problems in VLSI Physical Design A-tree Algorithm (5/13)
Compute dx/dy/df for all other nodes
Safe Move Computation
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Practical Problems in VLSI Physical Design A-tree Algorithm (6/13)
What kind of safe moves does node a contain?We have dx(a , F 0) = , dy(a , F 0) = 1, df (a , F 0) = 5
Type 1: dx df and dy df
Type 2: dx df and dy < df Type 3: dx < df and dy df
So a has type-2 safe move
Safe Move Computation (cont)
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Practical Problems in VLSI Physical Design A-tree Algorithm (7/13)
Compute safe moves for all nodes in F 0Type 1: dx df and dy df Type 2: dx df and dy < df
Type 3: dx < df and dy df All moves are safe
No heuristic moves necessary
Recall that
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Practical Problems in VLSI Physical Design A-tree Algorithm (8/13)
Recall that (cont)
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Practical Problems in VLSI Physical Design A-tree Algorithm (9/13)
Safe Move for Node a
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Practical Problems in VLSI Physical Design A-tree Algorithm (10/13)
Perform safe move for node a (type 2)
Safe Move for Node a (cont)
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Practical Problems in VLSI Physical Design A-tree Algorithm (11/13)
Updating dx/dy/df values and safe moves
Performing Remaining Safe Moves
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Practical Problems in VLSI Physical Design A-tree Algorithm (12/13)
Choose the nodes in alphabetical order
Performing Remaining Moves
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Practical Problems in VLSI Physical Design A-tree Algorithm (13/13)
Final rectilinear Steiner arborescenceAll source-sink paths are shortestTotal wirelength = 18
3 Steiner nodes (white square) usedAll moves performed were safe