Status of the Beam Phase and Intensity Monitor for LHCb Richard Jacobsson Zbigniew Guzik Federico...
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Transcript of Status of the Beam Phase and Intensity Monitor for LHCb Richard Jacobsson Zbigniew Guzik Federico...
Status of the Beam Phase and Intensity Monitor for LHCb
Richard JacobssonZbigniew GuzikFederico Alessio
TFC Team:
Motivation Aims Overview of the board Debugging process Performance Future plans
05/06/07 45th LHCb Week 2
Why BPIM?
General clock issues:- Clock locked with the beam transmitted over 14
km of optical fibres at a depth of ~1 m- Estimated diurnal (200 ps) and seasonal drift (8
ns) due to temperature variations (AB/RF ref.)
Aid in the coarse and fine time alignment of the experiment
- Monitor individual bunch position- Measure bunch intensity bunch-by-bunch for
trigger conditions- Measure bunch phase bunch-by-bunch for long-
term stability in clock distributionAble to- See single bunch crossing: signal coming from BPTXs for LHCb, very fast and
high bipolar pulse.- Check trigger/detector timing alignment on the fly and tag events with bunch
information through the TFC system (Interfaced with ODIN)
AB/RF optical links
TTC equipment
05/06/07 45th LHCb Week 3
• Developing custom made acquisition board:– 6U VME, one per beam– Online analysis of a bipolar pulse: ±5Vmax amplitude,
FWHM 1 ns at 40 MHz– Measure time between bunch arrivals and LHC bunch
clock locally • Bunch-by-bunch for a full LHC turn filled in FIFO • Triggered via controls interface• <100 ps precision and averaging phase as a function
of bunch crossing– Measure continuously bunch intensities bunch-by-bunch
• 12-bit resolution by integrating pulse per bunch• Output intensity on front-panel at 40 MHz (8/4-bit
resolution)• Triggered via controls interface, fill in FIFO with
intensities for full turn• Intensity per bunch as a function of bunch crossing
– Readout via Experiment Control System, CCPC based interface
– Interfaced directly to LHCb Timing and Fast Control system
– Data processing on FPGA– Data and clock transmitted over LVPECL protocol
The 1° prototype few months ago
What do we aim to?
05/06/07 45th LHCb Week 4
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
MAIN FPGA
LVDSDrivers
BX InfoGP outputs
ADC
TDC
Integrator+
Rectifier(positive)
Rectifier(negative)
FPGA
AttenuatorAnalogbuffer
Beam
Threshold comparator
Zero-crossingcomparator
ThresholdDAC
FPGA
Delay
PECLF/F
Data
Clock
Delay
Reset
Dis
char
ge
Sample
Leveladapter
Bunchclock Programmable
delay
FPGA Clockfanout
DelayOne-shot
LVPECL/PECL
8:1 Divider
LVPECL/PECL
LVPECL/PECL
LVPECL/PECL
2:1 Divider
One-shot
Start
Stop
FIFOPhase
FIFOIntensity
Local Bus
VME interface (FPGA)
Drivers
Glue Card
Credit Card PC
VME Bus
EthernetOrbit Level
adapter
Overview of the board
Pspice simulations are available in lhcb-2006-055 by R.Jacobsson & Z.Guzik
http://doc.cern.ch//archive/electronic/cern/others/LHB/public/lhcb-2006-055.pdf
a lot of debugging
6 logical blocks:- Intensity measurement chain- Phase measurement chain- Clock distribution - Digital processing and data accumulation- I/O interfaces- Board control via ECS
05/06/07 45th LHCb Week 5
Debugging adventureThe first prototype has been mounted and debugged in stages: a lot of “bricolage” on it (thanks to the Electronic Workshop!) and understanding of the problems.
The 1° prototype one month ago
The analog chain is working: impressive performance!
Input pulse 3Vpp – FWHM 2ns through an inverter, buffer and rectifier stage. Current amplifier with slew rate as 10000 V/µs
05/06/07 45th LHCb Week 6
Debugging adventureAlmost all the digital parts have been mounted. FPGA programmed to configure and readout the TDC (Time-to-digital converter) and ADC.
Debugged and fixed Start and Stop signals for the TDC (resolution of 27ps, data stored in 2 FIFOs).
The 1° prototype now
05/06/07 45th LHCb Week 7
ConclusionsWhat is good?- All the chips mounted, tested and debugged- Analog chain mounted and most of the problems solved with amplifiers, buffers, clock delays and distributor. - CCPC mounted and booted. It’s possible to program and readout the FPGA via the LocalBus- Digital parts mounted. FPGA already programmed (brief and simple VHDL code just to test TDC and ADC)- Fast TDC and ADC working well. Fixed all the driving signals to the chip- The new prototype is being designed by Z.Guzik with all the bugs fixed
What will be modified? - The input attenuator doesn’t work. To be changed with a new design- The integrator is working; not as stable as we wish.- Replace the zero crossing method with a constant fraction at falling edge.- Translators from PECL to LVPECL chips. The whole board uses LVPECL protocol- No FIFO storage yet. TDC and ADC just read on the fly- More GP outputs to be added- A lot of testing to find out best response of the board
05/06/07 45th LHCb Week 8
Plans for the future
A second prototype is under development with the mentioned changes, it will be ready soon and then produced. Some new chips and some new layout for the PCB.
We are confident that already the second prototype will work as designed.
We will continue studying the first prototype…
… with a bipolar signal generator from LHC-BI group …
… and then will be tested in the SPS accelerator …
… a Graphic User Interface (in PVSS) will be developed to monitor the board.
CMS & ALICE are interested...! (Optional VME interface already on board)
Thank you for your attention.