Status of 8ch calib prototype N. Dumont-Dayot, G. Perrot, P. Perrodo, I Wingerter-Seez LAPP Annecy...

Status of 8ch calib prototype

N. Dumont-Dayot, G. Perrot, P. Perrodo, I Wingerter-Seez

LAPP Annecy

U. Schafer, D. Schroff,

Univ Mainz

C. de La Taille, N. Seguin-Moreau, L. Serin

LAL Orsay

ATLAS

21 jun 2002 C. de La Taille calibration board design review 2

8ch prototype status

Slice of 8 analog channels + complete digital part

3 boards received in apr 02 2 in Orsay (-> 1 to Mainz), 1 in Annecy

Opamps& switch

DAC

Calolgic

TTCRx

Delay

SPAC2

8 outputs


8channel prototype chips

DAC V2 Improved reference 123 chips received may 02 110 work OK QFP100

Opamp V2 offset trimmed to 15 µV HF switch integrated 463 chips available QFP44

Calogic V2 40 chips available in QFP100 Tested to SEE in Louvain


Digital part

Worked OK at once TTCRx + Calogic + Delay chip + SPAC3 Jitter visibly improved


DC uniformity

Correction of output line resistance t = 35 µm R = 0.5 mΩ/ � ΔL = 17 cm W = 200 µm Expect : ΔRline = 0.4 Ω

ΔVout = 0.8 % effect

Correction by ΔR (5Ω) decreasing Iout by increasing R(5Ω) Exact correction for W = 2mm : ΔR5 =40 mΩ Measured value = 60 mΩ -> overcompensation

Rout (Ω)

10*ΔR (5Ω)

CH0 CH7

VP6 layer

output layer


DC uniformity

DC current output 1.4% variation between CH0 and CH7 Consistent with +5.5V additionnal resistance

5 Ω resistors All in ± 0.1% Rms = 0.04% 2 resistors where low by 1% : DAMAGED ?


Lots of unexpected problems…

Board very different from mod0 Channels no longer aligned but staggered in depth

Lots of problems with the 8 channels Ground bounce 2V change with enabled channels 80 µV DAC offset DAC change with all channels on Overshoot Signal uniformity DC uniformity Damaged chips Oscillations Ripple noise Linearity


Example : Ground bounce

Observation 100 ns bounce on small signals Worst on far channels (->7) Clean on channel 0 Present even with collector open Dissapears if termination resistor (R0)

removed

Explanation Large digital current (200 mA) in

inductive ground Produces 1 mV ground bounce, coupled

to the output through R0

Cure Try to reduce digital current (difficult) Move R0 in quiet zone near inductor Minimize loop area around NE856


Parasitic injected charge (PIC)

L = 0, 22 nH, 100 nH

Parasitic signal when DAC=0 Proportionnal to CGS and ΔVGS

ringing with parasitic inductance (L ~ 3 nH) Reducing VG can reduce the PIC

• Effect very visible, scaling with VGS

• Below VG= - 0.4V, some PMOS are not completely OFF : not acceptable

Improved by connecting the nwell to the source

Referred to DAC value Peak of PIC after shaping 1 V DAC makes 5 V output pulse 1 GeV (η=0,MID) corresponds to DAC=500 µV



Parasitic injected charge extraction DAC set at \x0004 = 64 µV Signal due to offset needs to be substracted



Parasitic injected charge very uniform on 8 channels Equivalent to DAC=0006=100 µV (180 MeV in the barrel middle) in peak Subsequently reduced by a factor ~3, very close to noise level (50MeV) Well differentiated

Injected charge x 10

= 500 µV pulse~DAC=100µV


Linearity

Measured on each gain 1-10-100

Pulse measurements In red After shaping

DC current measur. In black With Keithley

Several problems DAC referenced to

VP6 Bad 5Ω resistor brand

Well below 0.1%


Linearity

Fit residuals show opamp offset Very small contribution of parasitic injected

charge

Offset of High gain range inagreement with low offsetOpamp measurementEffect too small to be seenin other ranges


Slope different by 5 % in high gain range due to attenuatoraccuracy

= 0.3 % but 5 V stripline compensation deteriorates the uniformity

Linearity

Fit slopes give uniformity Very small contribution of parasitic injected

charge


slope uniformity 0.3 %

1.5 % effect from 5.5 V compensation foreseen when 50 near switch0.6 % from different output lenghesfrom 50 to connector (on 128 boards connector position will adda few per mille5 resistor at 0.1 % as expected

What should we compensateon 128 boards ?

Pulse uniformity


Oscillations

Observation 1 Large oscillation at 350 MHz when channels 2,3 or 4 are pulsed together with

DAC>0.25V Barely visible oscillation at 350 MHz on all the channels, increasing with DAC>0.25V Was not present on single channel test-board

Explanation 1 None (as usual for HF oscillations)

Cure 1 Add 150 pF to ground on Cp (gate of current source output transistor)

Observation 2 180 MHz oscillation on large pulses, alters decay time

Explanation 2 Delay chip loaded by coax for triggering purposes

Cure 2 Add 50 Ω in series for trigger output


Damaged opamps

Observation + 2V moves up to 5.5 V Some chips (4/18) show large current (5-50mA) from 7.5V to +2V They still work correctly, but with degraded offset All chips in parallel on supplies, common 100 Ω protection resistor on +2 V Difficult to locate bad chips

Explanation None, could only be reproduced with 7.5V raised to 15V Several power supplies mishandlings have been tried without damage

Cure Individual current limitation resistors on +2V and +7.5V Series resistors on input and common voltage busses (Vref)


Damaged DAC

Observation 1 chip damaged on brd 3 DAC = 0 gives 2 mV 4 µA leakage current on MSB

Explanation None Chip could not be remounted on DAC test board (pins damaged)

Cure To be examined


Enable schematic

Common emitter between VDD and VSS

Channels enabled flow 1 mA in VSS

Channels ON by default (Enable=VDD)

Go to common base configuration Powered between VDD and GND

No current in VSS

Base connected to VCC through 47 kΩ

Channels OFF by default 50K

50K

VCC

100K

VDD

Enable2-7V

Calogic0-5V

VSS

100K

VDD

Enable2-7V

5K

Calogic0-5V


Robustness

Power supplies Effect of missing +7.5V : maximum current flowing (0.3A/ch) -> add 1MΩ to 5.5V on

output transistor Effect of missing +9.5V : maximum current flowing (0.3A/ch) -> Produce +7.5V from

+9.5V Effect of missing +5.5V : none. Effect of missing -6 V : barely visible, can be almost any (negative) value

Tests of robustness The chip starts to deteriorate at VDD = 12 V

Permanent damage in protection diodes, if unlimited current for VDD = 14 V

Offset variations Observation : offset changes by 40 µV when all channels are ON Explanation : Offset sensitivity to Vss power supply : dVoff/dV2V = 100 µV/V = 0.01%

Cure : • Reduce +2V impedance by decreasing resistance in series with the 3 diodes

• Maintain robustness by individual large resistive decoupling

• Use regulator on +7.5V


Summary of proposed modifications

General Power supplies reduced by 0.5V to VP6=+5V, VDD=+7V and VP9=+9V

Individual channels R0 = 50 Ω moved away from switch, close to inductor Output line impedance decreased to 25 Ω Bulk connected to source instead of VDD via 1 MΩ, 100 nF decoupling Gate connected to GND, no VG adjustment 150 pF to ground on Cp and 1 MΩ to VDD

1 kΩ in series with Vss = + 2 V (I = 100 µA) 200 Ω in series with fuses to Vss (I = 2 mA) 100 Ω in series with Vdd = +7V (I = 2.1 mA) Enable translator changed from common emitter to common base configuration, with

no connection to Vss Short path between emitter of switching NE856 and decoupling capacitor of preceding

emitter follower. Series resistor of follower increased from 51 Ω to 82 Ω (910 Ω was really too much !)


Summary of proposed modifications

Groups of 8 channels Remove 50 Ω parallel termination on command line Change 0 Ω series termination to 50 Ω // 33 pF Add fuse on VP6 if RFUSE < 50 mΩ

Have local +2V with 3 diodes Keep possibility of local VG = -0.4 V ?

DAC Correct star disribution for VP6 on resistor ladder Keep bandgap and reference possibility

DAC distribution 150 pF to ground on Cp and 1 MΩ to Vdd Connect drain to ground via 1 k instead of using PMOS switch 1 kΩ in series with Vss = + 2 V (I = 100 µA) 200 Ω in series with fuses to Vss (I = 2 mA) 100 Ω in series with Vdd = +7V (I = 2.1 mA)


Pending questions

Digital part Clock terminations Reset scheme

Regulator on +5V Maximum current : 3A =>

• All channels ON with DAC=100mV (1/10 full scale)

• 10 channels with maximum DAC

Filtering

Use of Bandgap reference Not yet tested

Schedule for opamps production Issue order in june ? How many wafers : 12, 13, 14 ?


Pulse shape before shaping

DAC=1V -40dB

DAC=0.1V -20dB

DAC=10mV 0dB

DAC=1mV 0dB

DAC=100µV

Full DAC range 100 µV-> 1V Up to 5V pulses in 50 Ω

Undershoot Due to 50 Ω line between

switch and R0 : should be 25 Ω

Checked by simulation Will be corrected

Risetime < 2 ns Varies little with DAC


Pulse shape after shaping

DAC=1V -80dB

DAC=1mV -20dB

DAC=100µV 0dB

DAC=0µV

80 dB dynamic range

Parasitic injected charge Equivalent to DAC=30 µV Or a pulse of 150 µV At peak < 15 µV Improvement by >10

compared to module0


PIC uniformity

PIC on 8 channels Good uniformity

Singularities : CH7 had the Nwell tied to

5V, as in the original configuration : clear improvement !

CH4 has a larger offset (35 µV) damaged ?

DAC=1mV -20dBCH7 : VB=+5V


Designing the 128ch board

Large number of modifications ! 108 modification on the 8 ch. Board alone Improved performance and robustness Power supplies decreased by 0.5V

Goal : have VP6 = 5V uniform for all channels within 0.1% Star configuration mandatory All VP6 lines equalized in length Common reference point on borad center :

dimension 2 x 1 cm = 1 mΩ Minimize variation of amplitude with

number of enabled channels

Many tricky PCB layout details 150 mm

220 mm

5Vref


Schematics : power supplies

Regulators on VP9 and VP7 from +11V. Also on VP5 ? Regulators on digital Vcc for delays and logic chips


Schematics : TTCRx

Derives 40 MHz clock and calib pulse (CMD) No EPROM used


Schematics : SPAC


Schematics : calogic

1 chip for counter, 1 for DAC and 4 for Enables


Schematics : delay chips

Delay chip : AC output as it can be stuck to Vcc Trigger output on front panel


Schematics

CMD distribution : White follower


Schematics : DAC

Careful separate layout of VP5 and GND

External reference to VP9

Internal low offset opamp connected as others


Schematics : DAC distribution

Low offset opamp for low impedance DAC fanout to 128 channels External fuses ?


Schematics : 1 pulser

Low offset opamp for current source HF switch with external NE856 New enable schematic


PCB layout

Top layer : analog components Bottom layer : digital components


PCB layout

Layer 2 Layer 3


PCB layout

Layer 4 Layer 5


PCB layout

Layer 6 Layer 7


PCB layout

PCB cross section : all inner copper layers 70 µm thickness

Layer 1

Layer 2

Output connector Analog part Digital part

GND routing routing

Layer 3

Layer 4

outputs

GND

Layer 5

Layer 6

outputs

GND

Layer 7

Layer 8

GND

Inductors

GND

GND

outputs

GND

outputs

GND

GND

GND

GND

enables

VP5

GND

VP5

routing

GND

GND

enables

VP5

VP5

VP5

routing

GND

VP5

outputs


Summary

The operation of the 8 channels board has been more difficult than foreseen Layout very different from module 0 Coupling of large digital signals Many modifications necessary Robustness had been overlooked

Performance is good Linearity < 0.1% Parasitic injected charge ten times better than on module 0

The 128 channel is being finalized Difficult layout of uniform VP6 : star configuration Many lines equalized in length

Pending issues Voltage regulator on VP5 (pin 4)

Status of 8ch calib prototype N. Dumont-Dayot, G. Perrot, P. Perrodo, I Wingerter-Seez LAPP Annecy...

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Transcript of Status of 8ch calib prototype N. Dumont-Dayot, G. Perrot, P. Perrodo, I Wingerter-Seez LAPP Annecy...