Statistical Critical Path Selection for Timing Validation Kai Yang, Kwang-Ting Cheng, and Li-C Wang...

Statistical Critical Path Statistical Critical Path Selection for Timing Selection for Timing

ValidationValidation

Kai Yang, Kwang-Ting Cheng, and Li-C Wang

Department of Electrical and Computer Engineering

University of California, Santa Barbara

OutlineOutlineo Abstracto Backgroundo Motivationo Universal Representative Path Seto Statistical Timing Simulatoro UR-Path Constructiono Experimental Resulto Conclusion and Future Works

AbstractAbstract

Statistical critical path selection for timing validation

o Path selection aims at tolerating inaccurate timing models

o Develop an efficient statistical timing simulator which can model both intra-die and inter-die process variation

o Analyze the timing validation quality using the generated patterns for the selected paths Previous researches utilize static path analysis

BackgroundBackgroundo Continuous shrinking of device feature size

increases the following timing effects: Process Variation Power Noise Crosstalk Random Defects Thermal Effects

o Modeling Issue Traditional discrete-value timing models are no

longer effective Statistical timing modeling make more sense in

deep sub-micron domain

Background – Timing Background – Timing ValidationValidation

o Verify the design with the timing constraintso Functional pattern v.s. structure-based

patterno Focus on the impact of process variations

No target on spot defects

o Structure-based pattern Critical path selection for timing validation Test pattern generation for selected path set

AA

BBCC

MotivationMotivation

o Traditional discrete-value modeling not able to efficiently capture deep sub-micron timing effects

o Even with a statistical methodology, an accurate timing model may not be available during the design phase

o Even with an accurate timing model, the number of selected critical paths for timing validation may be huge

Universal-Representative Universal-Representative Path Path

o Definition: Definition: Universal-Representative Path Set Universal-Representative Path Set

(UR)(UR)

If we make sure the delays of these paths are less If we make sure the delays of these paths are less than athan a

given clock period, then we can guarantee that the given clock period, then we can guarantee that the worst-worst-

case circuit timing is also less than the clock case circuit timing is also less than the clock period.period.

0),|_( clkpURpclkdelaycircuityprobabilit

Factor Analysis v.s. UR-PathFactor Analysis v.s. UR-Path

6 aspects in your questionnaire

reduced to 3 factors

regression

Y=function of (3 factors)

Y’=function of (6 variables)

regression

Factor Analysis Path Selection

Representativepaths

ATPG ATPG

StatisticalTiming Simulation

StatisticalTiming Simulation

Identify the underlying structure of data matrix

Statistical Timing Simulator - Statistical Timing Simulator - DSIMDSIM

o Objective: build a flexible, accurate, and efficient timing simulator Support flexible interface for incorporating different DSM timing

effectso Inter-Die Process Variationo Hierarchical Intra-Die Process Variation Modelingo Allow us to study the impact of process variations

o software released !o Download source code at

http://cadlab.ece.ucsb.edu

Statistical Timing SimulatorStatistical Timing Simulator

Delay Random Variables

Statistical DelayLibrary

LayoutInformation

Intra-Die Process VariationProfile

Statistical TimingSimulator -- DSIM

SimulationPatterns

CircuitNetlist

Sample 1 Sample 2 Sample K

…..Delay 1 Delay 2 Delay K

Experimental Result and Experimental Result and EfficiencyEfficiency

Circuit CPU Time(sec) Memoryc880 46.45 2.56M

c1355 116.2 2.86Mc1908 97.74 2.55Mc2670 161.54 4.39Mc3540 229.37 4.63Mc5315 432.58 6.91Mc6288 679.72 6.58Mc7552 761.02 8.77Ms9234 1210.05 13M

s13207 1969.77 21Ms15850 2515.29 23Ms35932 5350.5 45Ms38417 3599.41 37Ms38584 6714.64 53M

Statistical Simulation Efficiency – 100 samples and 1000 random patterns – P4 2GHz Linux workstation

Intra-Die Process VariationsIntra-Die Process Variations

o Process variation can be divided into two categories Inter-Die Variation Intra-Die Variation

o Inter-die variation is more likely to be random Modeled in the statistical delay library

Intra-die variation is spatially correlated which is hard to directly modeled into the delay library Proximately-close devices may have similar

behaviors

Hierarchical Intra-Die Process Hierarchical Intra-Die Process Variation ModelingVariation Modeling

o Originally developed by David Blaauw’s group on channel-length modeling

C30

C20

C10

Layout

Each region is associated with a variation parameter Cn Cn characterize the change in standard deviation

)1,0(

)***(

)***(

302010

302010

DisNormalN

CNCNCNDY

CNCNCNDX

y

x

03.0%3 302010

xstd

CCC

Proximity-closer devices have a stronger correlations in theirs delay

Example

Impact of Modeled Intra-Die Impact of Modeled Intra-Die Process VariationProcess Variation

o Layout Information – UCLA Capoo Without real process variation profile, randomly setup Cn

o For each region, the change of accumulative std in percentage is less or equal to 15%

o 3000 critical path delay test patterns with 6 different variation profiles

Summary of DSIMSummary of DSIMo Each circuit sample has a different but fixed delay

configurationo Given a set of patterns, the simulator performs timing

simulation on each circuit sampleo For a given clock and for each pattern, the simulator can

compute the probability of circuit delay exceeding the clock

o Consider the effect of intra-die process variations into timing simulation process

clk

Primary Output

UR-Path ConstructionUR-Path Construction

o Two-Phase algorithmo Path selection:

Select the superset of path (U-Path) from the whole path space which may affect the critical timing

Timing guard-band based selection method to tolerate inaccurate timing model

o Path refinement: Select the subset of path (UR-Path) from U-Path

which can represent the timing behavior of the whole U-Path set

Phase-1: Path SelectionPhase-1: Path Selection

AA

BB

CC

clk

Δc5315

c5315

0

5000

10000

15000

20000

333 332 331 330 329 328 327 326 325 324 323 321 320 319

clk-delta

Num

ber of

U-P

ath

333 clk- Δ 319

o Goal:Goal: timing guard-band based method to select the

set of path which may affect the critical

timing

o Construction of U-Path [iccad2002]Construction of U-Path [iccad2002] Given a clock Given a clock clkclk and the threshold value and the threshold value ΔΔ, , U-Path includes all U-Path includes all

paths with non-zero critical probabilities to exceed the specified paths with non-zero critical probabilities to exceed the specified value value clkclk- ΔΔ..

For a large For a large ΔΔ will produce a large number of paths which will make will produce a large number of paths which will make the path selection very inefficient. the path selection very inefficient. Path RefinementPath Refinement

c5315

Phase-2: Path RefinementPhase-2: Path Refinemento Goal:Goal: Select a small set of path which can Select a small set of path which can

represent the represent the timing behavior of U-Path timing behavior of U-Path

o Timing behavior:Timing behavior: the possibility to be longer than the possibility to be longer than

the the clkclk

Identify the path p has the largest critical probability

Remove those samples which p is longer than clk

For the remaining circuit samples, select the path with the largest critical probability, estimated based on all remaining samples

DSIM

circuitsample

circuitsample

circuitsample

circuitsample

Sample-based method [iccad2002]

Phase-2: Path RefinementPhase-2: Path RefinementAfter phase-1, we get a set of UR-path but due to the inaccurate timing model, we need to enlarge the path

set Correlation based heuristic – statistical factor analysis

Select the paths which are more independent Paths with high correlation tend to have similar timing

behavior

UR-path setRemaining paths sorted with mean delay

Pick one path p’ can calculate the correlation coefficient with each path in UR-set

If the correlation is less than the given threshold value, include p’ into UR-path set

Experimental SetupExperimental Setup

o Incorporate the statistical simulator to calculate the failing sample rate as the evaluation metric

o Perform the proposed path selection with inter-die process variation only Modeled directly in the statistical delay library

o Evaluate the quality of the resulting pattern of the circuit samples with both intra-die and inter-die process variations To demonstrate the proposed method can

tolerate the inaccurate timing model

Metric: Failing Sample RateMetric: Failing Sample Rate

Circuit Instance with both Inter-die and Intra-die variations

Test set TCause delay

Exceeding clock?

Not-Detected

no

Detected

Statistical Timing Simulator

yes

Failing SampleRate Detected + Not-Detected

=Detected

Experimental ResultExperimental Resulto Construct UR-Path set with different correlation coefficiento Compare with other path selection strategieso The number of selected critical path converge quickly

compare to the traditional selection methodology

Ind32opt

Experimental ResultsExperimental Results

c2670opt

Conclusions and Future WorkConclusions and Future Work

o Propose a sample-based strategy to select statistical critical paths for timing validation. Experiment shows that the number of selected path converge quickly.

o For some circuits, the proposed sampled-based method is much more efficiency than the traditional critical path selection.

o Develop an efficient statistical timing simulator which can simulate both intra-die and inter-die delay.

Conclusion

Future Work

Theoretically analyze the path selection problem for timing validation

Incorporate real process variation profiles to evaluate the proposed methodology

Statistical Critical Path Selection for Timing Validation Kai Yang, Kwang-Ting Cheng, and Li-C Wang...

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