STATCOM Project - Submission Draft

Dublin Institute of Technology

School of Electrical and Electronic Engineering

Bachelor of Engineering Technology:

Electrical and Control Engineering (DT009)

Final Year Project

Student Name: Emmet Clarke

Project Title: Development of a Distribution Static Synchronous

Compensator for Power System Voltage Regulation

ii

Declaration

I the undersigned declare, that this report is entirely my own written work, except where

otherwise accredited, and has not been submitted for academic assessment to any other

university or institution.

Name: Emmet Clarke.

Signature:_________________________ Date:______________________

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Acknowledgements

Firstly I would just like to take this opportunity to thank my project supervisors Mr. Michael

Farrell and Dr. Ted Burke for their guidance and support throughout the duration of this

project. I would also like to extend my thanks to the members of staff of the school of

electrical and electronic engineering who willingly assisted me in any way they could.

Finally, I would like to thank my family and girlfriend, Suzanne for their continued support

and encouragement over the last few months.

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Abstract

Flexibility and controllability of transmission systems have become major issues in recent

decades. This can be attributed to many factors including; larger transmission grids, more

interconnection and larger power transfer across these grids. These issues are manifested in

power quality problems such as; transient and steady state stability issues, voltage regulation

problems, poor power factor, increased levels of harmonics, poor transmission line capacity

and high loss levels on long transmission lines. Of these issues, voltage regulation remains a

concern due to the potential for causing total system blackout. The ability to rapidly, reliably

and efficiently control the voltage at any point in the system offers far reaching benefits to

transmission system operators. These include; more reliable transmission grids, increased

levels of power transfer and increased line efficiency.

The main aim of this project will be to develop a static synchronous compensator for the

purpose of voltage regulation at distribution level. This will be accomplished through the

design of a compensator which is capable of maintaining the voltage magnitude at a pre-

determined level at the receiving end of a line by reactive power compensation of the line and

load. MATLAB/Simulink will be the software used to facilitate the design of the

compensator and also to conduct simulation studies on a sample system. Its successful

operation will be proven by a series of tests and these results will be validated by

mathematical analysis. The compensator will be based on a single phase full bridge voltage

source converter employing IGBTs. A unipolar sinusoidal pulse width modulation switching

scheme will be used and the control method employed will be the constant DC link voltage

method encompassing two PI controllers. Having completed system testing, it will be shown

that the compensator was capable of maintaining a voltage magnitude of 10 KV at the

receiving end despite a fluctuating load and a varying sending end voltage.

An optional objective which will be carried out if time constraints permit will be the

hardware implementation of a scaled down version of the simulated system. The aim of this

will be to further validate the findings of the simulation.

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Table of Contents

Declaration ................................................................................................................................. ii

Acknowledgements .................................................................................................................. iii

Abstract ..................................................................................................................................... iv

List of Figures ........................................................................................................................ viii

List of Tables ............................................................................................................................. x

List of Abbreviations ................................................................................................................ xi

1. Introduction ........................................................................................................................ 1

1.1 General Introduction ................................................................................................... 1

1.2 Flexible AC Transmission System .............................................................................. 2

1.3 Project Objectives ....................................................................................................... 2

2. Literature Review............................................................................................................... 3

2.1 STATCOM Fundamentals .......................................................................................... 3

2.2 Published Material....................................................................................................... 6

2.3 The STATCOM as a Shunt Connected Compensator ............................................... 10

3. Sample System and Test Results ..................................................................................... 16

3.1 Test System ............................................................................................................... 16

3.2 Test Results Analysis ................................................................................................ 19

4. D-STATCOM Design Considerations ............................................................................. 22

4.1 Criteria Which Influences D-STATCOM Performance............................................ 22

4.2 Switching Scheme ..................................................................................................... 23

4.2.1 Pulse Width Modulation ......................................................................................... 23

4.2.2 Hysteresis Current Control ..................................................................................... 23

4.2.3 Selective Harmonic Elimination Modulation ......................................................... 24

4.3 Control Strategy ........................................................................................................ 24

4.4 Output Filter .............................................................................................................. 24

vi

4.5 DC Link Capacitor .................................................................................................... 25

5. D-STATCOM Design Procedure ..................................................................................... 27

5.1 PWM Analysis .......................................................................................................... 27

5.2 Controller Design ...................................................................................................... 29

5.2.1 Active Power Absorption Loop .............................................................................. 30

5.2.2 Reactive Power Compensation Loop ...................................................................... 31

5.3 PI Controller Tuning ................................................................................................. 31

5.4 Filter Design .............................................................................................................. 32

5.5 DC Link Capacitor Selection .................................................................................... 37

6. Compensated Test System, Results and Analysis............................................................ 39

6.1 System Test Results .................................................................................................. 39

6.2 System Parameter Step Test Protocol ....................................................................... 41

6.2.1 Test Results Analysis .............................................................................................. 42

6.2.2 Capacitive Mode ..................................................................................................... 43

6.2.3 Inductive mode........................................................................................................ 44

7. Hardware Implementation of Test System ...................................................................... 46

7.1 Sample System for Hardware Implementation ......................................................... 46

7.2 Hardware System Testing ......................................................................................... 47

8. Conclusion ....................................................................................................................... 48

8.1 Discussion ................................................................................................................. 48

9. References ........................................................................................................................ 52

10. Appendices .................................................................................................................... 55

10.1 Appendix A - Calculations .................................................................................... 55

10.1.1 Calculations for Section 3.2 .................................................................................. 55

10.1.2 Calculations for Section 5.4 .................................................................................. 56

10.1.3 Calculations for section 6.2 ................................................................................... 57

10.1.4 Calculations for Section 6.2.2 and Section 6.2.3 .................................................. 57

vii

10.2 Appendix B - Controller Synchronisation ............................................................. 58

10.3 Appendix C - Further Results from Section 6.2 .................................................... 60

10.4 Appendix D - Full Model of Test System ............................................................. 62

10.5 Appendix E – Hardware Control Algorithm ......................................................... 63

10.6 Appendix F – Program Executed on dsPIC ........................................................... 64

viii

List of Figures

Figure 1: Basic STATCOM structure ........................................................................................ 4

Figure 2: V – I characteristic comparison .................................................................................. 4

Figure 3: Uncompensated distribution line .............................................................................. 11

Figure 4: Distribution line with shunt compensation ............................................................... 11

Figure 5: Transmission angle curve ......................................................................................... 13

Figure 6: Capacitive and inductive mode - phasor diagram .................................................... 15

Figure 7: Uncompensated test system...................................................................................... 17

Figure 8: Uncompensated test system - load voltage ............................................................... 18

Figure 9: Uncompensated test system - load power ................................................................ 18

Figure 10: Distribution line equivalent circuit ......................................................................... 19

Figure 11: Uncompensated test system - phasor diagram ....................................................... 20

Figure 12: Test system compensator........................................................................................ 21

Figure 13: Single phase VSC ................................................................................................... 22

Figure 14: Bipolar switching scheme ...................................................................................... 28

Figure 15: Bipolar switching scheme - frequency spectrum ................................................... 28

Figure 16: Unipolar switching scheme and frequency spectrum ............................................. 29

Figure 17: Controller block diagram........................................................................................ 30

Figure 18: Open loop system step response ............................................................................. 32

Figure 19: VSTATCOM - Fourier analysis results ........................................................................ 33

Figure 20: ISTATCOM - Fourier analysis results ......................................................................... 33

Figure 21: Low–pass LC filter with passive damping ............................................................. 34

Figure 22: Frequency response of G(s) with different values of resistance ............................ 35

Figure 23: Low – pass LC filter ............................................................................................... 35

Figure 24: LC filter frequency response .................................................................................. 35

Figure 25: Filter output voltage harmonics .............................................................................. 36

Figure 26: Filter output current harmonics .............................................................................. 36

Figure 27: DC voltage ripple with 500 μF capacitor ............................................................... 37

Figure 28: DC voltage ripple with 800 μF capacitor ............................................................... 37

Figure 29: DC voltage ripple with 1500 μF capacitor ............................................................. 38

Figure 30: Compensated test system........................................................................................ 39

ix

Figure 31: Compensated test system - load voltage................................................................. 40

Figure 32: Compensated test system - load power .................................................................. 41

Figure 33: Comparison of VLOAD with and without compensation ......................................... 43

Figure 34: Compensator output power .................................................................................... 44

Figure 35: Power injected by filter capacitor ........................................................................... 44

Figure 36: Power absorbed by the compensator ...................................................................... 45

Figure 37: Compensator output power .................................................................................... 45

Figure 38: Hardware test circuit .............................................................................................. 46

Figure 39: D-STATCOM output power - without synchronisation ......................................... 59

Figure 40: D-STATCOM output power - with synchronisation .............................................. 59

Figure 41: Comparison of VLOAD with and without synchronisation ...................................... 59

Figure 42: Power drawn from supply ...................................................................................... 60

Figure 43: VLOAD Fourier analysis ........................................................................................... 60

Figure 44: ILOAD Fourier analysis ............................................................................................. 61

x

List of Tables

Table 1: Distribution line impedance parameters .................................................................... 17

Table 2: Distribution line ABCD parameters .......................................................................... 19

Table 3: Test results analysis - measured results vs. calculated results ................................... 20

Table 4: D-STATCOM ratings ................................................................................................ 21

Table 5: PI controller gain values ............................................................................................ 32

Table 6: System test procedure ................................................................................................ 42

Table 7: Hardware system test results ..................................................................................... 47

Table 8: Filter calculations....................................................................................................... 57

xi

List of Abbreviations

CB - Circuit breaker

CSC - Current source converter

DSO - Distribution system operator

D-STATCOM - Distribution static synchronous compensator

FACTS - Flexible AC transmission system

FFS - Fundamental frequency switching

GTO - Gate turn off thyristor

HCC - Hysteresis current control

IGBT - Insulated gate bipolar transistor

IGCT - Integrated gate commutated thyristor

KP - Proportional gain

MA - Modulation index

OLTC - On load tap changer

PCC - Point of common coupling

PI - Proportional and integral

PLL - Phase locked loop

PWM - Pulse width modulation

SHEM - Selective harmonic elimination modulation

SPWM - Sinusoidal pulse width modulation

STATCOM - Static synchronous compensator

SVC - Static VAR compensator

xii

TCR - Thyristor controlled reactor

THD - Total harmonic distortion

Ti - Integral action time

TSC - Thyristor switched capacitor

TSO - Transmission system operator

UPFC - Unified power flow controller

VSC - Voltage source converter

VSI - Voltage source inverter

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1. Introduction

1

1.1 General Introduction

In recent times the increased load demand on power systems has led to widespread problems

on the transmission grids of many countries. As society’s progress and load demand

continues to rise and becomes more variable and non-linear in its nature, these problems are

likely to grow in both scale and severity [1]. Power system operators have tried to combat

this, in most cases the solution has led to; an increase in transmission grid size,

interconnection and power transfer. This has been shown to give rise to problems in relation

to controllability and flexibility of the grid [2]. A large number of developing and indeed

developed nations have experienced power quality issues due to the nature and design of the

traditional transmission grid. These problems include; transient and steady state stability

issues, voltage regulation problems (sags, swells and flicker), poor power factor, increased

levels of harmonics, poor transmission line capacity and high loss levels on long transmission

lines.

If left unchecked these problems can have far reaching consequences not only for the

transmission system but also for large numbers of industrial, commercial and domestic

customers. One approach formerly used to solve the problem was to construct more

transmission lines. However, this option is unfavourable due to the social and political

difficulties posed by such a strategy. In recent times utilities have found it extremely difficult

to obtain the relevant permissions and licenses required to construct new lines [2]. Therefore

it is imperative that the use of existing lines is maximised. One of the methods currently

being used to mitigate these issues is reactive power compensation [3]. The impedance of

transmission lines together with the requirement for reactive power by most machines in a

generating system, coupled with the inductive nature of most industrial loads results in a

requirement for reactive power. If the transmission system can be relieved from the burden of

producing and carrying some of this reactive power, some of the issues previously mentioned

can be alleviated and thus better system controllability can be attained. This can be achieved

Introduction

2

by dynamically controlling one or more of the following parameters; sending end voltage,

power transmission angle (δ) or load impedance. The effective realisation of such control can

be achieved by use of flexible AC transmission system (FACTS) controllers.

1.2 Flexible AC Transmission System

The application of power electronics in the electric power transmission industry has led to

increased reliability, controllability and efficiency [3]. The most popular solution to the

previously mentioned problems is an approach known as FACTS. FACTS devices utilise

power electronics and have proven themselves to be very effective in increasing power

system reliability and maintaining power quality while increasing transmission capacity and

efficiency [3]. Since the concept was first introduced in the 1970’s and further developed in

the 1980’s FACTS has now become the technology of choice for power flow control (active

& reactive), voltage control, harmonic reduction and dynamic stability improvement [4].

FACTS controllers can be split into two main categories; shunt connected devices and series

connected devices. The shunt connected variety can be further split into impedance type

devices (SVC) and converter based devices (STATCOM). With an increasing surge of

interest in converter based devices, the STATCOM will ultimately be the primary focus of

this project.

1.3 Project Objectives

The aim of this project is to design and implement a single phase distribution level static

synchronous compensator (D-STATCOM) for the purpose of voltage regulation on a given

test system using the MATLAB/Simulink software package. The compensators success will

be judged by its ability to maintain the voltage at 10 KV at the receiving end, while also

managing to maintain both voltage and current total harmonic distortion (THD) of the output

at acceptable levels despite a varying load and fluctuating system voltage. In order to confirm

the correct operation of the D-STATCOM a series of tests will be performed upon a test

system before and after the implementation of the compensator. The comparison of

measurements and mathematical analysis will be employed to validate the successful

operation of the D-STATCOM. In order to design a suitable compensator a brief assessment

of different control strategies, switching techniques, filtering options, converter types and

solid state switches will also be included.

An additional objective will be to construct a scaled down hardware model of the simulated

test system. The purpose of this will be to further confirm the findings of the simulation.

3

2. Literature Review

2

2.1 STATCOM Fundamentals

One of the most popular and promising members of the FACTS device family is the static

synchronous compensator (STATCOM). The STATCOM is a shunt connected device which

has the ability to either absorb or inject reactive power at the point of common coupling

(PCC) to the grid. The main purpose of the STATCOM is to generate a voltage/current at the

fundamental frequency whose magnitude and phase angle are controllable. This is generated

from an inverter supplied by a DC source, usually a charged capacitor. A diagram of the basic

STATCOM structure and grid connection is shown in Figure 1. The output of the STATCOM

is typically coupled to the grid through a transformer, however for the purpose of this project,

the STATCOM output will be coupled to the grid through an inductance which will be used

to model the transformers leakage reactance. The capacitive or inductive output current of the

STATCOM can be controlled independently of the AC line voltage. The STATCOM can be

based around the voltage source converter (VSC) also known as voltage source inverter (VSI)

or the current source converter (CSC). It has extremely fast response times when compared to

1st generation FACTS devices such as the static VAR compensator (SVC) [16]. Some other

reasons for its popularity reside in the fact that its physical size is smaller than that of an SVC

for a comparable level of compensation. It has wider operating parameters and an increased

number of applications within the transmission grid and the distribution network. By

comparison the STATCOM is more expensive than the traditional SVC and so it is advised

that end user requirements are extensively explored prior to selection of a compensation

device [17]. Although the STATCOM is more expensive than the SVC it has been reported in

[6] that its implementation can lead to savings on other power system devices such as load

dependant tap changers. The STATCOMs popularity has largely been driven by research

conducted in the field of power electronics and in particular self-commutated devices such as

insulated gate bipolar transistors (IGBT), integrated gate commutated thyristors (IGCT) and

gate turn – off thyristors (GTO) [4]. The utilisation of these devices means that a STATCOM

does not require banks of capacitors and reactors, such as those used to form an SVC. This

Literature Review

4

leads to a saving in physical space but the main advantage is made clear by the comparison of

the V – I characteristics of both the STATCOM and SVC in Figure 2.

Figure 1: Basic STATCOM structure

Figure 2: V – I characteristic comparison

As can be seen in Figure 2, the reactive power output of the SVC is directly related to the

system voltage therefore any reduction in this voltage has an impact on the reactive power

compensation capability of the SVC. Crucially, it is as the system voltage sags that the

compensator is required to operate, meaning the SVCs compensation ability is compromised

by the very disturbance it is there to alleviate. Figure 2 also shows that the STATCOM does

not suffer from this drawback. The reason for this is that the reactive power compensation

capability of the STATCOM is completely independent of the system voltage. This is a good

Literature Review

5

illustration of the fundamental difference between the two devices. Which is that, the SVC is

essentially a controllable impedance/admittance and therefore its capabilities are reliant on

the system voltage to a certain extent, while the STATCOM can be considered as a

completely independent synchronous voltage source.

The prevailing trend in industry is towards FACTS devices employing IGBTs and even more

recently IGCTs [7]. However in the early days of FACTS devices based on the voltage source

converter, the STATCOM was restricted to high voltage applications with a fundamental

frequency switching (FFS) control method. This was due to the power electronics being used;

GTOs were the preferred choice because of their high voltage and current ratings (typically 6

KV and 6 KA) however they have high loss levels if they are switched any more than once

every cycle [6]. Nowadays with the higher power capabilities of the IGBT and IGCT, which

have lower loss levels even when switched at high frequencies in switching schemes such as

PWM, the STATCOM has become more accessible to a wide variety of applications.

Utilisation of the technology at distribution level being one of them.

Equation (1), sourced from [7], forms the basis for the apparent power transfer of the D-

STATCOM. From it, equation (2) and equation (3) can be derived. The sign preceding the

imaginary part of equation (1) depends on the mode of operation of the compensator. A

negative sign indicates inductive mode (absorbing reactive power) while a positive sign

signifies capacitive mode (injecting reactive power). If it is assumed that the angle α is

maintained at a constant value for a given load it can be shown that equation (3) demonstrates

how independent control of the STATCOM output voltage (VCOMP) controls the reactive

power compensation. The active power absorption by the STATCOM is described by

equation (2). From equation (2), it can be stated that in order to minimise real power

absorption from the grid, the angle α should be maintained as small as possible, although it

cannot be made 0° as some real power must be absorbed. The reason for this will be

explained in the following chapters.

𝑺 = 𝑽𝒈𝒓𝒊𝒅 × 𝑽𝒄𝒐𝒎𝒑

𝑿𝒍𝐬𝐢𝐧 𝜶 + 𝒋 (

𝑽𝒈𝒓𝒊𝒅 × 𝑽𝒄𝒐𝒎𝒑

𝑿𝒍𝐜𝐨𝐬 𝜶 −

𝑽𝒈𝒓𝒊𝒅𝟐

𝑿𝒍) (1)

Where: Xl = Coupling inductance.

α = Phase angle between VGRID and VCOMP.

Literature Review

6

𝑷 = 𝑽𝒈𝒓𝒊𝒅 × 𝑽𝒄𝒐𝒎𝒑

𝑿𝒍𝐬𝐢𝐧 𝜶 (2)

𝑸 = 𝑽𝒈𝒓𝒊𝒅

𝑿𝒍 (𝑽𝒄𝒐𝒎𝒑 − 𝑽𝒈𝒓𝒊𝒅)𝒄𝒐𝒔𝜶 (3)

2.2 Published Material

The concept of using power electronics as a means of increasing flexibility and control in an

AC power system is introduced in [4]. The idea of FACTS was introduced following a

number of significant research developments in relation to the thyristor. The primary concept

of the thyristor has since been developed and refined; and together with other solid state

devices, they are collectively revolutionising how the AC power system is managed. [4] is

purely an introduction to the subject matter and hence no actual FACTS devices are

discussed.

[5] presents a comprehensive overview of the fundamental theory behind reactive power

compensation. A wide range of FACTS controllers are thoroughly explored, ranging from 1st

generation devices such as thyristor controlled reactors (TCR) and thyristor switched

capacitors (TSC), collectively known as the SVC, to more recent developments such as the

STATCOM and unified power flow controller (UPFC). While there is no system design or

implementation, the author simply offers a theoretical knowledge of the subject and as such

the methodology used to explain the various FACTS controllers is the derivation of the

fundamental equations governing the behaviour of each device.

Through mathematical analysis, the credentials of the STATCOM as an effective means for

compensating reactive power are established. Through the derivation of equations and

solving of various calculations, the fundamental difference between the SVC and STATCOM

is explored. It is clearly demonstrated that the SVC is essentially a controlled reactive

admittance and the STATCOM functions as a controlled synchronous voltage source. The

benefit of this difference is confirmed by the comparison of V – I characteristics for both

devices. By solving the relevant system equations it is verified that the output of the SVC

decreases linearly with system voltage while the STATCOM output is proven to be

independent of system voltage. This allows the STATCOM to offer a wider and more reliable

degree of control. In contrast to [5]; [6] presents a test system and through simulation and the

generation of relevant data, the theory stated was proven to be correct. By measuring the grid

voltage, reactive power output and output harmonic spectrum, the credentials of the

STATCOM as a means of reactive power compensation is firmly established. The author

Literature Review

7

demonstrates the ability of the STATCOM to maintain load bus voltage at 1 p.u. despite the

introduction of various disturbances such as step changes in load.

In [7] a synopsis of the underlying principles of this technology is given which includes the

research potential and future trends in this field. Some possibilities are the development of

high power ratings STATCOMs using IGCT based VSCs employing a pulse width

modulation (PWM) mode of operation, improvement of controller function to enable control

of system dynamics during both symmetrical and asymmetrical faults and in co-ordination of

systems employing multiple FACTS controllers in various locations. The operating principles

of the STATCOM are described together with a brief look at different solid state devices

commonly employed for switching. The author offers an insight into why the GTO is still the

preferred solid state switch for high power applications despite its relative old age. By

comparing and contrasting relevant research papers the author deduces that the conduction

and switching losses experienced by other solid state switches make the GTO using

fundamental frequency switching (FFS) the preferred option. However it is also noted that

low to medium power applications of the STATCOM have shifted towards the IGBT and

IGCT due to technical developments resulting in low losses and the flexibility offered in

control method selection. A range of different STATCOM topologies are explored along with

various control strategies. This research article purely provides a basic overview of the

technology and as such no mathematical derivation or system implementation is presented.

When considered in unison with [6] a strong appreciation for the core principles of this

technology is formed. Although two distinct methodologies are used by [6] and [5] they are

both in agreement that the STATCOM based on the VSC is a viable means of reactive power

compensation for future power systems at both transmission and distribution level.

In [8] a basic introduction of the single phase VSC which the STATCOM is based upon can

be found. The author explores two different methods of switching for the VSC which are;

square wave mode and PWM mode. By comparing the harmonic spectrum of the output for

each switching method it is shown that a PWM switching technique offers advantages over

square wave mode such as; low order harmonic attenuation and it also pushes higher order

harmonics further up the frequency spectrum making them easier to filter. This data is further

confirmed in [9] however both authors use only mathematical derivation and examples as a

methodology, implementation and testing of a VSC is excluded by both. [10] provides a

comprehensive description of the STATCOM employed as a FACTS controller in a sample

system when using both a square wave mode of operation and PWM mode. Simulations are

Literature Review

8

carried out and by comparing an uncompensated system to a compensated system with

particular attention being given to load bus voltage magnitude and response times for each

control method. The data generated confirms that both systems offer similar control with

regards to maintaining the voltage magnitude. However the PWM control method is capable

of achieving this much faster with the added harmonic benefits already stated.

[11] presents the basic VSC topology where the constant DC link voltage control strategy is

employed. A generic control algorithm is given and the STATCOM is tested on a sample

system. The system used is a three machine, nine bus system with the STATCOM connected

to one of the buses. Each bus has different loads switching in and out and prior to the

introduction of the STATCOM the voltage at selected buses drops to, between 0.94 p.u. and

0.87 p.u. However after the introduction of the STATCOM the voltage on each bus is shown

to remain at 1 p.u.

The merits of the constant DC link voltage scheme can be further observed if the results

obtained by [11] are compared to the results generated by [28]. In [28] the phase angle

control method is employed and tested in a similar manner. The average response time of the

compensator was found to be approximately 450 ms however in the results generated by [11]

the average response time was found to be in the region of 150 ms. Therefore it can be

concluded that the DC link voltage control scheme offers significant benefits in terms of

response speed.

In [12] the importance of choosing the correct control scheme for a chosen application is

emphasised by comparison of control schemes employed on the same system. The choice of

control scheme is shown to be a key factor influencing the performance of the STATCOM.

An extensive range of tests are undertaken and the resulting pros and cons of the selected

control techniques are summarised under the following categories; harmonic distortion, speed

of operation, transient performance and control strategy complication. The focal point of this

particular research is the comparison of the PWM technique and the hysteresis current control

(HCC) technique. Mathematical derivations of the relevant transfer functions are used to

present the qualities of each, however simulation and field tests are carried out and the results

confirm the superiority of the PWM technique over HCC. On average the HCC controller

response time was found to be 66 ms faster than the PWM controller. However the switching

frequency in a PWM system remains constant while in a HCC system it continually

fluctuates, thus making control system design more difficult. In a PWM system the

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9

harmonics are centred around the sidebands of the switching frequency making them easier to

filter however in the HCC system they were found to be distributed from 1 KHz to 3 KHz for

an average switching frequency of 1 KHz.

Due to the aforementioned advances in power electronics the STATCOM is no longer

restricted to high power applications. Nowadays the STATCOM is increasingly being

employed in the distribution network, and in this application it is known as the D-

STATCOM. [13] presents a comprehensive study of the design and implementation of a D-

STATCOM. The operating principles of the D-STATCOM are similar to that of the

STATCOM however a D-STATCOM offers more flexibility in relation to the selection of

solid state switch, control strategy and switching scheme. The D-STACOM is implemented

in a test system and the test results mirror those achieved for earlier versions of the

STATCOM. In this case the author explores an alternative control technique known as

selective harmonic elimination modulation (SHEM). The SHEM technique is shown to

eliminate selected harmonics at a switching frequency approximately 50% lower than the

equivalent PWM technique, thus reducing switching losses. A combination of both

mathematical analysis and simulation results are used to confirm the theory.

Further D–STATCOM design and simulation studies can be found in [26] and [27], however

only simulated test results are provided and the mathematical analysis presented is quite

vague in detail. Yet [26] and [27] do however serve to prove the robustness of the D-

STATCOM under a range of different abnormal voltage conditions such as sags and swells.

The D-STATCOM was capable of maintaining the bus voltage at 1 p.u. despite being

exposed to a range of disturbances such as; load increases, load decreases and transient faults.

Another critical factor which significantly influences the overall performance of the

STATCOM is the correct design of the DC link capacitor. In [28] capacitor sizing

considerations are outlined, an equation for the optimum selection of the DC link capacitor is

provided. A sample system is used to prove that sizing the capacitor using the equation

provided by the research leads to optimum performance of the STATCOM. The performance

of the capacitor is evaluated under the headings; percentage voltage ripple and speed of

response. By comparing the performance of the calculated capacitor value to randomly

selected capacitor values, the author proves that the capacitor which was correctly designed

performed better in relation to both response time and voltage ripple. An alternative method

for sizing the DC link capacitor is offered in [29]. Similarly, the author presents an equation

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for capacitor sizing however the same robust level of testing undertaken in [28] was not

present in [29]. The main focus of this research was harmonic elimination and although

specific capacitor performance test results were unavailable the system was still found to

behave as the design had intended.

Output filter design considerations and techniques are explored in [14] and [15]. Both studies

offer comprehensive design strategies for the output filter. However, [14] focuses on the LC

filter while [15] concentrates on the LCL filter. The LCL filter is shown to possess improved

performance, although this comes at an increased cost and further design complexity. Both

filters were analysed with the main emphasis on high order harmonic attenuation and

amplification at resonant frequency. The results were confirmed by generating the harmonic

spectrum for each of the filters outputs through Fourier analysis. [14] also offers an

interesting approach to reducing power loss associated with the damping resistor while also

increasing the filtering effect. It is proposed that a small inductor is connected in parallel with

the damping resistor in order to achieve this result. The validity of this system is revealed by

comparing filter power losses before and after the introduction of the inductor. The results

generated substantiate the authors theory, THD of the filter output is improved from 2% to

1.88% while losses associated with resistor decrease from 25.2 W to 0.32 W.

2.3 The STATCOM as a Shunt Connected Compensator

Shunt compensation has been extensively used in the transmission system to enhance system

stability, improve voltage quality and regulate voltage magnitude [3]. Figure 3 illustrates the

equivalent circuit of a typical uncompensated short distribution line and its associated phasor

diagram. If it is assumed that the load at the receiving end is inductive, then it can be said that

it requires reactive power for it to operate correctly. This reactive power must be supplied

from the source end (system generator) which increases the current and apparent power flow

through the line. Shunt compensation supplies this reactive power directly at the receiving

end or from the midpoint of the line which minimises line current, reduces losses and offers

improved voltage regulation at the load terminals.

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11

Figure 3: Uncompensated distribution line

In Figure 4 a shunt compensator has been installed at the receiving end. It compensates the

reactive component of the current at the receiving end and hence the reactive component

being drawn from the source is reduced or almost eliminated. An improvement in voltage

regulation can be seen.

Figure 4: Distribution line with shunt compensation [18]

The power transmission equations can be derived from Figure 3 as follows:

Assuming a lossless line, and IS = IR let the sending end voltage = VS∠δ and the receiving

end voltage = VR∠0°. The resistance of the line will be neglected as it tends to be much

smaller than the inductance.

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12

Therefore, from source [19]:

�⃗� =

|𝑽𝒔|∠𝜹 − |𝑽𝒓|∠𝟎

𝑿

(4)

𝑺𝒓 = 𝑷𝒓 + 𝒋𝑸𝒓 = 𝑽𝒓⃗⃗⃗⃗⃗⃗ × 𝑰�̽�⃗⃗⃗⃗⃗ =

|𝑽𝒓| × |𝑽𝒔|∠𝟗𝟎 − 𝜹

𝑿−

|𝑽𝒓|𝟐 ∠𝟗𝟎

𝑿

(5)

The real power over the line is given in [19] as:

𝐏𝐫 =

|𝑽𝒓| × |𝑽𝒔|𝒄𝒐𝒔 (𝟗𝟎 − 𝜹)

𝑿−

|𝑽𝒓|𝟐𝒄𝒐𝒔 𝟗𝟎

𝑿

(6)

And from this:

𝐏𝐫 =

|𝑽𝒓| × |𝑽𝒔|

𝑿𝐬𝐢𝐧 𝜹

(7)

Similarly, QR is given in [19] as:

𝑸𝒓 =

|𝑽𝒓| × |𝑽𝒔|𝒔𝒊𝒏 (𝟗𝟎 − 𝜹)

𝑿−

|𝑽𝒓|𝟐𝒔𝒊𝒏 𝟗𝟎

𝑿

(8)

This yields:

𝑸𝒓 = 𝑽𝒓 × (𝑽𝒓 − 𝑽𝒔 𝐜𝐨𝐬 𝜹)

𝑿 (9)

Equation (9) is further manipulated in [20] to show:

|𝑽𝒔| − |𝑽𝒓| = 𝑸𝒓 × 𝑿

|𝑽𝒓| (10)

From equation (10) it can be said that the scalar difference between the voltages at either end

of the line depends on the reactive power, i.e. transmitting reactive power causes a voltage

drop across the line.

As previously mentioned, shunt compensation not only improves voltage quality and

regulation but it also improves system stability. Voltage stability refers to the ability of a

system to return to the nominal (pre – fault) voltage at all buses following a disturbance. In a

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13

regular power system (no compensation), the amount of real power transmitted is generally

dependant on the transmission angle (δ), which is the phase angle between the sending end

voltage and the receiving end voltage. The reason for this is that the other parameters

concerning power flow; sending end voltage and line impedance are typically fixed. So as δ

is increased, power flow increases. This is valid up to δ = 90°, at which point power flow is at

its maximum. Any further increase in the angle δ will result in the system becoming unstable.

Therefore system stability margins are employed and this results in δ being maintained below

35° [19]. This in turn limits the transmittable power capacity of the line far below its thermal

loading limit.

The addition of shunt compensation at the midpoint of the line increases the stability margin

of the system as proven in Figure 5, thus increasing the maximum power transfer capability

of the line. The reason for this is that maximum power transfer now does not occur until δ =

180°.

Figure 5: Transmission angle curve [6]

Due to the compensator being connected at the midpoint of a short line, and because the line

is being assumed lossless, it can be stated that VS = VR = V.

After the introduction of the midpoint shunt compensator, the real power transfer across the

line is given in [6] as:

𝑷 =

𝟐𝑽𝟐

𝑿 𝒔𝒊𝒏

𝜹

𝟐

(11)

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14

The reactive power generated by the compensator is given in [6] as:

𝑸 =

𝟒𝑽𝟐

𝑿 (𝟏 − 𝒄𝒐𝒔

𝜹

𝟐)

(12)

From equation (10) it can be said that compensating the reactive power at the receiving end

of the line will reduce voltage drop across the line and from equation (11) and (12) and

Figure 5, it can be said that midpoint compensation will have the additional benefit of

stability improvement.

As previously mentioned, in order to make these improvements to the power system, the

magnitude and phase angle of the compensator output voltage must both be controlled in

order to indirectly control the output current. It is the magnitude control which dictates the

direction of the flow of reactive power. If the magnitude of the compensator voltage is greater

than the system voltage at the PCC then reactive power will flow from the compensator into

the power system (capacitive mode). Conversely, if the system voltage is greater than the

compensator voltage the compensator will absorb reactive power (inductive mode). Figure 6

presents the phasor diagram for both capacitive and inductive mode where VX is the voltage

across the coupling inductance. Due to the fact that current in an inductor lags the voltage

across it by 90° it can be concluded that the direction of the voltage across the inductor

determines the direction of reactive power flow. The purpose of phase angle control is to

ensure that the compensator voltage is almost in phase with the system voltage. In Figure 6

the angle α = 0° for simplicity of the diagram. However in reality a very small phase angle

must be maintained in order to ensure the compensator absorbs some real power from the

system. The real power absorbed supplies the switching and conduction losses of the VSC

and any losses associated with the coupling transformer. Additionally it also maintains the

charge on the DC link capacitor. If this phase angle control is properly achieved it will ensure

that the output current of the compensator is maintained near - 90° thus ensuring almost all

the current being supplied is reactive. A STATCOM designed in this way has no capacity to

deliver real power to the grid.

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15

Figure 6: Capacitive and inductive mode - phasor diagram

The theory outlined in the previous sections was used as a basis for ensuring the correct

design of the compensator. The design procedure will be outlined in the subsequent chapters.

16

3. Sample System and Test Results

3

3.1 Test System

The growing popularity of D-STATCOMs, which has been driven by developments in power

electronics and the push for increased levels of distributed generation on the system has led to

a need for more control and flexibility [5]. This is of particular importance at distribution

level, as the utilisation of renewable energy based generating stations such as wind farms and

solar panel arrays is both unpredictable and non-schedulable. The implementation of a D-

STATCOM provides an innovative solution to these issues. Therefore it seemed fitting to

design a D-STATCOM, the proposed design is for a simple single phase, single source 10

KV system connected by a 75 km long distribution line to a variable industrial load. In an

actual power system a 10 KV line would never be as long as 75 km. This length was chosen

to increase the severity of the problem in order to better demonstrate the impact of the

compensator.

The test system is presented in Figure 7 prior to the inclusion of a D-STATCOM. It was

designed, modelled and analysed in the Matlab/Simulink software package. The system

consists of a 10 KV RMS (phase voltage) source, a 75 km distribution line (impedance

parameters are given in Table 1) connected to an industrial load. The load represents the full

rated loading conditions of the line, in this case that consists of 1 MVA at a power factor of

0.8 lagging. The test system was simulated with the main emphasis placed on; voltage

magnitude at the load, power (real and reactive) being drawn from the supply and current

being drawn from the supply. Figure 8 and Figure 9 show the voltage at the load and the

power delivered to the load respectively.

It can be noted that there is a resistance connected in series with the distribution line in Figure

7. This resistance does not form part of the system and is simply there to fulfil simulation

requirements in Simulink. Its inclusion is deemed negligible in relation to its impact on

system test results.

Sample System and Test Results

17

Figure 7: Uncompensated test system

Distribution line impedance parameters

Resistance [Ω/km] 0.01273

Inductance [H/km] 0.9337 e -3

Capacitance [F/km] 12.74 e -9

Table 1: Distribution line impedance parameters

The 10 KV distribution line is 75 km long and as previously stated should have been

supplying 1 MVA at a power factor of 0.8 lagging and at a voltage of 10 KV. However as

examination of Figure 8 and Figure 9 shows, the load voltage was 8704 V and the load

supplied was only 0.7625 MVA at a power factor of 0.8 lagging. These system test results

suggested that there were voltage regulation issues with this line.

The circuit breaker (CB) present in Figure 7 was opened at 0.8 s in order to allow the

receiving end voltage to return to its steady state no–load value. Further analysis of Figure 8

shows this value to be 10.03 KV. When the CB opened this also resulted in the collapse of

power being drawn from the supply noted in Figure 9.


18

Figure 8: Uncompensated test system - load voltage

Figure 9: Uncompensated test system - load power

Regular two port network transmission/distribution line theory was applied to the

measurements recorded in Figure 8 and Figure 9. This allowed the extent of the voltage

regulation issues to be fully understood and this also facilitated the correct design of the D-

STATCOM parameters.

Firstly it was beneficial to calculate the ABCD parameters of the line as this allowed the

theory to be used to prove the accuracy of the measurements, and in turn ensured maximum

accuracy of all subsequent calculations. Due to the fact that the line used in the test system

was considered a short line (less than 80 km) it was possible to neglect the capacitance of the

line during calculations. Although the capacitance was not neglected by the simulation in

Matlab/Simulink, the error introduced was considered negligible in relation to its impact on

system behaviour. Subsequent calculations are shown in Appendix A, only equations used

and results generated are presented in the following sections.


19

3.2 Test Results Analysis

If Figure 10 is taken as the basis for the line theory, it is given in [21] that:

[𝑽𝒔⃗⃗ ⃗⃗ ⃗

𝑰𝒔⃗⃗ ⃗⃗] = [

𝑨 𝑩𝑪 𝑫

] [𝑽𝒓⃗⃗⃗⃗⃗⃗

𝑰𝒓⃗⃗⃗⃗⃗] (13)

Figure 10: Distribution line equivalent circuit

From Table 1, z = (0.01273 + j0.293) Ω/km, and since Z = z × Ɩ,

Where: Ɩ = 75 km.

It can be stated that; Z = 0.995 + j21.98 [21.996 ∠ 87.512].

Short line ABCD parameters are given as:

A B C D

1 Z 0 1

Table 2: Distribution line ABCD parameters [21]

An equation for 𝑉𝑠⃗⃗⃗⃗⃗ can be derived from equation (13) as follows:

𝑽𝒔⃗⃗ ⃗⃗ ⃗ = 𝑨. 𝑽𝒓⃗⃗⃗⃗⃗⃗ + 𝑩. 𝑰𝒓⃗⃗⃗⃗⃗ (14)

Therefore:

𝑽𝒔⃗⃗ ⃗⃗ ⃗ = 𝑽𝒓⃗⃗⃗⃗⃗⃗ + 𝒁. 𝑰𝒓⃗⃗⃗⃗⃗ (15)

From this 𝐼𝑟⃗⃗⃗⃗ and 𝑉𝑠⃗⃗⃗⃗⃗ were calculated as follows, 𝐼𝑟⃗⃗⃗⃗ = 87 ∠-36.9° A and 𝑉𝑠⃗⃗⃗⃗⃗ = 10.028 ∠8.5°

KV. When these theoretical values were compared to the values measured from the system in

Table 3, the accuracy of the model was confirmed and this enabled the accurate calculation of

percentage voltage regulation for the system. It can be observed that there is an error in Table

3 between measured and calculated values of receiving end current phase angle. This is due

to the aforementioned neglect of capacitance in short line calculations. This error was found


20

not to affect the behaviour of the system. Further analysis of Table 3 shows that δ was

measured as - 0.45°, however the previous calculations show that δ = 8.5°. The reason for this

difference is that in regular distribution/transmission line theory; VR is taken as the reference

phasor i.e. VR∠0°. However in Matlab/Simulink VS is taken as the reference. If δ is defined

as the phase difference between VR and VS, it can be confirmed that the measurements and

calculations are both correct as the phase angle of VR was measured as -8.97°:

𝜹 = |−𝟖. 𝟗𝟕| − |−𝟎. 𝟒𝟓| = 𝟖. 𝟗𝟕 − 𝟎. 𝟒𝟓 = 𝟖. 𝟓𝟐°

Measured Calculated

VS 10KV 10.028KV

IR 87A 87A

Φ -44° -36.9°

δ - 0.45° 8.5°

Table 3: Test results analysis - measured results vs. calculated results

Voltage regulation is given in [21] as:

|𝑽𝒓| (𝒏𝒐 − 𝒍𝒐𝒂𝒅) − |𝑽𝒓| (𝒇𝒖𝒍𝒍 − 𝒍𝒐𝒂𝒅)

|𝑽𝒓| (𝒇𝒖𝒍𝒍 − 𝒍𝒐𝒂𝒅) × 𝟏𝟎𝟎% (16)

Voltage regulation for the test system was calculated as 15%. This was an unacceptable value

for voltage regulation as voltage regulation should be maintained below 10% at all times

[20].

Figure 11: Uncompensated test system - phasor diagram

As previously mentioned voltage regulation less than 10% is acceptable however for the

purpose of demonstration, it was proposed to design a D-STATCOM capable of delivering

the lowest achievable value of voltage regulation (≈ 0%). In this way the impact of the

compensator would be more readily identifiable.


21

If this is applied to equation (16), it yields; VR (no-load) = VR (full-load) = 10 KV. This made

it possible to calculate the maximum required output (MVAR) of the D-STATCOM. Using

equation (17), sourced from [19], to recalculate δ allowed the reactive power requirement of

the line to be calculated. The reactive power requirement of the line was then added to the

maximum reactive power requirement of the load to yield the required output of the

compensator.

𝑺𝒓 = 𝑽𝒔 × 𝑽𝒓

𝑩 ∠(𝜷 − 𝜹) −

𝑨 × 𝑽𝒓𝟐

𝑩 ∠(𝜷 − 𝜶) (17)

Substituting in the required values and solving for δ, yielded a new transmission angle of

10.18°. Equation (17) was then solved for QR by substituting back in the newly calculated

value for δ. In this way the reactive power required by the line when operating at full load

was calculated to be 0.107 MVAR. This was added to the reactive power requirement of the

load (0.6 MVAR) and therefore it was shown that a compensator with a reactive power

compensation capability of 0.707 MVAR was required.

Figure 12: Test system compensator

Applying an appropriate design factor of approximately 15% to the previous results allowed

the maximum output of the D-STATCOM to be determined.

D-STATCOM Ratings

Reactive power capability +/- 0.8 MVAR

Nominal voltage 10 KV

Table 4: D-STATCOM ratings

22

4. D-STATCOM Design Considerations

4

4.1 Criteria Which Influences D-STATCOM Performance When designing a D-STATCOM there are a number of crucial elements which have a direct

impact on the performance of the compensator. It is imperative that all these factors are

carefully considered in order to guarantee optimum performance of the D-STATCOM. The

scope of this report does not cover an in depth analysis of all these factors and each different

option available. A brief summary of each is presented and the most suitable option was

explored in sufficient detail to facilitate the correct design of the D-STATCOM for the

chosen application.

As previously stated, the STATCOM can be based either on the VSC or the CSC. For the

purpose of this research the VSC based type was adopted as current trends in industry are

moving towards the VSC and also the CSC based type introduces a higher level of

complexity with regards to power system and control system design [11]. The VSC consists

of a two arm (level) bridge employing four solid state switching devices with anti – parallel

diodes connected. This topology allows the device, using an appropriate control method, to

generate a sinusoidal voltage with controllable magnitude and phase.

Figure 13: Single phase VSC [22]

D-STATCOM Design Considerations

23

4.2 Switching Scheme

The solid state switches employed have gradually shifted from the GTO towards the IGBT,

and even more recently the IGCT. Amongst these the GTO is still favoured for the highest

power applications being developed globally however for lower power applications such as

the D–STATCOM, IGBTs or IGCTs are preferred. This is because IGBTs and IGCTs have

undergone significant development in recent decades and now boast significantly lower

levels of losses even when switched at high frequencies. This translates to greater degrees of

flexibility when selecting a switching scheme and control strategy. The selection of solid

state switch governs both the control strategy and switching scheme which may be used and

also the switching frequency which may be employed within that switching scheme. For

example the selection of a GTO restricts the control method selection to one choice; phase

angle control employing FFS. As the converter conduction and switching losses are a

function of switching frequency, the PWM control method is not a viable option for high

power rating applications. Conversely FFS is not well suited to lower power applications [7].

For these reasons the IGBT was selected for this application. The selection of a particular

make and model of IGBT introduces further constraints in a real system such as; power

ratings, current and voltage limits, forward bias voltage limits and snubber circuit component

selection. However, as this system is being simulated these constraints were neglected and a

generic Simulink IGBT was selected. Currently the most popular switching schemes in use

are PWM, HCC and SHEM.

4.2.1 Pulse Width Modulation

PWM is one of the most popular switching schemes used for VSCs [6]. It compares an input

(reference) sine wave to a fixed frequency triangular (carrier) wave and this allows the firing

pulses for the solid state switches to be generated. The phase and magnitude of the

fundamental component of the output voltage can be directly controlled by varying the

magnitude and phase of the reference sine wave. The AC output contains harmonics based

around multiples of the switching frequency. The switching frequency can be chosen to

optimise triplen and low order harmonic elimination. However, an output filter is still

required [12].

4.2.2 Hysteresis Current Control

In the HCC method, the current variable is controlled instead of the voltage variable. Control

is achieved by comparing the AC output current to a sinusoidal reference current. The output

current is then maintained within a tolerance band. Similarly to PWM, by varying the


24

magnitude and phase of the reference current wave, the magnitude and phase of the output

current can be controlled [12].

4.2.3 Selective Harmonic Elimination Modulation

The selective harmonic elimination modulation technique requires further “chopping” of the

output waveform at selected angles in order to eliminate selected harmonics. It can employ a

lower switching frequency and thus lower losses. However, the controller design complexity

is increased [23].

4.3 Control Strategy

The switching scheme chosen for the design of the D-STATCOM was PWM. The main

reasons for this choice are that it combines simplicity with robustness to achieve the desired

level of control. Following the selection of an appropriate switching scheme there are further

control considerations to be explored. There are a number of different methods which are

available to generate the required output from the VSC, the most popular methods are; phase

angle control and constant DC link voltage scheme [7].

The phase angle control scheme is mainly employed in square wave control strategies i.e.

FFS. The parameter which must be controlled is the phase angle α, this is the phase angle

between VGRID and VCOMP across the leakage reactance. This method is used to dynamically

control the DC voltage magnitude. Control is achieved by increasing or decreasing α which

results in further charging or discharging of the capacitor. From this approach control of the

output voltage is achieved.

Typically, when a VSC is operated in PWM mode, the constant DC link voltage scheme is

employed. Control is achieved by adjusting two parameters; α and also MA (PWM

modulation index). α is controlled in order to control the rate of absorption of real power

from the grid which supplies converter losses and maintains VDC at a pre – determined value.

This can be thought of as the real power absorption control loop. The reactive power transfer

control loop functions by varying MA in order to vary the direction and amount of reactive

power being transferred. This control strategy is traditionally implemented with a

proportional and integral (PI) control algorithm [7].

4.4 Output Filter

Due to the selection of a control strategy based on PWM, the design of the VSC output filter

is very important as the D-STATCOM should not inject any unwanted harmonics into the


25

grid. The three most common types of filter are a basic L filter, a low pass LC filter and a low

pass LCL filter.

The simplest way to couple the output of the D-STATCOM to the grid is through an L filter.

The inductor sizing calculations are quite straightforward and in some cases the leakage

reactance of the transformer can actually fulfil this role. However this is not an efficient way

of filtering the output and it also does not provide optimum levels of filtering [9]. Better

harmonic attenuation and improved efficiency whilst utilising smaller filtering components is

offered by the third order LCL filter [24]. The LCL filter design calculations are however

more difficult. The maximum allowable current ripple in the inductor is the main design

criteria for an L filter. For an LCL filter there are many more factors to be considered

including; output current ripple, current ripple sourced by IGBTs, series fundamental volt

drop, VAR limits, resonance frequency, stand alone and low voltage ride through

requirements [15].

The second order low pass LC filter can be used as a satisfactory trade-off between the L and

LCL filters. It provides adequate harmonic attenuation with reduced component sizes.

Smaller component sizes translate to a reduced overall cost. The main design factors to be

considered when designing a second order LC filter are; the resonant frequency, harmonic

distortion rate, inductance fundamental volt drop and reactive power compensation ability

[14]. Based on this information, a second order low pass LC filter was adopted for this

application.

4.5 DC Link Capacitor

The final factor to be considered in the design process of a D-STATCOM is the DC link

capacitor. While the reactive power is generated internally by the switching action of the

converter, a DC capacitor must still be connected to the input of the VSC. The main reasons

for this are to provide a voltage source and circulating path for the current [6]. The selection

of a DC link capacitor is a trade-off between two things:

The response time of the D-STATCOM to variations in the required output. A smaller

capacitor ensures faster response times [16].

Ripple voltage on the capacitor should be less than 10% of the nominal capacitor

voltage. Larger capacitors are better in this regard, they are also better for lowering

harmonic distortion on the AC side [16].


26

Thus it can be concluded that the optimum capacitor size is the smallest value which still

satisfies the 10% voltage ripple constraint, however the possibility of resonance for a given

coupling inductance must also be considered as this could lead to high THD of the output.

27

5. D-STATCOM Design Procedure

5

5.1 PWM Analysis

The PWM switching technique consists of comparing a reference (modulating) wave to a

fixed frequency triangular (carrier) wave in order to generate the firing pulses for the IGBTs.

To confirm the suitability of the PWM switching technique for this application it is necessary

to define some terms associated with it. The triangular wave (VTRI) is at a constant frequency

fSW which determines the switching speed of the IGBTs. The modulating wave (VCONTROL)

which can be used to vary the amplitude, phase and frequency of the output is at the required

fundamental frequency f1. The amplitude modulation ratio or modulation index is defined in

[22] as:

𝑴𝑨 = 𝑽𝒄𝒐𝒏𝒕𝒓𝒐𝒍

𝑽𝒕𝒓𝒊 (18)

The frequency modulation ratio is defined in [22] as:

𝒎𝒇 = 𝒇𝒔𝒘

𝒇𝟏 (19)

The peak value of the fundamental component of the output voltage is given in [22] as:

𝑽𝒐 = 𝑴𝑨 × 𝑽𝒅𝒄 (20)

As the proposed application required a full bridge VSC, two voltage switching options were

available, namely; bipolar voltage switching and unipolar voltage switching. Both of which

are a form of carrier based sinusoidal pulse width modulation (SPWM). The amplitude of the

fundamental component of both systems is calculated the same way and is defined in [22] as:

𝑽𝒐 = 𝑴𝑨 × 𝑽𝒅𝒄 ( 𝑴𝑨 < 𝟏) (21)

How this output is achieved and the amplitude and location in the harmonic spectrum of the

dominant output harmonics for these systems differ greatly. Figure 13 was taken as the VSC

which this analysis was based on. Figure 14 shows the output of a VSC if a bipolar switching

scheme is employed. It can be noted that a single modulating wave is compared to a

triangular carrier wave in order to generate the output which switches between two states,

D-STATCOM Design Procedure

28

+VDC and –VDC. Figure 15 presents the results of a Fourier analysis of the output. The output

voltage harmonics appear at sidebands centred around the switching frequency and its

multiples. This is better defined by equation (22) sourced from [10].

𝒉 = (𝒍 × 𝒎𝒇) ± 𝒌 (22)

Where mf is chosen as an odd integer and h is the harmonic order, odd values of l result in

harmonics only being present for even values of k and even values of l result in harmonics

only being present for odd values of k [25]. This is illustrated in Figure 15.

Figure 14: Bipolar switching scheme [25]

Figure 15: Bipolar switching scheme - frequency spectrum [25]

In the unipolar switching scheme shown in Figure 16, a second modulating wave which is

180° out of phase with the original modulating wave is used to give independent control of

leg A and leg B. The output now has three possible states, +VDC, -VDC and 0. This is

advantageous because the switching levels are now from 0 to +/- VDC as opposed to being

from +VDC to -VDC. This switching scheme has the advantage of effectively doubling the

frequency at which the lowest order output harmonics appear [22]. The location of the

harmonics can also be described by equation (22) although in the case of unipolar switching l

= 2, 4, 6… and k = 1, 3, 5…


29

Figure 16: Unipolar switching scheme and frequency spectrum [25]

Examination of Figure 15 and Figure 16 reveals the advantage of unipolar switching. The

frequency spectrum in Figure 16 shows that the lowest order harmonics appear at the

sidebands of 2mf as opposed to the sidebands of mf for a bipolar switching technique. If mf is

chosen as an even integer, the AC output will not contain even harmonics, the output voltage

harmonics will appear at odd frequencies centred around 2mf and its multiples [10]. This is

considered an advantage because the unipolar output contains lower harmonic content and the

harmonics which do appear are pushed further along the frequency spectrum making them

easier to filter and also permitting the use of smaller filtering components. Due to these

benefits, a unipolar switching scheme was employed. For optimum harmonic attenuation by

the switching scheme, mf should be chosen even. The particular value chosen for mf would

usually be constrained by the characteristics of the IGBT selected, however as this will be

tested in a Matlab/Simulink simulation this constraint does not apply therefore mf will be

chosen as 22 i.e. fSW = 1100 Hz (f1 = 50 Hz).

5.2 Controller Design

After an appropriate switching technique was selected, it was important to correctly design

the control loops. Ensuring that the correct parameters are being measured is imperative in

order to achieve the desired control. Having previously selected the constant DC link voltage


30

control method, and also in previous chapters it was outlined how the relationship between

the magnitude of VSTATCOM and magnitude of VGRID govern the direction and amount of

reactive power being absorbed from or injected into the system. It has also been outlined how

the phase angle between the two voltages govern the direction and amount of real power

being transferred. Therefore it can be said that two variables must be measured to implement

the selected control strategy. They are; grid voltage magnitude and DC link voltage.

Typically; control is achieved using PI controllers due to fast response times which can be

achieved and the robust level of control. Figure 17 shows the implementation of the control

scheme in block diagram format.

Figure 17: Controller block diagram

The controller can be split into two separate sections; the active power absorption loop and

the reactive power compensation loop.

5.2.1 Active Power Absorption Loop

The purpose of this control loop is to facilitate the absorption of real power. The compensator

should absorb enough real power to supply its own losses and also maintain VDC at a pre-

determined level. Therefore, if a reference value for VDC is specified and the actual measured

value of VDC is subtracted from this. The error generated can be used to vary the angle α

which in turn will lead to an increase or decrease in the amount of real power absorbed and

hence an increase or decrease in VDC. The error is fed into a PI controller with output limits of

+/- 10. These limits where chosen in order to limit the variation of active power and maintain

stability in the control loop. The output of the PI controller can be thought of as an angle in

degrees and so it must be converted to radians so that it can be added to the output of the

phase locked loop (PLL). The PLL locks onto the phase and frequency of VGRID and

facilitates correct synchronisation between VGRID and VSTATCOM. The PLL outputs a saw


31

tooth wave rising from 0 to 2π. When the angle generated by the PI controller is added to ωt

of the PLL it produces a saw tooth wave phase shifted by an appropriate amount to try and

reduce the error to zero. If this wave is passed through a sine function it produces a phase

shifted sine wave with an amplitude of 1.

5.2.2 Reactive Power Compensation Loop

The purpose of the reactive power compensation loop is to generate the modulation index

(MA) which will be used to vary the modulating wave in the SPWM generator. A pre–

determined reference voltage magnitude must be specified first. In this case that was 10 KV

as this was a 10 KV system. The actual value of grid voltage magnitude can be measured and

subtracted from the set-point in order to generate an error signal. This error signal is fed into

the second PI controller. The output of this PI controller is limited to between 0.3 and 0.9.

These limits are selected to supress the variation in output and hence ensure controller

stability. Over – modulation i.e. MA > 1, is used in some situations however it is not covered

in the scope of this report. The output of this PI controller is taken as MA and it is then

multiplied by the phase shifted sine wave generated by the active power control loop, the

resulting signal is a sine wave with controllable magnitude and phase angle. This sine wave is

used as the modulating wave for the SPWM generator. The SPWM generator automatically

generates the second modulating wave by phase shifting the original wave by 180° and hence

by varying the magnitude and phase of the modulating wave, the magnitude and phase of the

fundamental component of VSTATCOM can be varied.

5.3 PI Controller Tuning

The PI controller gain values were selected by using a trial and error method. As Figure 18

shows, the open loop step response of the system was not first order. This made practical use

of an industry standard tuning rule such as Ziegler–Nichols or Cohen–Coon difficult. Figure

18 shows the response of VLOAD to a step increase in sending end voltage. Optimisation of

controller gain values was achieved by tuning each gain value individually starting with the

reactive power controller, KP (proportional gain) then Ti (integral action time). The same

approach was taken for the active power controller. Gain values were initially set to zero,

then increased while the system response was monitored with a focus on response speed and

reliability.


32

Figure 18: Open loop system step response

The final gain values selected are shown in Table 5.

Kp Ti

PI Controller 1 -50 -5

PI Controller 2 2.7 55

Table 5: PI controller gain values

5.4 Filter Design

The design of the output filter for a VSC is governed by the location, on the harmonic

spectrum, of the harmonics which are introduced by the VSC [9]. Since a unipolar switching

scheme is being used, it was expected that the lowest order harmonics introduced would

appear at the sidebands of 2mf, which is 2200 Hz. The results of a Fourier analysis carried out

in Simulink on the VSC output are shown in Figure 19. Analysis of Figure 19 confirms that

the location of the harmonics are as expected, as the lowest order harmonics can be seen to

appear around 2200 Hz, with a magnitude of almost 45% of the fundamental component.

Total harmonic distortion was recorded at the unacceptably high level of 83.44%. IEEE

standard 519 – 1992 recommends that voltage THD be maintained below 5% and current

THD be maintained below 3%. Figure 20 shows the current harmonics in the D-STATCOM

output. Current THD was recorded as 8.55%.


33

Figure 19: VSTATCOM - Fourier analysis results

Figure 20: ISTATCOM - Fourier analysis results

From Figure 19 and Figure 20 it can be noted that a cut–off frequency less than 2000 Hz is

required for the filter design.

The low-pass LC filter topology shown in Figure 21 was taken as the basis for the filter

design. The transfer function of the filter is defined in [14] as:

𝑮(𝒔) = 𝑽𝒐(𝒔)

𝑽𝒊(𝒔)=

𝑹𝑪𝒔 + 𝟏

𝑳𝑪𝒔𝟐 + 𝑹𝑪𝒔 + 𝟏 (23)

The cut–off frequency for the filter is defined in [14] as:

𝒇𝒄 = 𝟏

𝟐𝝅 × √𝑳𝑪 (24)


34

Figure 21: Low–pass LC filter with passive damping

As it was a consistent design feature in the literature, the filter was designed to provide 20%

of the rated reactive power of the D-STATCOM with a cut–off frequency of 170 Hz. The size

of filter capacitor required was found using equation (25) sourced from [12]:

𝑪 = 𝑸𝒓𝒂𝒕𝒆𝒅 × 𝟎. 𝟐

𝑽𝒈𝒓𝒊𝒅𝟐 × 𝝎𝒈𝒓𝒊𝒅= 𝟓. 𝟏 𝝁𝑭 (25)

From equation (24), LC can be found as:

𝑳𝑪 = (𝟏

𝟐𝝅 × 𝒇𝒄)

𝟐

(26)

Therefore L is calculated as 194 mH.

All calculations are shown in Appendix A. The transfer function for the LC filter stated in

equation (23) was used to obtain the frequency response bode plot for the filter, shown in

Figure 22. The resistor is connected in series with the capacitor to supress the resonance;

therefore its impact on the overall filtering effect must be studied before selecting a suitably

sized resistor. Figure 22 presents the bode plot of the filters frequency response with the

previously stated component sizes for L and C. The blue signal is with R = 100 Ω, the red

signal is with R = 10 Ω and the green signal is with R = 1 Ω. Examination of Figure 22 shows

that a larger value of resistance makes the amplification at resonant frequency smaller

however it results in weaker attenuation of high frequency harmonics and also a larger value

of resistance will result in more power losses. For these reasons a value of 1 Ω was selected

for the resistor. As proposed in [14], the addition of a small inductor in parallel with the

damping resistor will further reduce the power loss by reducing the current flowing through

the resistor and will also aid the filtering effect. Experimentation led to the selection of a 1.18


35

mH inductor. This was connected in parallel with the damping resistor. The final filter circuit

is shown in Figure 23 and the frequency response bode plot is shown in Figure 24.

Figure 22: Frequency response of G(s) with different values of resistance

Figure 23: Low – pass LC filter

Figure 24: LC filter frequency response


36

In order to confirm that the filter was working correctly, the Fourier analysis carried out

previously, and illustrated in Figure 19 and Figure 20 was carried out again after the filter had

been implemented. Figure 25 and Figure 26 show the results of a Fourier analysis carried out

on the output side of the filter.

Figure 25: Filter output voltage harmonics

Figure 26: Filter output current harmonics

Comparing Figure 25 to Figure 19 shows that the filter reduces voltage THD from 83.44% to

3.27% meaning VSTATCOM now complies with the recommendations set out in IEEE 519 –

1992. Comparing Figure 26 to Figure 20 shows that the filter reduces current THD from

8.55% to 3.94%. While ISTATCOM is not below the recommended 3%, current THD at the load

bus – bar was found to be compliant at 0.78%.


37

5.5 DC Link Capacitor Selection

As previously discussed; the most important criteria to be considered when selecting a

suitable DC side capacitor is the open loop response time of the D-STATCOM and the

voltage ripple experienced on the capacitor. Larger values of capacitance result in slower

response times however they serve to decrease voltage ripple and help to minimise harmonics

experienced on the AC side [13]. Through some experimentation with different capacitor

sizes, an 800 μF capacitor was selected for the DC link. Figure 27, Figure 28 and Figure 29

show the voltage on the DC link capacitor with a nominal voltage of 23.6 KV. As these tests

were being carried out in simulation, the specific capacitor type (i.e. electrolytic vs. film)

could not be considered.

Figure 27: DC voltage ripple with 500 μF capacitor



38

From examination of these results it was deduced that both the 800 μF and the 1500 μF

capacitor satisfied the stated voltage constraint (ripple < 10%) while the 500 μF capacitor did

not. Therefore the choice was narrowed down to the two larger capacitors, however the

response speed of the D-STATCOM was found to be unsatisfactory with the 1500 μF

capacitor selected. Hence an 800 μF capacitor was selected for use in the test system. From

Figure 28 it is also possible to calculate the frequency of VDC ripple. This is important

because if the capacitor was not optimally sized the frequency of VDC ripple could coincide

with the resonance frequency and this in turn would lead to high harmonic distortion on the

AC side [10]. From Figure 28 it can be noted that DC ripple frequency = 50 Hz and thus it

can be said that the DC link capacitor will operate correctly [9].


In summary, the designed D-STATCOM has reactive power compensation capabilities of +/-

0.8 MVAR for a nominal grid voltage of 10 KV. The fundamental building block of the

system is the VSC comprising four IGBTs with anti-parallel diodes connected. A constant

DC link voltage control scheme has been implemented by using two PI controllers which

independently control the magnitude and phase of the modulating wave of an SPWM

generator. This in turn generates the firing pulses for each of the IGBTs. The D-STATCOM

output is filtered by a second order low-pass LC filter in order to ensure the output adheres to

recommendations for harmonic distortion set out in IEEE 519 – 1992.

39

6. Compensated Test System, Results and Analysis

6

6.1 System Test Results

The test system presented in Figure 7 is shown again in Figure 30. However the D-

STATCOM is now shunt connected at the receiving end of the line.

Figure 30: Compensated test system

Figure 30 shows the D-STATCOM and associated controller. The system has been re-tested

under the same test conditions that were employed in chapter three. Figure 31 shows the

voltage at the receiving end. Further testing was undertaken to prove the robustness and

reliability of the D-STATCOM. These tests include step increases and decreases of the load

and step increases and decreases of the sending end voltage magnitude. The fluctuation of

sending end voltage is employed to represent the tapping up or down of the on-load tap

changer (OLTC) on an MV transformer.

Analysis of Figure 33 confirms that the D-STATCOM is functioning correctly by

maintaining the voltage at the pre-determined reference voltage of 10 KV. There is an initial

transient period at 0.75 s in which some oscillation of the voltage occurs. This occurs because

the D-STATCOM is initially disconnected. It is only connected to the system via the CB at

Compensated Test System, Results and Analysis

40

0.75 s. The controller then takes a finite amount of time to match the actual magnitude and

phase of VSTATCOM to the required values of magnitude and phase. This oscillation was

minimised by synchronising the controller output with the actual system parameter values

before the compensator is switched in. This synchronisation of the controller output was

found to dramatically reduce transient oscillation upon compensator switch-in and hence

improve the initial response speed of the D-STATCOM. Further analysis of the improvement

offered by the controller synchronisation is presented in Appendix B. As can be seen in

Figure 31, before the D-STATCOM is switched in, load voltage is 8704 V. After the

compensator is switched in, load voltage increased to the reference value of 10 KV, thus it

can be stated that the D-STATCOM rectifies the voltage regulation issue on this test system.

The load being supplied increased to the required 800 KW and 600 KVAR due to the

increase in load voltage magnitude provided by the reactive power compensation from the D-

STATCOM. This is illustrated in Figure 32.

Figure 31: Compensated test system - load voltage

The improvement in voltage regulation can be further confirmed by using equation (16) to

recalculate the new value of voltage regulation for the system. Voltage regulation can now be

said to be ≈ 0%. Comparison of Figure 8 and Figure 31 allows the conclusion to be drawn

that the D-STATCOM functions correctly in the test system. However, further testing was

carried out in order to confirm both the reliability and the robustness of the D-STATCOM.

This testing took the form of step increases and decreases in both load and grid voltage.

System parameters monitored included; load voltage, real and reactive power delivered to the

load, real and reactive power absorbed/injected by the compensator and harmonics

experienced at the load.


41

Figure 32: Compensated test system - load power

6.2 System Parameter Step Test Protocol

In order to confirm that the D-STATCOM could perform reliably under varying conditions,

such as those that would be experienced by an actual 10 KV line connected to an industrial

load, the test protocol outlined in Table 6 was implemented. It presents the response time of

the D-STATCOM to a step change in either load or sending end voltage, that is, the time

taken for the compensator to return VLOAD to the reference value of 10 KV after a change in

system conditions results in VLOAD deviating from 10 KV. Appendix C presents further

results generated by this test.


42

Test Procedure

Simulation Time Sending End

Voltage Load

Compensator

Response Time

0 s – 2.5 s 10 KV P = 800 KW

QIND = 600 KVAR 250 ms

2.5 s – 5 s 10 KV P = 700 KW


5 s – 7.5 s 9.8 KV P = 700 KW


7.5 s – 10 s 9.8 KV P = 200 KW


10 s – 12.5 s 10.5 KV P = 200 KW


12.5 s – 15 s 10.5 KV P = 600 KW


15 s – 20 s 9.9 KV P = 600 KW


Table 6: System test procedure

6.2.1 Test Results Analysis

The initial system conditions which are shown from 0 s to 2.5 s in Table 6 result in a

relatively long response time from the compensator, which is connected to the system at 0.1

s. This is due to the previously mentioned output oscillations experienced upon switching in

of the compensator. This time would be expected to be longer without the use of the

aforementioned compensator synchronisation prior to connection to the system. At 2.5 s the

load is decreased while the sending end voltage is maintained at 10 KV, this results in a

compensator response time of 140 ms. The next step occurs at 5 s, in this case the load is

maintained at the same value while the sending end voltage drops from 10 KV to 9.8 KV.

The compensator response time was measured to be 150 ms. As Table 6 shows, the test

proceeded with various step changes in load and sending end voltage resulting in an average

compensator response time of 177 ms. This length of time would be considered quite long

with respect to STATCOMs in commercial operation worldwide which would have typical

response times of 1 or 2 cycles [30]. Figure 33 presents VLOAD for the test protocol outlined

in Table 6.


43

Figure 33: Comparison of VLOAD with and without compensation

The compensator is operating in capacitive mode (injecting reactive power) from 0 s to 10 s

and from 12.5 s to 20 s. It operates in inductive mode (absorbing reactive power) between 10

s and 12.5 s. This results in the compensator absorbing reactive power between 10 s and 12.5

s in order to stop VLOAD increasing above 10 KV. The proper operation of the D-STATCOM

can be further proved by applying equation (1) and comparing the resulting calculated values

to the measured values. Proper operation in capacitive mode means that the compensator only

supplies reactive power and absorbs some active power. Proper operation in inductive mode

requires both active and reactive power absorption.

6.2.2 Capacitive Mode

Using equation (1) and substituting appropriate parameter measurements recorded at

simulation time (t) = 1.5 s.

Compensator apparent power was calculated as -47.99 + j541.75 KVA, that is to say, the

compensator is absorbing 47.99 KW and supplying 541.75 KVAR. Comparing these

calculated values to Figure 34 highlights a discrepancy in the calculation. It can be noted that

the real power calculation is approximately equal to the measured value, however the reactive

power measured is 158.3 KVAR greater than the calculated value. This difference can be

explained by the filter design. Referring back to section 5.4, it can be noted that the filter was

designed to provide 20% of the reactive power in capacitive mode. Therefore using equation

(27), sourced from [21], it can be proven that the difference between measured and calculated

values is due to the filter capacitor providing the remaining reactive power.


44

Figure 34: Compensator output power

𝑸 = 𝒗𝟐

𝑿𝒄 (27)

Applying equation (27) yields QCAP = 160.2 KVAR, this is confirmed in Figure 35. If QCAP is

subtracted from QTOTAL in Figure 34, it confirms that the calculation is in fact correct and that

the D-STATCOM is indeed producing approximately 541 KVAR. Calculations are shown in

Appendix A.

Figure 35: Power injected by filter capacitor

6.2.3 Inductive mode

The theory applied in the previous section can be reapplied for inductive mode of operation

however the sign preceding the imaginary part of equation (1) must be changed. Therefore

using equation (1) again, and substituting appropriate parameter measurements recorded at

simulation time (t) = 11.5 s, yields compensator apparent power = -12.98 – j238.7 KVA.

Thus it can be said the compensator is absorbing 12.98 KW and also absorbing 238.7 KVAR.


45

This is approximately equal to the values shown in Figure 36. Calculations are shown in

Appendix A.

Figure 36: Power absorbed by the compensator

Referring back to section 2.3, it was stated that the D-STATCOM will have no capacity to

deliver real power to the grid and as such should absorb enough real power from the grid to

maintain VDC and supply losses. If Figure 37 is examined it will be noted that, as per correct

operation, the compensator did not supply any real power and it injected/absorbed reactive

power depending on line and load conditions.

Figure 37: Compensator output power

46

7. Hardware Implementation of Test System

7

7.1 Sample System for Hardware Implementation

In order to fully validate the results outlined in the previous chapter the sample system shown

in Figure 30 was scaled down and modelled in hardware to facilitate real time testing. The

test circuit is shown in Figure 38. It consists of a 30 V RMS source connected to an RLC load

through an impedance which modelled that of a short transmission line. The load consisted of

6.3 VA at 0.92 lagging. The compensator was constructed using a Mitsubishi PM25CL1A120

inverter module, this was interfaced through the BP7B interface module to a dsPIC30F4011

which executed the control algorithm illustrated in Appendix E.

AC Line Impedance

Load (6.3 VA at 0.92 Lag)

Sending End Voltage –�30 V RMS

Coupling Inductance

Inverter Module

VDC –�55V

PCC

ControllerInterface

Circuit

Figure 38: Hardware test circuit

Hardware Implementation of Test System

47

Prior to connection of the compensator to the grid, the importance of the previously

mentioned synchronisation was highlighted. It was extremely important to ensure that

compensator output voltage and grid voltage were equal in frequency, voltage magnitude and

phase prior to connection. Failure to confirm this could result in a large in-rush of current

upon connection which could lead to damage of circuit components.

7.2 Hardware System Testing

The testing methodology used was consistent with the methodology used in simulation.

Firstly the system was energised without the compensator in circuit and various

measurements were recorded. The compensator was then connected to the circuit through a 2

mH coupling inductor and the measurements were repeated. Sending end voltage was

maintained at 30V throughout. The measurements recorded are displayed in Table 7.

Without compensator With compensator

Receiving end voltage 22.5 V 30.9 V

Load current 0.28 A 0.2 A

Real power drawn from the

supply 5.8 W 6 W

Reactive power drawn from

the supply 2.5 VARs - 3.2 VARs

Apparent power drawn from

the supply 6.3 VA 7.2 VA

Power factor 0.92 0.9

Table 7: Hardware system test results

From the results shown in Table 7 it can be seen that the introduction of the compensator

results in an increase in receiving end voltage. It can be concluded, through further

examination of Table 7, that this increase in voltage is a result of reactive power

compensation. It can be seen that the source goes from supplying 2.5 VARs to absorbing 3.2

VARs. This confirms that the compensator is now supplying the reactive power required by

both the line and the load and this leads to the increase in receiving end voltage. The current

being drawn from the supply can also be seen to reduce from 0.28 A to 0.2 A. This occurs

because the reactive component of the current is now being supplied from compensator.

48

8. Conclusion

8

8.1 Discussion

Without doubt one of main challenges facing power utilities is voltage regulation on power

lines. The influence of transmitting reactive power through transmission lines has been

widely documented and has been shown to augment the issue of voltage regulation while

simultaneously decreasing the real power transmission capacity of the line. The intent of this

work was to compensate the reactive power at the receiving end of a line, relieving the line of

the burden of transmitting reactive power from generator to load and thus alleviate any

problems in relation to voltage regulation. In order to effectively illustrate the problem, a

sample system with some inherent voltage regulation issues was presented. Although the

problems presented were perhaps more excessive than those which would be encountered on

an actual power system, the purpose of this was purely to facilitate careful consideration of

the problem and enable an in depth assessment of the implications on the test system. The

extent of the voltage regulation issues were evaluated by application of the voltage regulation

formula. From this mathematical equation it was deduced that the sample system displayed

severe voltage regulation issues as a value of 15% was obtained.

In fulfilment of the projects objectives, a design procedure for a D-STATCOM was initially

outlined and successfully implemented. It was capable of maintaining the voltage at the

receiving end of the line at 10 KV despite fluctuating system conditions. Throughout the

design phase due consideration was given to the recommendations for harmonic limits on the

compensator output set out in IEEE 519 – 1992. A holistic approach was taken when

critically analysing each key aspect of the industry design standard, and through the

application of a clearly defined testing protocol and rigorous mathematical confirmation of

the results, the approach taken was proven to be successful.

As the project proposal intended the D-STATCOM maintained the load voltage at 10 KV.

The authenticity of the results was clearly illustrated through the application of equation (1).

This was applied to show that the compensator was indeed supplying the correct amount of

Conclusion

49

reactive power for a given system voltage. The expected output of the compensator, derived

from calculations, was shown to be consistent with that of the recorded output.

The compensator was designed to provide +/- 0.8 MVAR, while maintaining voltage THD

of the output below 5% and current THD of the output below 3%. The use of a unipolar

SPWM switching scheme meant that the inclusion of a filter on the compensator output

would be necessary in order to meet THD targets. The various filters were assessed based on

high order harmonic attenuation, reducing component size and associated losses. An in-depth

investigation and comparison of several filter types led to the selection of a second order low

pass LC filter. The LC filter seemed the most fitting choice in relation to filter component

size and design complexity. While it was intended to carry out an analysis of losses

associated with the filter, time constraints did not permit this. However some loss

minimisation techniques outlined by research in this area were employed, such as the

connection of a small inductor in parallel with the damping resistor.

From the current literature it would appear that a compensator based on the VSC employing

IGBTs is the prevailing trend within industry. When this trend is considered in unison with

the freedom associated with control strategy/switching scheme selection, the VSC employing

IGBTs becomes the logical topology choice upon which to base the D-STATCOM. The

constant DC link voltage control strategy was utilised as it offered benefits over the phase

angle control scheme such as faster response times and more robust control. While the

control algorithm is slightly more complicated for the constant DC link voltage method, the

specified advantages were deemed to outweigh any additional complexity. The IGBT was

selected over the GTO because of the aforementioned industry trends but also because of its

ability to facilitate a range of different switching schemes with relatively low loss levels.

When the merits of PWM, HCC and SHEM were compared this resulted in the selection of

PWM on the basis that it provided robust and reliable control with a less complex control

algorithm. The use of unipolar SPWM also made the filter design more straightforward as the

location on the harmonic spectrum of the dominant harmonics was more readily identifiable.

If the successful performance of a control loop is to be characterised by its ability to respond

quickly to system disturbances in order to match compensator output with system

requirements, then the design and implementation of the controller can be considered a

success. The D-STATCOM responded to each system perturbation with an average response

time of 177 ms. While the controller was proven to perform as the design plan had intended,

Conclusion

50

there still remains some areas that warrant further study and improvement/development. For

instance the response speed of both PI controllers could be improved to bring the overall

response of the D-STATCOM into line with commercially operational technology which is

about 1 or 2 cycles. This could be achieved by further optimisation of controller gain values

through the use of more advanced tuning methods.

Filter performance is ultimately judged on the ability of the filter to sufficiently attenuate any

harmonics which appear at frequencies greater than the designed cut-off frequency. In this

regard, the filter can be deemed to operate successfully as it was shown to reduce both

voltage and current harmonics to acceptable levels. Voltage THD of the compensator output

was reduced from 83.44% to 3.27% and compensator output current THD was reduced from

8.55% to 3.94%. Even so, with appropriate levels of loss calculation and modelling, further

optimisation of filter components could be possible. In reality this could translate to monetary

savings on passive component procurement.

The design and implementation of the D-STATCOM as a means of voltage regulation for the

given test system can be considered a success for the previously stated reasons which are

validated by simulation results and mathematical analysis. Further scope for the improvement

of the system lies in; the design of a protection scheme for the compensator and further

controller optimisation. Unfortunately, time constraints did not permit further exploration in

either of these areas.

The optional objective stated in the abstract, which was to implement the compensator in

hardware on a scaled down system in order to further validate the results obtained by the

simulation was also completed. While it was not possible to implement every component of

the simulated compensator in hardware, the fundamental components were designed and

implemented and it was shown that the hardware model performed the basic requirements of

a compensator. The hardware model was shown to increase receiving end voltage from 22.5

V up to 30.9 V by injecting reactive power into the system. The completion of this objective

firmly established the validity of the design procedure which was employed and also

highlighted the importance of some issues such as filtering and pre-connection

synchronisation.

The extent of the voltage regulation issues experienced on the test system were more severe

than what might be expected in reality and as such the resulting compensator was somewhat

“over-rated”. In reality a compensator would not be designed in order to reduce voltage

Conclusion

51

regulation to 0%, most compensators are designed to reduce voltage regulation below 10%.

The D-STATCOM was “over-rated” in order to emphasise its impact on such a small scale

system. Most TSOs/DSOs will use a combination of methods to achieve acceptable levels of

voltage regulation rather than the use of a solitary device such as the STATCOM. One of the

most common approaches employed is to use a STATCOM in conjunction with a tap changer

on the sending end transformer.

Without doubt the utilisation of FACTS devices on a transmission level and more recently on

a distribution level within the global power industry is steadily growing. As the levels of

research in this area continue to grow, so too will the influence of the FACTS controller on

the AC power system. Once restricted to high power transmission level implementation;

FACTS controllers are fast becoming commonplace at low and medium power levels. The

drive to eradicate some of the inherent problems of the traditional power system

configuration has led to the utilisation of FACTS devices at distribution level on both the

utility and consumer side. Of these devices the D-STATCOM has undoubtedly established

itself as a highly effective means of mitigating issues in relation to system stability, voltage

regulation, line efficiency and harmonic reduction.

On the basis of the findings presented in this paper, it can be concluded that FACTS

controllers and in particular the D-STATCOM will play a major role in the control of power

systems across the globe. With the projected growth of power systems and the increase in

grid interconnection it has never been more important to ensure optimum levels of system

control are achieved.

52

9. References

9

[1] H. R. Baghaee, M. Jannati, B. Vahidi, S. H. Hosseinian, and H. Rastegar,

"Improvement of voltage stability and reduce power system losses by optimal GA-

based allocation of multi-type FACTS devices," in Optimization of Electrical and

Electronic Equipment, 2008. OPTIM 2008. 11th International Conference on, 2008,

pp. 209-214.

[2] N. G. Hingorani, "FACTS-flexible AC transmission system," in AC and DC Power

Transmission, 1991., International Conference on, 1991, pp. 1-7.

[3] J. J. Paserba, "How FACTS controllers-benefit AC transmission systems," in

Transmission and Distribution Conference and Exposition, 2003 IEEE PES, 2003, pp.

949-956 vol.3.

[4] N. G. Hingorani, "High Power Electronics and flexible AC Transmission System,"

Power Engineering Review, IEEE, vol. 8, pp. 3-4, 1988.

[5] N. G. Hingorani and L. Gyugyi, Understanding FACTS : concepts and technology of

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control and hysteresis current control (HCC)," 2007 2007.

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EAST TECHNICAL UNIVERSITY, 2007.

[14] W. Cunping, Y. Xianggen, W. Minghao, J. Liu, X. Qing, and Z. Bin, "Structure and

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55

10. Appendices

10

10.1 Appendix A - Calculations

10.1.1 Calculations for Section 3.2

Calculation of receiving end current:

𝑰𝒓⃗⃗⃗⃗⃗ = 𝑷𝒓

𝑽𝒓 × 𝐜𝐨𝐬 𝝋 ∠ − 𝝋

𝑰𝒓⃗⃗⃗⃗⃗ = 𝟔𝟎𝟔𝟐𝟓𝟎

𝟖𝟕𝟎𝟒 × 𝟎. 𝟖 ∠ − 𝟑𝟔. 𝟗°

𝑰𝒓⃗⃗⃗⃗⃗ = 𝟖𝟕∠ − 𝟑𝟔. 𝟗° 𝑨

Calculation of sending end voltage:

𝑽𝒔⃗⃗ ⃗⃗ ⃗ = 𝑽𝒓⃗⃗⃗⃗⃗⃗ + 𝒁 × 𝑰𝒓⃗⃗⃗⃗⃗

𝑽𝒔⃗⃗ ⃗⃗ ⃗ = 𝟖𝟕𝟎𝟒∠𝟎° + (𝟐𝟏. 𝟗𝟗𝟔 ∠𝟖𝟕. 𝟓𝟏𝟐 × 𝟖𝟕∠ − 𝟑𝟔. 𝟗)

𝑽𝒔⃗⃗ ⃗⃗ ⃗ = 𝟏𝟎𝟎𝟐𝟖 ∠𝟖. 𝟓° 𝑽

Calculation of voltage regulation:

Voltage regulation = |𝑽𝒓| (𝒏𝒐−𝒍𝒐𝒂𝒅)−|𝑽𝒓| (𝒇𝒖𝒍𝒍−𝒍𝒐𝒂𝒅)

|𝑽𝒓| (𝒇𝒖𝒍𝒍−𝒍𝒐𝒂𝒅) × 𝟏𝟎𝟎%

𝑽𝒐𝒍𝒕. 𝑹𝒆𝒈. = 𝟏𝟎𝟎𝟐𝟖 − 𝟖𝟕𝟎𝟒

𝟖𝟕𝟎𝟒 × 𝟏𝟎𝟎% = 𝟏𝟓. 𝟐%

Recalculation of δ using equation (17):

𝑹𝒆𝒄𝒊𝒆𝒗𝒊𝒏𝒈 𝒆𝒏𝒅 𝒂𝒑𝒑𝒂𝒓𝒆𝒏𝒕 𝒑𝒐𝒘𝒆𝒓 = 𝑺𝒓 = 𝑽𝒔 × 𝑽𝒓

𝑩 ∠(𝜷 − 𝜹) −

𝑨 × 𝑽𝒓𝟐

𝑩 ∠(𝜷 − 𝜶)

𝑺𝒓 = 𝟏𝟎𝒆𝟑 × 𝟏𝟎𝒆𝟑

𝟐𝟏. 𝟗𝟗𝟔 ∠(𝟖𝟕. 𝟓𝟏𝟐 − 𝜹) −

𝟏 × (𝟏𝟎𝒆𝟑)𝟐

𝟐𝟏. 𝟗𝟗𝟔 ∠(𝟖𝟕. 𝟓𝟏𝟐 − 𝟎)

Appendices

56

𝑺𝒓 = 𝟒. 𝟓𝟓𝒆𝟔 ∠(𝟖𝟕. 𝟓𝟏𝟐 − 𝜹) − 𝟒. 𝟓𝟓𝒆𝟔 ∠𝟖𝟕. 𝟓𝟏𝟐

𝐏𝐫 = 𝟒. 𝟓𝟓𝒆𝟔 𝒄𝒐𝒔(𝟖𝟕. 𝟓𝟏𝟐 − 𝜹) − 𝟒. 𝟓𝟓𝒆𝟔 𝐜𝐨𝐬 𝟖𝟕. 𝟓𝟏𝟐

𝟎. 𝟗𝟗𝟕𝟓𝟐 = 𝟒. 𝟓𝟓𝒆𝟔 𝐜𝐨𝐬(𝟖𝟕. 𝟓𝟏𝟐 − 𝜹)

𝟖𝟕. 𝟓𝟏𝟐 − 𝜹 = 𝐜𝐨𝐬−𝟏𝟎. 𝟗𝟗𝟕𝟓𝟐

𝟒. 𝟓𝟓𝒆𝟔

𝜹 = 𝟏𝟎. 𝟏𝟖°

Calculation of line reactive power requirement:

𝐐𝐫 = 𝟒. 𝟓𝟓𝒆𝟔 𝒔𝒊𝒏(𝟖𝟕. 𝟓𝟏𝟐 − 𝜹) − 𝟒. 𝟓𝟓𝒆𝟔 𝐬𝐢𝐧 𝟖𝟕. 𝟓𝟏𝟐

𝑸𝒓 = 𝟒. 𝟒𝟑𝟗𝒆𝟔 − 𝟒. 𝟓𝟒𝟔𝒆𝟔 = −𝟎. 𝟏𝟎𝟕 𝑴𝑽𝑨𝑹

10.1.2 Calculations for Section 5.4

Filter capacitor calculation:

𝑪 = 𝑸𝒓𝒂𝒕𝒆𝒅 × 𝟎. 𝟐

𝑽𝒈𝒓𝒊𝒅𝟐 × 𝝎𝒈𝒓𝒊𝒅

𝑪 = (𝟎. 𝟖 × 𝟏𝟎𝟔) × 𝟎. 𝟐

𝟏𝟎𝟎𝟎𝟎𝟐 × 𝟐𝝅 × 𝟓𝟎= 𝟓. 𝟏 𝝁𝑭

Filter inductor calculation:

𝑳 = (

𝟏𝟐𝝅 × 𝒇𝒄

)

𝑪

𝟐

𝑳 = (

𝟏𝟐𝝅 × 𝟏𝟕𝟎)

𝟓. 𝟏 × 𝟏𝟎−𝟔

𝟐

= 𝟏𝟕𝟐 𝒎𝑯

Further testing and optimisation led to an increase in inductor size to 194 mH.

Calculations used to obtain the bode plot for the selected filter:

𝑮(𝒋𝝎) = 𝑽𝒐(𝒋𝝎)

𝑽𝒊(𝒋𝝎)=

𝑹𝑪𝒋𝝎 + 𝟏

𝑳𝑪𝒋𝝎𝟐 + 𝑹𝑪𝒋𝝎 + 𝟏

𝑮(𝒋𝝎) = 𝟏 + 𝟓. 𝟏𝒆−𝟔𝒋𝝎

𝟏 + 𝟗𝟖𝟗𝒆−𝟗𝒋𝝎𝟐 + 𝟓. 𝟏𝒆−𝟔𝒋𝝎

Appendices

57

Letting ω = 2π.50:

𝑮(𝒋𝝎) = 𝟏 + (𝟓. 𝟏𝒆−𝟔 × 𝒋𝟑𝟏𝟒. 𝟐)

𝟏 + (𝟗𝟖𝟗𝒆−𝟗 × 𝒋𝟑𝟏𝟒. 𝟐𝟐) + (𝟓. 𝟏𝒆−𝟔 × 𝒋𝟑𝟏𝟒. 𝟐) = 𝟏. 𝟏𝟎𝟖𝟐 − 𝒋𝟎. 𝟎𝟎𝟎𝟐

By using this method, and a range of sample values for ω, the behaviour of the filter can be

calculated. Table 8 provides an example of this, the bode plot shown in Figure 24 fully

describes the behaviour of the filter.

f (Hz) 50 150 300 500 1000 5000 10000

|G| 1.1082 8.2427 0.3975 0.1141 0.0263 0.001 0.00026

dB gain 0.89 18.3 -8 -18.9 -31.6 -60 -71.8

Table 8: Filter calculations

10.1.3 Calculations for section 6.2

The values used in this calculation are approximate as the measurements vary slightly

throughout the duration of the simulation. However they can be seen to have an average value

of 10 KV across the duration of the test.

𝑽𝒐𝒍𝒕. 𝑹𝒆𝒈. = 𝟏𝟎𝟎𝟎𝟎 − 𝟏𝟎𝟎𝟎𝟎

𝟏𝟎𝟎𝟎𝟎 × 𝟏𝟎𝟎% = 𝟎%

10.1.4 Calculations for Section 6.2.2 and Section 6.2.3

STATCOM apparent power is given by:

𝑺 = 𝑽𝒈𝒓𝒊𝒅 × 𝑽𝒄𝒐𝒎𝒑

𝑿𝒍𝐬𝐢𝐧 𝜶 + 𝒋 (

𝑽𝒈𝒓𝒊𝒅 × 𝑽𝒄𝒐𝒎𝒑

𝑿𝒍𝐜𝐨𝐬 𝜶 −

𝑽𝒈𝒓𝒊𝒅𝟐

𝑿𝒍)

At simulation time (t) = 1.5 s:

VGRID = 9998.25 V

VCOMP = 13304 V

α = -1.26°

XL = 60.95 Ω

Appendices

58

Therefore:

𝑺 = 𝟗𝟗𝟗𝟖. 𝟐𝟓 × 𝟏𝟑𝟑𝟎𝟒

𝟔𝟎. 𝟗𝟓𝐬𝐢𝐧 −𝟏. 𝟐𝟔 + 𝒋 (

𝟗𝟗𝟗𝟖. 𝟐𝟓 × 𝟏𝟑𝟑𝟎𝟒

𝟔𝟎. 𝟗𝟓𝐜𝐨𝐬 −𝟏. 𝟐𝟔 −

𝟗𝟗𝟗𝟖. 𝟐𝟓𝟐

𝟔𝟎. 𝟗𝟓)

𝑺 = −𝟒𝟕𝟗𝟖𝟗 + 𝒋𝟓𝟒𝟏𝟕𝟒𝟖. 𝟐 𝑽𝑨

Reactive power provided by the capacitor:

𝑸 = 𝑽𝒄𝒂𝒑𝟐

𝑿𝒄

𝑿𝒄 = 𝟏

𝟐𝝅𝒇𝒄

𝑸 = 𝟏𝟎𝟎𝟎𝟎𝟐

𝟔𝟐𝟒. 𝟏= 𝟏𝟔𝟎𝟐𝟑𝟎. 𝟕 𝑽𝑨𝑹𝒔

At simulation time (t) = 11.5 s:

VGRID = 10002 V

VCOMP = 8548 V

α = -0.53°

XL = 60.95 Ω

𝑺 = 𝟏𝟎𝟎𝟎𝟐 × 𝟖𝟓𝟒𝟖

𝟔𝟎. 𝟗𝟓𝐬𝐢𝐧 −𝟎. 𝟓𝟑 − 𝒋 (

𝟏𝟎𝟎𝟎𝟐 × 𝟖𝟓𝟒𝟖

𝟔𝟎. 𝟗𝟓𝐜𝐨𝐬 −𝟎. 𝟓𝟑 −

𝟏𝟎𝟎𝟎𝟐𝟐

𝟔𝟎. 𝟗𝟓)

𝑺 = −𝟏𝟐𝟗𝟕𝟓. 𝟓 − 𝒋𝟐𝟑𝟖𝟔𝟔𝟑. 𝟗 𝑽𝑨

10.2 Appendix B - Controller Synchronisation

As discussed in section 6.1, the controller was synchronised to the grid voltage prior to

connection of the D-STATCOM. The purpose of this synchronisation was to minimise any

oscillations in compensator output power upon switch – in. The synchronisation ensured

VCOMP was equal to VLOAD prior to connection to the grid. This had the added effect of

slightly decreasing the time taken to return VLOAD to 10 KV. The improvement offered by

this technique can be noted in Figure 39, Figure 40 and Figure 41. The peak of the spike in

output power can be seen to have been reduced by 0.2 MVAR and 0.2 MW by the

introduction of synchronisation. The synchronisation could be further improved if the

compensator could predict how much reactive power would be required at the moment it is

Appendices

59

connected. This could possibly be achieved by measuring the power flowing in the line and

VGRID prior to connection of the compensator and then applying equation (1) to calculate the

required magnitude of VSTATCOM. Time constraints did not permit further exploration of this

theory.

Figure 39: D-STATCOM output power - without synchronisation

Figure 40: D-STATCOM output power - with synchronisation

Figure 41: Comparison of VLOAD with and without synchronisation

Appendices

60

10.3 Appendix C - Further Results from Section 6.2

Figure 42 shows the power being drawn from the supply. As per correct operation of the D-

STATCOM it can be seen that no reactive power is being drawn from the supply until 10 s, at

this point the D-STATCOM begins operating in inductive mode. It must absorb reactive

power in order to prevent a voltage swell.

Figure 42: Power drawn from supply

Figure 43 illustrates the result of a Fourier analysis carried out on the load voltage. It can be

noted that it is fully compliant with IEEE 519 – 1992 recommendations. Figure 44 presents

the results of a Fourier analysis carried out on load current, it is also shown to be fully

compliant with IEEE 519 – 1992 recommendations. In both cases the Fourier analysis was

carried out on the relevant signal sampled between 0.75 s and 2 s.

Figure 43: VLOAD Fourier analysis

Appendices

61

Figure 44: ILOAD Fourier analysis

Appendices

62

10.4 Appendix D - Full Model of Test System

Appendices

63

10.5 Appendix E – Hardware Control Algorithm

System

Configuration

Declare Global

Variables

Configure ADC

Configure

UART

Configure

PWM mode

Call ISR Reset ISR FlagUpdate PDC1

Value

Fill Data Buffer

With 200

Samples and

Return Data to

Main

Calculate

Amplitude and

Phase of Sample

Signal

Check if in

Synchronisation

or

Compensation

Mode

If in Sync.

Mode Match

Inverter Voltage

to Grid Voltage

If in Comp.

Mode Increase

or Decrease

Inverter Voltage

Until Load

Voltage = Set

point

Is Inverter

Frequency =

Grid

Frequency?

Yes No

If Inverter

Frequency <

Grid Frequency

Decrease

PTPER

If Inverter

Frequency >

Grid Frequency

Increase PTPER

START

Interrupt Service Routine

Appendices

64

10.6 Appendix F – Program Executed on dsPIC

//

// This dsPIC30F4011 example program generates a PWM signal

// with duty cycle modulated by a 50 Hz sinusoidal input signal.

// The PWM frequency is 10 kHz and an input sinusoid (the grid voltage)

// is sampled on AN0 and recorded to a buffer.

// The buffer takes 200 samples in each period of the input sine wave.

// The data stored in the buffer is then analysed using a discrete

// Fourier transform in order to extract the amplitude and phase of

// the input. The program has two modes of operation, synchronising

// mode and compensating mode. When in sync. mode the output of the

// inverter is matched to the input using the values obtained from

// the DFT. When in comp. mode the output of the inverter is varied

// in order to bring the input wave to a specified set-point, in

// this case 30 V.

//

#include <xc.h>

#include <libpic30.h>

#include <math.h>

#include <stdio.h>

// Configuration settings

_FOSC(CSW_FSCM_OFF & FRC_PLL16); // Fosc=16x7.5MHz, Fcy=30MHz

_FWDT(WDT_OFF); // Watchdog timer off

_FBORPOR(MCLR_DIS & PWMxL_ACT_LO & PWMxH_ACT_LO & RST_PWMPIN); // Disable

reset pin

// Sample buffer for input voltage waveform

#define N 200

int buffer[N] = {0};

// cos look-up table

const float cos_table[N] = {

1.00000, 0.99951, 0.99803, 0.99556, 0.99211, 0.98769, 0.98229,

0.97592, 0.96858, 0.96029,

0.95106, 0.94088, 0.92978, 0.91775, 0.90483, 0.89101, 0.87631,

0.86074, 0.84433, 0.82708,

0.80902, 0.79016, 0.77051, 0.75011, 0.72897, 0.70711, 0.68455,

0.66131, 0.63742, 0.61291,

0.58779, 0.56208, 0.53583, 0.50904, 0.48175, 0.45399, 0.42578,

0.39715, 0.36812, 0.33874,

0.30902, 0.27899, 0.24869, 0.21814, 0.18738, 0.15643, 0.12533,

0.09411, 0.06279, 0.03141,

0.00000,-0.03141,-0.06279,-0.09411,-0.12533,-0.15643,-0.18738,-

0.21814,-0.24869,-0.27899,

-0.30902,-0.33874,-0.36812,-0.39715,-0.42578,-0.45399,-0.48175,-

0.50904,-0.53583,-0.56208,

-0.58779,-0.61291,-0.63742,-0.66131,-0.68455,-0.70711,-0.72897,-

0.75011,-0.77051,-0.79016,

-0.80902,-0.82708,-0.84433,-0.86074,-0.87631,-0.89101,-0.90483,-

0.91775,-0.92978,-0.94088,

-0.95106,-0.96029,-0.96858,-0.97592,-0.98229,-0.98769,-0.99211,-

0.99556,-0.99803,-0.99951,

-1.00000,-0.99951,-0.99803,-0.99556,-0.99211,-0.98769,-0.98229,-

0.97592,-0.96858,-0.96029,

-0.95106,-0.94088,-0.92978,-0.91775,-0.90483,-0.89101,-0.87631,-

0.86074,-0.84433,-0.82708,

-0.80902,-0.79016,-0.77051,-0.75011,-0.72897,-0.70711,-0.68455,-

0.66131,-0.63742,-0.61291,

Appendices

65

-0.58779,-0.56208,-0.53583,-0.50904,-0.48175,-0.45399,-0.42578,-

0.39715,-0.36812,-0.33874,

-0.30902,-0.27899,-0.24869,-0.21814,-0.18738,-0.15643,-0.12533,-

0.09411,-0.06279,-0.03141,

0.00000, 0.03141, 0.06279, 0.09411, 0.12533, 0.15643, 0.18738,

0.21814, 0.24869, 0.27899,

0.30902, 0.33874, 0.36812, 0.39715, 0.42578, 0.45399, 0.48175,

0.50904, 0.53583, 0.56208,

0.58779, 0.61291, 0.63742, 0.66131, 0.68455, 0.70711, 0.72897,

0.75011, 0.77051, 0.79016,

0.80902, 0.82708, 0.84433, 0.86074, 0.87631, 0.89101, 0.90483,

0.91775, 0.92978, 0.94088,

0.95106, 0.96029, 0.96858, 0.97592, 0.98229, 0.98769, 0.99211,

0.99556, 0.99803, 0.99951,

};

// This variable is used to coordinate use of the buffer

// between the main function and the PWM ISR

//

// State 0: buffer available (main sets this)

// State 1: buffer waiting to fill (main sets this)

// State 2: buffer filling (ISR sets this)

// State 3: buffer full (ISR sets this)

//

int buffer_state = 0;

// magnitude and phase variables

float A_setpoint = 0.8; // what A_load should equal at nominal grid voltage

float A_load = 0; // measured from analog input

float A_inverter = 0; // calculated value for PWM output

float A_inverter_max = 0.95, A_inverter_min = 0.3; // maximum and minimum

values of inverter "MA"

int phi = 0, previous_phi = 0;

// operating mode variable

#define SYNCHRONISING_MODE 0

#define COMPENSATING_MODE 1

int operating_mode = SYNCHRONISING_MODE;

// Function prototype for analog read function

unsigned int read_analog_channel(int);

//

// PWM ISR

//

void __attribute__((interrupt, auto_psv)) _PWMInterrupt(void)

{

// Reset PWM interrupt flag

_PWMIF = 0;

// Update duty cycle using value from look-up table

static int n=0;

int i;

n = (n + 1) % N;

i = (n + phi + N) % N;

PDC1 = PTPER + PTPER * A_inverter * cos_table[i];

// If buffer is waiting, then start filling when n=0

if (buffer_state == 1 && n == 0) buffer_state = 2;

// If buffer is filling, record a sample

Appendices

66

if (buffer_state == 2)

{

buffer[n] = read_analog_channel(0);

if (n == N-1) buffer_state = 3;

}

}

int main(void)

{

// Configure RD0 as a digital output for an indicator LED

TRISD = 0b1110;

// Configure AN0-AN8 as analog inputs

ADCON3bits.ADCS = 15; // Tad = 266ns, conversion time is 12*Tad

ADCON1bits.ADON = 1; // Turn ADC ON

// Enable UART for printing debug info

U1BRG = 48; // 38400 baud @ 30 MIPS

U1MODEbits.UARTEN = 1; // Enable UART

// Configure PWM

_DTAPS = 0b01; // Set deadtime prescaler to 1:2

_DTA = 42; // Generate a deadtime of about 2.8us

_PMOD1 = 0; // PWM channel 1 in complementary mode

_PEN1H = 1; // Enable PWM1H pin

_PEN1L = 1; // Enable PWM1L pin

_PWMIE = 1; // Enable PWM interrupt

_PTCKPS = 0; // prescale=1:1 (0=1:1, 1=1:4, 2=1:16, 3=1:64)

PTPER = 2999; // Set PWM frequency to 10 kHz

PDC1 = 3000; // Set initial duty cycle

_PTEN = 1; // Enable PWM time base

// This is the main function. The ISR is called here, the ISR then

// fills the buffer full of data (200 samples) and returns this to

// the main function. The main function then completes the DFT to

// calculate the phase and amplitude of the input. The main function

// then checks which mode of operation it is in and then decides

// what to do with the output based on this.

while(1)

{

// Change buffer state to "waiting" and wait for it to be full

buffer_state = 1;

while(buffer_state != 3);

// Turn on LED on RD0 to signal start of frame analysis

_LATD0 = 1;

// Calculate phase and amplitude of data in buffer

int n;

float re, im;

re = 0;

im = 0;

for (n=0 ; n<200 ; ++n) // Carry out DFT analysis

{

re += buffer[n] * cos_table[n];

im -= buffer[n] * cos_table[(n+3*N/4)%N];

}

re = re / (512.0 * N);

im = im / (512.0 * N);

A_load = 2 * sqrt(re*re + im*im);

previous_phi = phi;

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67

phi = 100.0 * atan2(im, re) / 3.141592653589793; // convert to

sample offset

// Check switch input to see which operating mode compensator

should be in

if (_RD3 == 1) operating_mode = COMPENSATING_MODE;

else operating_mode = SYNCHRONISING_MODE;

// Set inverter amplitude according to current operating mode

if (operating_mode == SYNCHRONISING_MODE)

{

A_inverter = A_load;

}

else if (operating_mode == COMPENSATING_MODE)

{

if (A_load < A_setpoint && A_inverter < A_inverter_max)

A_inverter = A_inverter + 0.001;

else if (A_load > A_setpoint && A_inverter > A_inverter_min)

A_inverter = A_inverter - 0.001;

}

// Check if phase has changed significantly since previous frame.

// If it has the inverter frequency (basically determined by PTPER)

// may not be matched to the grid frequency, so adjust PTPER.

int delta_phi;

delta_phi = phi - previous_phi;

if (delta_phi == 0)

{

// no change

}

else if (delta_phi > 0 && PTPER > 2500)

{

// if phi needs to be increased, that means we're nudging

// forwards in the lookup table, which means the inverter

// isn't "keeping up" with the grid oscillation. Therefore,

// inverter frequency needs to be increased by decreasing

// the value of PTPER.

PTPER = PTPER - 1;

}

else if (delta_phi < 0 && PTPER < 3500)

{

// if phi needs to be decreased, that means we're nudging

// backwards in the lookup table, which means the inverter

// is "overtaking" the grid oscillation. Therefore,

// inverter frequency needs to be decreased by increasing

// the value of PTPER.

PTPER = PTPER + 1;

}

// Print some debugging information

printf("%5d %5d %5d %f %f\n", PTPER, PDC1, phi, A_load,

A_inverter);

// Turn off LED on RD0 to signal end of frame analysis

_LATD0 = 0;

}

return 0;

}

// This function reads a single sample from the specified

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68

// analog input. It should take less than 5us when the

// microcontroller is running at 30 MIPS.

// The dsPIC30F4011 has a 10-bit ADC, so the value

// returned is between 0 and 1023 inclusive.

unsigned int read_analog_channel(int channel)

{

ADCHS = channel; // Select the requested channel

ADCON1bits.SAMP = 1; // Start sampling

__delay32(30); // 1us delay @ 30 MIPS

ADCON1bits.SAMP = 0; // Start Converting

while (!ADCON1bits.DONE); // Should take 12 * Tad = 3.2us

return ADCBUF0;

}

STATCOM Project - Submission Draft

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