STAR TOF Readout Electronics and DAQ Joachim Schambach University of Texas at Austin For the STAR...

STAR TOF Readout Electronics and DAQ

Joachim Schambach

University of Texas at Austin

For the STAR TOF Collaboration

CHEP 2003 J. Schambach, UT Austin 2

The STAR TOF CollaborationP. Fachini, Zhangbu XuBrookhaven National Laboratory

Feng Liu, Lianshou Liu, Zhixu Liu, Jinghua Fu, Yuan Hu, Zhiming Li, Yuanfang Wu, Yan LuHuaZhong Normal University, Wuhan, China

Jin Li, Junguang Lu, Bingyun ZhangInstitute of High Energy Physics (IHEP), Beijing, China

Wenlong Zhan, Zhiyu SunInstitute of Modern Physics (IMP), LanZhou, China

D. Hardtke, F. Retiere, N. XuLawrence Berkeley National Laboratory, Berkeley, CA

L. KotchendaMoscow Engineering Physics Institute, Moscow, Russia

J.W. MitchellNASA - Goddard Space Flight Center, Greenbelt, MD

G. Paic, E. Cuautle, A. Martinez, G. CalderonUNAM & CINVESTAV, Mexico City, Mexico

B. Bonner, G. Eppley, F. Geurts, W.J. Llope, T. Nussbaum, J. RobertsRice University, Houston, TX

Wenging Shen, Yugang Ma, Xiangzhou CaiShanghai Institute of Nuclear Research (SINR),Shanghai, China

Kejun Kang, Jianping Cheng, Yuanjing Li, Yulan Li, Yi WangTsinghua University, Beijing, China

C. Whitten, H. Huang, G. Igo, V. Ghazikhanian, S. Trentalange, A. Tai, H. LongUniversity of California - Los Angeles, Los Angeles, CA

Hongfang Chen, Xin Dong, Xiaolian Wang, Ziping Zhang, Cheng Li, Lijuan Ruan, Shuwei Ye, Jian Wu, Ming Shao, Shengli HuangUniversity of Science and Technology of China (USTC), Hefei, China

G. Hoffmann, A. Ishihara, C.F. Moore, L. Ray, J. Schambach, H. Ward

University of Texas, Austin, TX

T. Trainor

University of Washington, Seattle, WA

C. Markert

Yale University, New Haven, CT


RHIC at BNL


Multi-Gap Resistive Plate Chamber Developed in collaboration with

the ALICE TOF group CERN experiment HARP has

been using it for 2 years Tested at CERN in 2000/01 and at

AGS in 2002 Prototype tray with 192 channels

in current STAR run Timing-resolution < 100ps,

efficiency > 95% Measure large & small scale

correlations Increase statistics for multi-

strange baryon measurements Extend the Pt range of ID’d

particles in STAR

Gas: 90%C2H2F4

5% Iso-Butane

5% SF6

Pad Geometry


TOF Tray Design


Electronics OverviewSTAR TOF: PARTITIONING AND DATA FLOW FOR 1 DETECTOR TRAY

TFEE(24 CHAN)

4 RPCMODULES(6 CHANEACH)

TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TFEE(24 CHAN)


TDIG(4 TDC ICs

TOTAL)

TCPU

32 RPC MODULESPER TRAY( = 192 DETECTORCHANNELS PER TRAY)

8 TFEE CARDS PERTRAY

8 TDIG CARDS PERTRAY

1 TCPU CARD PERTRAY

TDC READOUT CHAIN

MULTIPLICITY (96 CHAN)

TDC READOUT CHAIN

MULTIPLICITY (96 CHAN)

TMIT

FORMATTED DATA

OPTICAL FIBER DATA LINK

FORMATTEDDATA FROM 3OTHER TRAYS

1 TMIT CARD PER4 TRAYS

---------------------------17.25 CIRCUITCARDS PER TRAY

MULTIPLICITY OUTPUT TO TRIGGER

NOTE: CLOCK AND CONTROL NOT SHOWN

TDRCDATA LINK TO DAQ


On Detector Electronics

TFEE

RPCDETECTORS

(24 CHANNELS)AMPLIFIER

CONSTANTTHRESHOLD

DISCRIMINATOR

THRESHOLD

4 TIME-TO -DIGITAL I.C.s:

3 FOR RISING EDGES +1 FOR FALLING EDGES

MULTIPLICITYLOGIC

LOCAL DATAPROCESSING

READOUTCONTROL

CONFIGURATIONCONTROL

TDIG

TIMING

TCPU

TDC CLOCK& MULTIPLICITY

GATE

JTAG CONFIGURATIONAND STATUS

24

23 MORE CHANNELS

MULTIPLICITYLOGIC

JTAG

TEMPERATUREMONITOR

FASTREADOUT

CHAIN

STAR TOF: FUNCTIONAL PARTITIONING

TEMPERATUREMONITOR

THRESHOLDSETTING

Maxim 3760 AD96687

CERN HPTDC ASIC


Off Detector Interface Electronics

STAR TOF: TCPU FUNCTIONS

AGGREGATEMULTIPLICITY

(½ TRAY)

TRIGGERCOMMAND

PROCESSING

READOUTCONTROL

BUFFER

HIGH SPEEDTRANSMIT

DAUGHTER-BOARD

TEMPERATUREMONITOR

CONFIGURATIONAND STATUS

CONTROL

AGGREGATEMULTIPLICITY

(½ TRAY)

JTAG

DATA FROM 4 TDIG CARDS

CONFIG/STATUSTO/FROM 4 TDIG CARDS

TRIGGER ANDACQUISITION

TIMEBASEREFERENCE

MULTIPLICITY INPUT FROM ½ TRAY(4 TDIG CARDS)

MULTIPLICITY INPUT FROM ½ TRAY(4 TDIG CARDS)

SYSTEMTIMEBASE

TO TRIGGER

TO TRIGGER

SERIALBUS

COMMANDSFROM

TRIGGER

FIBER OPTICLINK TO TDRC

TDC CLOCK AND MULTIPLICITY GATE

DATA FROM 3 OTHER TCPU CARDS

TCPU

TMIT

TEMPERATURE DATA AND THRESHOLD SETTING


DAQ Receiver

Token

Data

Header

Header

Fibre

Fibre Deserializer

Header Decoder(Trigger Command & Token)

Data Distribution

4096 Token Buffers1 TOF Tray




4096 TokenBuffers

Header Data

VME Interface

Trigger Decoder

TokenFIFO

TOF DAQ Receiver CardTDRC

Token

VME Interrupt on“not empty”

TriggerFIFO

TriggerData

Trigger Data(For Debugging)


TDIG & TFEE PrototypesTDIG TFEE


TDIG Prototype: “Jalapeno”(SBIR with Lloyd Bridges, Blue Sky Electronics)

FEEDIGITAL

FEEANALOG

INTGRATE Q +ADC

TDC 1&2

PLD MICRO

JTAG

16

CONNECTOR + INTERFACE BOARD

RS-232

CAN BUS

ICD-2

PC

JTAGMUX

Microchip PIC18F8720 (with CANbus & Serial port) Altera APEX 20K family PLD 2 HPTDC’s, independent or chained JTAG interface Analog meant for comparison of slewing correction, section not (yet)

implemented (final version will use time-over-threshold)


“Jalapeno” Test Environment

PLD used for I/O routing to/from TDC Micro used for power-up sequencing and interface to PC TDC programming via JTAG Current readout of TDC via JTAG as well JTAG software interface via “Standard Test and Programming

Language” (STAPL), a JEDEC standard (JESD71), originally the “JAM” Programming & Test Language from Altera

Free STAPL “player” available from Altera, including source code Jam player code modified to write optional data files from JTAG

output Jalapeno used to learn the (rather complicated) HPTDC ASIC Used to verify that proposed time resolution can be achieved Initially used pulsers, then interface with prototype TFEE


HPTDC Architecture


Internal Time Resolution

HPTDC measures timestamps only

Pulse generated by TDC clock is used to reset TDC, so all data points fall into approximately the same bin

A delayed version of this pulse is used as hit (with delays generated by an HP8131A pulse generator)

Delay & Sigma

13599

13600

13601

13602

13603

13604

13605

13606

50 100 150 200 250 300

Delay

Tim

eb

in

0

5

10

15

20

25

30

Delay

Sigma


TFEE and TDIG Time Resolution Timebin & Sigma

14140

14142

14144

14146

14148

14150

14152

14154

0 50 100 150 200 250 300 350

Delay (ps)

Tim

ebin

0

5

10

15

20

25

30

35

40

Sig

ma

(ps)

Timebin

Sigma

Data from complete TFEE and TDIG chain

Input pulser lightly coupled and capacitively loaded to simulate MRPC’s

STAR TOF Readout Electronics and DAQ Joachim Schambach University of Texas at Austin For the STAR...

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Transcript of STAR TOF Readout Electronics and DAQ Joachim Schambach University of Texas at Austin For the STAR...