ST1232 Touch Screen Controller

Datasheet

Note: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change.

Version 0.6

2010/05/04

P r e l i m i n a r y

ST1232

Preliminary Ver 0.6 Page 2/13 2010/05/04

1 INTRODUCTION

The ST1232 is a low-cost single chip solution for capacitive touch screen. It is 8-bit RISC architecture microcontroller devices with SPI, I2C and I/O mode. For function application, the ST1232 support button/coordinate information for customers. The capacitive touch sensor is covered with a plastic or glass case. It provides auto-calibrate the parameter for a wide range of capacitance on the touchpad sensor. The system controller converts finger data to button presses, depending on finger location and human interface context. The ST1232 supports QFN package.

ST1232

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FEATURES ���� MCU based touch controller ���� Operation voltage

– VDD = 2.4V ~ 3.6V – IOVDD = 1.8V ~ 3.6V

���� Temperature: -40 ℃℃℃℃ ~ 85℃℃℃℃ ���� Interface

– I2C (slave) – SPI (slave)

���� Sensor input: 32 channel ���� Screen Size: up to 5.0” ���� Resolution: 2048 x 2048 ���� Single finger handwriting ���� Up to three finger gestures ���� Capacitive Sensor

– Self-capacitance sensing – Resolution: 8fF/50 points/mm – Max. loading: 100 kOhm/200pF – Speed: 100us/ch, 8ms/point – 14-bit A/D converter – Hardware noise reduction – Waterproof circuit

���� Power Consumption – Normal mode: 5mA – Power down: 5uA

���� Package

– I2C/SPI interface

QFN 6x6

QFN 5x5

Pin No. 48 40 Sensor 32 28

APPLICATIONS ���� Cell phones ���� PDAs ���� Portable instruments ���� Touch screen monitors ���� Electrical papers ���� Gaming machines ���� Pointing devices ���� PC peripherals

ST1232

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2 PACKAGE INFORMATION

V18_2 1

2

3

413

14

15

16

5

6

7

8

9

10

11

12

17

18

19

20

21

22

23

24

36

35

34

33

32

31

30

29

28

27

26

25

48

47

46

45

44

43

42

41

40

39

38

37

GND

IOVDD

RESET

SS/SCL

SCK/SDA

MISO

MOSI

GPIO1

GPIO0

S31

VDD

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

GND

C2

C1

VCM

V18_1

QFN48

Figure 2-1 Package Pin Configuration (QFN48)

Table 2-1 Package Signal Descriptions (QFN48)

Pin # Pin Name Description 1 V18_2 Core power, connect to 4.7uF capacitor 2 GND Ground 3 VDD Power supply 4 IOVDD I/O power supply 5 RESET System reset signal input, active low

6 SS /SCL SPI: slave select I2C: serial clock

7 SCK /SDA SPI: serial clock I2C: serial data

8 MISO SPI: master input/slave output 9 MOSI SPI: master output/slave input

10 GPIO1 General purpose input/output 11 GPIO0 General purpose input/output

43~12 S0~S31 Touch sensor input 44 GND Ground 45 C2 Connect capacitor tenfold to touch pad capacitor 46 C1 Connect capacitor tenfold to touch pad capacitor 47 VCM Common mode voltage, connect to 0.1uF 48 V18_1 Core power, connect to 4.7uF capacitor

ST1232

Preliminary Ver 0.6 Page 5/13 2010/05/04

Figure 2-2 Package Pin Configuration (QFN40)

Table 2-2 Package Signal Descriptions (QFN40)

Pin # Pin Name Description 1 V18_2 Core power, connect to 4.7uF capacitor 2 GND Ground 3 VDD Power supply 4 RESET System reset signal input, active low

5 SS /SCL SPI: slave select I2C: serial clock

6 SCK /SDA SPI: serial clock I2C: serial data

7 GPIO1 General purpose input/output 8 GPIO0 General purpose input/output

9~36 S1~S31 Touch sensor input, except S0, S17, S18, S19 37 C2 Connect capacitor tenfold to touch pad capacitor 38 C1 Connect capacitor tenfold to touch pad capacitor 39 VCM Common mode voltage, connect to 0.1uF 40 V18_1 Core power, connect to 4.7uF capacitor

ST1232

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3 SYSTEM MANAGEMENT

3.1 Power Down

In power down mode, all of the clocks of ST1232 are stopped, including internal oscillator. The way to exit power down mode is by a reset. In power down mode, ST1232 consumes a few current, less than 5uA. 3.2 Reset

3.2.1 Master Reset

Master can reset ST1232 through RESET pin. RESET pin is low active and needs hold low for 1us to take effect.

Figure 3-1 RESET Pin Low Pulse Width

3.2.2 Power On Reset

ST1232 provides an on-chip Power-On-Reset (POR) circuit to detect power-on and to reset internal logic before VDD reached the pre-determined POR threshold voltage. Under VDD=3.3V, the POR threshold voltage is set to be about 2.1V. Sometimes, when the VDD is power-off and quickly power-on again, there might be cases that the POR will work improperly and internal reset might not be generated. For this reason, it is also highly recommended user should have a long time between power-off and next power-on to ensure proper start-up. The time depends on actual system board environment and how much decoupling capacitors between power and ground. User has to take into account this effect during board level design.

3.2.3 Watch Dog Timer Reset

The watchdog timer (WDT) protects the ST1232 from incorrect code execution over a long period of time by causing a system reset when the watchdog timer overflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count.

ST1232

Preliminary Ver 0.6 Page 7/13 2010/05/04

4 DIGITAL INTERFACE

4.1 SPI Interface (Slave)

SPI provides full-duplex, synchronous serial communication between ST1232 and host controller. It is a 4-wire protocol, consisting of slave select( SS /SCL), clock(SCK/SDA), master data input/slave data output(MISO), and master data output/slave data input(MOSI). The SPI can only be configured to operate as salve in ST1232 and clock is always provided by master. Data is sampled at rising edge of the clock.

Figure 4-1 SPI Waveform 4.2 I2C Slave Interface

ST1232 equipped with I2C provide two wires, serial data (SDA) and serial clock (SCL), to carry information transfers at up to 400 kbit/s(Fast mode). ST1232 plays a slave role in I2C transfer. Both SDA and SCL are bidirectional lines, connected to IOVDD via pull-up resistors. All transactions begin with a START (S) and can be terminated by a STOP (P). 7-Bit address follows START to recognize device. Each bye is 8-bit length and followed by an acknowledge bit. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Read

Write

Figure 4-2 I2C Waveform

ST1232

Preliminary Ver 0.6 Page 8/13 2010/05/04

5 ELECTRICAL CHARACTERISTIC

5.1 DC Electrical Characteristics

Table 5-1 System DC Electrical Characteristics

Condition: VDD = IOVDD = 3.3V, TA = 25°C, unless otherwise specified.

Parameter Symbol Min. Typ. Max. Unit Condition

VDD VVDD 2.4 3.3 3.6 V

IOVDD VIOVDD 1.8 3.3 3.6 V

Operating Current INML - 5 - mA

Power Down Current IPD - 5 - uA

Input High Voltage VIH - 1.9 - V

Input Low Voltage VIL - 1.3 - V

Input Pull Up Resistor RPU - 56 - KOhm

Output Driving Current IDRV - 40 - mA VOH=0.7xVDD

Output Sinking Current ISINK - 70 - mA VOL=0.3xVDD

Low Voltage Reset VLVR - 1.6 - V

5.2 AC Electrical Characteristics

Figure 5-1 I2C Fast Mode Timing

Table 5-2 I2C Fast Mode Timing Characteristic

Conditions: VDD = IOVDD = 3.3V, GND = 0V, TA = 25°C Rating Symbol Parameter

Min. Typ. Max. Unit

fSCL SCL clock frequency 0 - 400 kHz tLOW Low period of the SCL clock 1.3 - - us tHIGH High period of the SCL clock 0.6 - - us

tf Signal falling time - - 300 ns tr Signal rising time - - 300 ns

tSU_STA Set up time for a repeated START condition

0.6 - - us

tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated

0.6 - - us

ST1232

Preliminary Ver 0.6 Page 9/13 2010/05/04

tSU_DAT Data set up time 100 - - ns tHD_DAT Data hold time 0 - 0.9 us tSU_STO Set up time for STOP condition 0.6 - - us

tBUF Bus free time between a STOP and START condition

1.3 - - us

Cb Capacitive load for each bus line - - 400 pF

Figure 5-2 SPI Timing

Table 5-3 SPI Timing Characteristic

Conditions: VDD = IOVDD = 3.3V, GND = 0V, TA = 25°C Rating Symbol Parameter

Min. Typ. Max. Unit

tSS_SCK SS falling to 1st SCK falling 41.6 - - ns tCYC SCK cycle time - 83 - ns tDS Data setup time prior SCK rising 2 - - ns tDH Data hold time after SCK rising 2 - - ns tDD MISO data output delay from SCK falling 10 - - ns

tSCK_SS SCK rising to SS rising 41.6 - - ns

ST1232

Preliminary Ver 0.6 Page 10/13 2010/05/04

6 APPLICATION CIRCUITS

Figure 6-1 Application Circuit

ST1232

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7 PACKAGE DIMENSION

Figure 7-1 Package Dimension (QFN48)

ST1232

Preliminary Ver 0.6 Page 12/13 2010/05/04

Figure 7-2 Package Dimension (QFN40)

ST1232

The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Preliminary Ver 0.6 Page 13/13 2010/05/04

8 REVISION

REVISION DESCRIPTION PAGE DATE

0.6

� Add QFN40 to package table � Add Figure 8-1 Package Pin Configuration (QFN40) � Add Table 8-1 Package Signal Descriptions (QFN40) � Modify Figure 8-1 I2C Waveform � Add Figure 8-2 Package Dimension (QFN40)

3 5 5 7

12

2010/5/4

0.5

� Revise DC electrical characteristics. � Revise SPI timing “tDD” parameter . � Modify Figure 6-1 Application Circuit . � Change package dimension.

7 8 9

10

2010/2/24

0.4

� Modify introduction section description � Delete QFN5X5 package � Modify V18_1 and V18_2 pin description � Modify Figure 6-1 Application Circuit

2 3 4 9

2009/12/18

0.3

� Rename SS/SCK to SS/SCL � QFN48 pin10 is renamed from GPIO0 to GPIO1. Pin11 is renamed from

GPIO1 to GPIO0 � Revise typing error in Figure 5-2 SPI Timing and Table 5-3 SPI Timing

Characteristic � Modify Figure 6-1 Application Circuit

3,4,6 4

8

9

2009/10/23

0.2

� Modify introduction chapter � Rename sleep keyword to power down � Rename SCK/SS to SS/SCK , SDA/SCK to SCK/SDA � Add package information chapter � Add system management chapter � Add digital interface chapter � Add tDH parameter in Figure 5-2 SPI Timing and Table 5-3 SPI Timing

Characteristic � Modify Figure 6-1 Application Circuit � Add package dimension chapter

2 3,7 3 4 5 6 8

9 10

2009/09/09

0.1 � First release 2009/08/26