sramcell

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010 93

Statistical Design of the 6T SRAM Bit CellVasudha Gupta and Mohab Anis, Member, IEEE

Abstract—In this paper, a method for the statistical design ofthe static-random-access-memory bit cell is proposed to ensure ahigh memory yield while meeting design specifications for perfor-mance, stability, area, and leakage. The method generates the nom-inal design parameters, i.e., the widths and lengths of the bit-celltransistors, which provide maximum immunity to the variationsin a transistor’s dimensions and intrinsic threshold-voltage fluc-tuations. Moreover, the need to deviate from the conventional bit-cell sizing strategy to obtain a high-yield low-leakage design in thenanometer regime is demonstrated.

Index Terms—Circuit optimization, design methodology, static-random-access-memory (SRAM) chips.

I. INTRODUCTION

C URRENTLY, more than 50% of the area of system-on-chip designs is occupied by embedded memory [1]. This

is due to the increasing integration of functional blocks that re-quire large memories for data manipulation and storage. The useof minimum-size transistors in static random access memories(SRAMs), along with technology scaling, increases the intrinsicvariability, causing a large deviation in the transistor proper-ties such as the threshold voltage . This and the varyingtransistor dimensions adversely impact the yield of SRAMs.Memory yield is the percentage of the number of bit cells thatmeet all the functionality and performance requirements, evenunder variability. For an SRAM, the bit cell is functional if it al-lows for a nondestructive read and a successful write. Tradition-ally, these have been evaluated as static noise margin (SNM) andwrite trip voltage (Vtrip), respectively. The performance con-straints are the desired memory speed and leakage.

It should be noted that the SRAM design involves the evalu-ation of several bit-cell architectures and layout topologies forprocess–layout interactions. It also requires the choice of SRAMspecific physical design rules and the assessment of their robust-ness. At this level, process developers are involved. However,this phase of the bit-cell development is not analyzed in thispaper. This paper is of significance to the circuit designer, whois involved in the ‘electrical’ design phase. This entails the op-timal selection of the transistor sizes to avoid parametric failuressuch as destructive read, write, and access failures and excessiveleakage, which can occur due to variations in the transistor pa-rameters. From now on, ‘bit-cell design’ refers to this electricaldesign phase.

In large measure, the variability in the bit-cell metrics, suchas the SNM, Vtrip, speed, and leakage, is caused by intrinsic

Manuscript received June 15, 2008; revised November 15, 2008. First pub-lished March 06, 2009; current version published January 22, 2010. . This paperwas recommended by Associate Editor J. Pineda de Gyvez.

The authors are with the Department of Electrical and Computer Engineering,University of Waterloo, Waterloo, ON N2L3G1, Canada (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TCSI.2009.2016633

variations, which, in turn, are related to the bit-cell transistor di-mensions. Therefore, to meet the specifications for all the bit-cell design metrics (some of which are conflicting) in the min-imum possible area, the widths and lengths of the bit-cell tran-sistors must be chosen optimally [12]. The impact of variabilityon the design metrics should be considered up front during thedesign phase to maximize yield.

However, the current industrial practice is to first develop adatabase, by simulations, which characterizes the design met-rics for various transistor sizes. This is used to carefully choosethe sizes of the bit-cell transistors. Monte Carlo (MC) simula-tions are run for the chosen design to verify if variations in thedesign metrics such as the SNM are within the desirable bounds.The chosen design is updated, and MC simulations are run it-eratively, until all the design metrics meet the specifications.Another approach is to develop analytical functions for the de-sign metrics, as a function of the device sizes. These are thendeployed to choose nominal transistor sizes. These procedureshave many drawbacks. The characterization, through simula-tions, is quite time consuming. These methods are iterative andrely on manual transistor-size selection. Moreover, the chosendesign may not be optimal, it may be an overdesign with largerarea. In this paper, a systematic statistical design method to de-termine the optimal size of the bit-cell transistors is proposed.The proposed framework is capable of eliminating the charac-terization step completely. Currently, the electrical bit-cell de-sign in the industry takes about two to three weeks or even more.However, with the proposed method, the optimal design can beobtained in a day or two.

The various causes of variability in transistor dimensions aresubwavelength lithography, proximity effects, etc. [2], [3]. Theintrinsic variability is caused by the atomistic-level differencesbetween the devices, even though they might have identical lay-outs and environments. This manifests primarily as variationsin the device . The main reasons for variations are fluc-tuations in the number and location of the dopant atoms in thechannel [random dopant fluctuation (RDF)], line edge rough-ness, and oxide-thickness variations [4]. Of these, the most sig-nificant factor is observed to be the RDF [4], [5], [6], [8]. In addi-tion, the distribution due to RDF is normal, and the variance

is inversely proportional to the channel area. In [7], thechannel-area component of the for fabricated MOSFETsis observed to be dominant.

Because of the intrinsic variations, the SNM, read current,and Vtrip are observed to have normal distributions [9]–[11].Technology scaling has a twofold impact on the SRAM. First,an increase in the due to scaling SRAM transistors causesthe distributions of SNM, read current, and Vtrip to take a largersigma value. Second, the increase of the memory density at eachsuccessive technology node requires the bit cell to tolerate alarger number of sigma variations (e.g., – ) in the designcharacteristics [13] to ensure a satisfactory memory yield.

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94 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

However, little work has been done to propose a system-atic framework to design the bit cell, while incorporating theimpact of the statistical variations in the design metrics, upfront. Methods to optimize one of the design metrics, e.g.,read access or leakage, have been proposed [41]–[43], butwe could only find [12], which attempts to optimize the yieldconsidering all design metrics. Reference [12] uses the conceptof failure probability to choose the sizes of bit-cell transistors.However, it ignores the joint failure probabilities (e.g., readand speed failure occurring together) because of computationalcomplexity. Therefore, the obtained design solution need notbe optimal. On the other hand, in this paper, the bit-cell failuresare formulated as problem constraints. Because the solutionof the optimization problem requires that all the constraintsbe satisfied simultaneously, the failure of the bit cell due tothe simultaneous occurrence of two or more reasons is alsoaccounted for. Additionally, [12] ignores interdie variations.It also uses semianalytical models at three stages: 1) for thetransistor characteristics (such as the saturation current andleakage); 2) for the design metrics such as the write time; and3) for variability and yield. The modeling of the transistorcharacteristics and design metrics not only induces approxima-tion errors but also has limited usage in the industry, becausedesigners prefer available SPICE models. In this paper, theproposed method does not use analytical modeling for eitherthe transistor characteristics or the design metrics. Modeling isdone only for variability and yield (i.e., stage 3). This reducesapproximation and makes the proposed method attractive andpractical for industrial usage.

In this paper, the proposed method provides nominal tran-sistor dimensions that provide the maximum immunity to theintrinsic fluctuations due to RDF and the variability in thetransistor dimensions. It involves a minimal infrastructure formodel building and mathematical computations and uses readilyavailable models and tools in the industry for simulation. More-over, the proposed formulation imparts the necessary flexibilityto tune the design as per the specifications, as demonstratedin Section IV. High-performance moderate-leakage and low-leakage moderate-performance bit cells in the 45-nm CMOStechnology are designed and analyzed. It is shown that the con-ventional sizing is no longer sufficient to ensure a high yield fora low-leakage bit-cell design.

In Section II, the bit-cell design constraints are described.Section III formulates the statistical design problem and de-scribes the yield optimization. The results and observations arediscussed in Section IV. Section V concludes this paper.

II. PRELIMINARIES

A. Design Constraints

A typical 6T SRAM bit cell is shown in Fig. 1(a). M1 and M2are called drivers, M3 and M4 are load transistors, and M5 andM6 denote the access transistors. The output nodes of inverters1 (M1 and M3) and 2 (M2 and M4) are called VL and VR,respectively. For subsequent discussions, assume VL at logic“0” and VR at logic “1.” A brief overview of the bit-cell designmetrics, such as the SNM, Vtrip, read current, leakage, and area,follows.

1) SNM: SNM is the maximum static noise that the bit cellcan tolerate, while still maintaining reliable operation [13], [16],

Fig. 1. (a) 6T SRAM bit cell. (b) Sample SRAM bit-cell layout from [19].

[17]. The bit cell is the most unstable (the least SNM) when theword line (WL) is turned ON for read. VL rises to an interme-diate voltage level due to the voltage divider action between M1and M5 and can flip the bit cell. Generally, the driver shouldbe stronger than the access transistor [12]–[14] to ensure a non-destructive read since VL remains close to the ground. In thispaper, SNM is measured by dc simulation when .

2) Vtrip: This is measured by dc simulation. To determine ifthe bit cell is writable, a dc sweep is applied on in Fig. 1(a),and the maximum bit-line voltage at which the bit cell flips isnoted as the Vtrip [13], [14] or Vtrip. The bit cell should havea reasonable value for the Vtrip [13] to guarantee that no unin-tended write occurs during the read cycle and that write is nottoo difficult. Typically, the access transistors should be strongerthan the load devices.

3) Read Current: The bit-line current through the access anddriver stack, i.e., M5 and M1 in Fig. 1(a), during the read cycleis the performance metric for the bit cell [13]–[15]. To a largeextent, the read access time is governed by the time requiredto develop a certain differential voltage between the bit lines asone of them discharges during read. This is a function of thebit-cell read current, which can also be measured by dc simula-tion. During the read operation, leaks though the M6 tran-sistor of idle bit cells (when in the idle bit cell) inthe column. If the voltage dips too much, it may cause er-roneous sensing. This can be prevented if the leakage is keptwithin reasonable limits. Therefore, to ensure a successful read,the designer also needs to carefully calculate the maximum tol-erable leakage limit.


GUPTA AND ANIS: GUPTA AND ANIS: STATISTICAL DESIGN OF THE 6T SRAM BIT CELL 95

4) Bit-Cell Leakage: The leakage current in the bit cell isthe primary contributor to the overall memory leakage. It is thesum of various components, e.g., the subthreshold leakage, gateleakage, and band-to-band tunneling. In this paper, the total bit-cell leakage, measured by dc simulation, is considered.

5) Area: The bit cell can have different types of layout[12], [18], [19]. Researchers at IBM [21], Intel [22], andTexas Instruments Incorporated [23] have proposed RestrictiveDesign Rules (RDRs) such as single-orientation poly-silicongates, resulting in geometries that are more regular with en-hanced manufacturability [20]. Some of these have alreadybeen adopted as best practices for memory [23]. The layouttopology in 45-nm technology from [19] is used in this paperand reproduced in Fig. 1(b). The corresponding tight designrules are also mentioned in [19]. The and dimensions of thebit-cell layout are calculated as a function of the layout rules asfollows:

(1)

In Fig. 1(b), all diffusion contacts have a diffusion layer un-derneath (not visible), but there is no diffusion layer overhungaround the contact. This is because the design rules for SRAMare scaled beyond those of standard logic—process design rulesand several design rules are violated within the array to achievea competitive area [38]. Post-layout lithographic correction isused to ensure a robust layout [39]. The rectangular contacts arethe coupled contacts, which are used to strap poly and diffusionfor cross-coupling without using metal [38]. It should be notedthat (1) can be easily modified to formulate the and dimen-sions of any different layout topology.

The bit-cell area is very important from the economic per-spective. For a good SNM, the driver needs to be stronger thanthe access transistor. However, the access transistor cannot bemade too small since this degrades the read current. Addition-ally, the access transistor needs to be reasonably strong to enablea successful write. The strength of the load can be reduced toimprove the Vtrip, but a very weak load deteriorates the SNM,although the impact is small. The lengths of the driver and ac-cess can be reduced to improve the read performance, but thisadversely impacts the leakage, which has become a serious con-cern these days. The problem is further compounded because ofprocess variations. The aforementioned discussion outlines thebit-cell design problem.

TABLE IWORST CASE OPERATING CONDITIONS FOR DESIGN CONSTRAINTS

B. Preparatory Work

The bit-cell design is constrained by the specifications forSNM, Vtrip, read current, and leakage. Each of these shouldbe satisfied for a range of operating parameters (voltage andtemperature), design parameters (transistor width/length), andstatistical parameters (process fluctuations such as ).

1) Operating Parameters: These are often more critical andcan be accounted for by evaluating the design metrics at theirrespective worst case operating conditions. For example, theleakage is the worst at high temperature (subthreshold leakagebeing the primary component) and high supply voltage. Simi-larly, read current should be simulated at the performance cornerto meet the timing goal. The number of performance cornersand the voltage and temperature for each performance cornerare determined by the intended set of applications, e.g., for mo-bile applications, the operating temperature is lower than thatfor high-performance applications. The performance corner inthis paper has low voltage and high temperature (for worst readcurrent). Table I documents the worst case operating conditions(low or high) for all the design metrics.

Most of the behavior in Table I should remain the same for alltechnologies. The worst case voltage condition for SNM (when

) is interesting for the 45-nm technology. At highvoltage and high temperature, the SNM begins to degrade as VRstoring “1” leaks excessively through M2. This behavior can bearrested, if the cell ratio (the ratio of the of the driver tothat of access) is increased, as shown in Fig. 2. With a higher ,VL storing “0” remains closer to ground (stronger “0”), and thegate voltage of M2 reduces, thereby shutting it off more effec-tively. However, since the proposed solution explores the entirespace of the allowable transistor sizes, SNM is simulated at bothhigh and low voltages. A nominal supply voltage of 1 V is as-sumed, and predictive technology models are employed in the45-nm technology [28].

2) Design Parameters: These are the widths and lengths ofthe driver, access, and load transistors. In this paper, the interdievariations in the widths and lengths of transistors are consid-ered. Since the gate length impacts significantly, interdiethreshold-voltage variations are also accounted for implicitly[24]. According to the International Technology Roadmap forSemiconductors (ITRS) [32], the gate-dimension variations havea value of 12% of the physical gate length. With a physicalgate length of 25 nm in the 45-nm technology [12], [32], thevariation in the gate dimension is selected as 3 nm (a differenttransistor length can be chosen for the design, but the varia-tion remains fixed at 3 nm).

3) Statistical Parameters: is the most significant statis-tical parameter. Because of the small area of the SRAM bit cell,the close proximity of the transistors, the use of restricted de-sign rules, a highly regular layout, and fairly controlled processfor the array fabrication, the effect of intradie variations in the



Fig. 2. SNM variation with voltage and temperature. (a) � � �. (b) � � ��.

channel length and width is negligible [12]. Therefore, in thispaper, the intrinsic variation due to RDF is considered asthe main source of intradie variation.

The variations of six transistors are considered to be sixindependent and uncorrelated Gaussian random variables [10],[12]. Moreover, —the standard deviation of the dis-tribution of a minimum-sized transistor—is an input parameter.

is usually available in the process development kits ofvendors. Then, the for a transistor of width and length

is related to the transistor size as follows [4], [12]:

(2)

At the circuit-design level, the designer can specify only thenominal values of the geometrical transistor dimensions (de-sign parameters) and has little control over statistical parameterssuch as the variations due to mismatch. However, as shownby (2), the choice of design parameters is used to control the ex-tent of device mismatch.

III. PROBLEM FORMULATION

A. Intradie Variation

To consider the impact of intrinsic fluctuation due to RDF,a conservative method is to calculate the worst case changefor each of the six transistors (e.g., sigma) and evaluatethe design constraint for this case [34]. However, this approachoverestimates variability and gives poor results in terms of bit-cell area. Therefore, the statistical approach is applied in thispaper to model the intradie variations.

Because of the intrinsic variations, the design met-rics—SNM, Vtrip, and read current—exhibit Gaussian distri-butions [13]. To statistically model the impact of the intrinsic

variations due to RDF, on the design metrics, the statisticalaverage and variance of the Gaussian distributions of the design

Fig. 3. SNM (in volts) distribution as obtained from MC simulations.

metrics must be estimated. This can be done by using the Taylorseries expansion as follows [11], [12], [40]:

(3)

(4)

Equations (3) and (4), contain the of the driver, access,and load transistors, which can be calculated by (2). isthe simulated SNM at mean values. The partial derivativeterms are also computed at mean values numerically by sim-ulation. In the aforementioned two equations, the term ‘SNM’can be replaced by Vtrip, Iread, or leakage.

The results of modeling have been verified by MC simula-tions. For example, the SNM average and standard deviationfrom MC simulations are 131.8 and 22.1 mV, respectively(Fig. 3). The corresponding estimated values from modelingare 132.1 and 21.6 mV, respectively. Similarly, Fig. 4(a) showsthat the average leakage and standard deviation, from the 45-nmbit-cell leakage MC results, are 77.2 and 8.9 nA, respectively.The estimated values from modeling are 77.7 and 8.57 nA, re-spectively. For our purpose of modeling, this level of accuracyis sufficient.

The coefficient of on the right-hand side (RHS) of (4)contains the slopes of SNM versus and . These will beinterchanged if the opposite data value (1 instead of 0) is stored



Fig. 4. Leakage (in microamperes) distribution histogram and normal proba-bility plot for (a) single-memory bit cell and (b) the sum of the leakages of 16bit cells.

in the bit cell, but the overall coefficient of and, hence,will remain the same, irrespective of the data value stored

in the bit cell.Within-die variations cause each memory bit cell of millions

in an array to differ slightly from all the others in the SNM, readcurrent, Vtrip, and leakage. The number of identical bit cellsand the expected electrical yield to the specifications determinethe number of sigma , over which the bit cell must operateproperly [11], [13]. Typically, the number of sigmas requiredfor the SNM, Vtrip, read current, and bit-cell leakage rangesfrom 4 to 5. This is used in the proposed problem formulationto incorporate the effect of intradie variations. The constraintsof the optimization problem take the following form:

(5)

In (5), a constraint is put on the SNM yield instead of theSNM value. The value of is selected according to the re-quired yield and redundancy. Both the and areimpacted by the choice of the nominal design parameters, as ob-served from (2) to (4). The constraints for Vtrip and read currentare formulated in a similar way.

The constraint bounds, also called residuals, such as thein (5), impart the necessary flexibility to design

different types of the bit cell. Such bounds on the read current(lower limit) and leakage (upper limit) enable the design ofa bit cell with a high or moderate performance and a low orultralow leakage. The residuals on SNM and Vtrip are used tobuild margin for reliability. The constraint is shown in Fig. 5.

However, the bit-cell leakage does not have a normal distri-bution with the variation, and (5) cannot be used directly.Leakage has a lognormal distribution because of the exponentialrelationship of subthreshold leakage with the threshold voltage(subthreshold leakage is the primary component). The usage ofthe central limit theorem [40] helps to model the sum of the

Fig. 5. Pictorial representation of the SNM design constraint.

leakage of a sufficiently large number of bit cells normally [12].Fig. 4 shows that the sum of the leakages of 16 bit cells ( ofevery transistor in each of the 16 bit cells is a random variable)displays a normal distribution. The use of 16 bit cells is reason-able, since the deployment of memories as storage elements isjustified for only a certain minimum number of bits, becauseof the associated overhead of the peripherals in memories. Themean and sigma values of the sum of the leakages of 16 bit cellsis given as follows [40]:

- -

- - (6)

Now, the total leakage of 16 bit cells can be treated as a designmetric, and the corresponding constraint can be expressed as

- - -, where can range from 4 to 5, depending on

the desired yield. Moreover, -- .

B. Yield Maximization

The within-die threshold-voltage variations and the de-sign constraints are a function of the transistor sizes, asshown by (2)–(4). The transistor sizes (design parame-ters)— —define a 6-Dparameter space. Within this parameter space, the design con-straints (5) modeling within-die variations define a feasibleregion. The nominal design should be chosen somewhere inthis feasible region, so as to best satisfy the design constraints.At the same time, the variations in the transistor dimensionsshould also be considered. This can be done as follows.

If the spread of the design parameters is known (e.g.,value of normally distributed widths and lengths), the nominaldesign can be specified within a certain imaginary box, calledthe tolerance box. This is shown graphically in two dimensions(for illustration) in Fig. 6 for an arbitrary feasible region definedby arbitrary constraints. The dimensions of the tolerance box aredetermined by the spread of the design parameters. The centerof the box is the nominal design (since the design parametersare assumed to have a normal distribution, hence symmetrical).The smaller dots within this box represent all the possible de-sign realizations. The fraction of the area of the tolerance boxthat overlaps the feasible region determines the yield. The tol-erance box should be moved (the nominal design moves withit) so as to ensure the maximum overlap of the box and the fea-sible region (region of widths and lengths), which satisfy all thedesign constraints of within-die variations (5), thus maximizingthe overall yield. The inner box in Fig. 6 captures the maximum



Fig. 6. Simplified yield maximization method in two dimensions.

rectangular overlap that can be attained between the feasible re-gion and the tolerance box and can be used to estimate the yielddirectly [37]. In six dimensions (which is the case of bit-celldesign problem), the 6-D volume of the inner box, henceforthcalled the yield box, defines the yield.

In this paper, the feasible region is determined implicitly, i.e.,whether a design point lies in the feasible region is determinedby simulations and by checking if all the design constraints aremet. The typical design centering approach needs an explicitfeasible region, i.e., the design constraints should be expressedas analytical expressions. This is not always possible and re-quires either a polytope approximation or simulations for curvefitting the data in the region of interest, which becomes difficultwith the increase in the number of dimensions [25].

Qualitatively, the problem is reduced to finding and , thecoordinates of the yield box in Fig. 6, such that the followingconditions are satisfied: 1) the maximum difference betweenand is not more than the maximum spread in design parame-ters (the yield box should lie within the tolerance box) and 2) theyield box lies in the feasible region (all the points lying withinthe box satisfy all the design constraints that cover within-dievariations).

If the aforementioned conditions are met, then for the nom-inal design placed at the center of the yield box, the probability(yield) that the design constraints are satisfied in the presence ofparameter variations is estimated in two dimensions (for illus-trative purposes) as follows:

- and

where , , , and form the coordinates of theyield box (in two dimensions as in Fig. 6) and rep-resents the cumulative distribution function of [33]. In six di-mensions (which is the case of our problem)

(7)

where is the th design parameter. The solution of (7) in-volves the evaluation of a multidimensional probability integralby quadrature or MC-based methods, which is computationallyexpensive [25]. However, the problem is simplified if a closed-form expression for CDF can be used. Because a Gaussian dis-tribution does not have a closed-form CDF, a double-boundedprobability distribution function (DB-PDF), proposed by Ku-maraswamy [26] is employed. This is appropriate for physicallybounded dimensions. With this model, the PDF is given by

where (8)

In (8), is the normalized value of , and and are thelower and upper bounds, respectively, of the DB random vari-able . and are the shape parameters, and distributions suchas uniform, triangular, and Gaussian can be obtained by usingdifferent values of and . A truncated Gaussian shape is usedin this paper with variation as the design spread around thenominal design . Therefore

(9)

In (9), represents the maximum spread on the design param-eter . The closed-form DB-CDF can be obtained by integrating

and is given by

(10)

Due to the symmetrical nature of the distribution of the designparameters, the final optimized design solution is the center ofthe yield box and is computed as

(11)

Therefore, by using DB-CDF and (7), (10) and (11)

(12)

Equation (12) gives the probability of finding a design solu-tion in the 6-D yield box, given the probability distributions of



Fig. 7. (a) SNM variation with� and� . (b) Constraint minimization.

the widths and lengths of the transistors. Maximizing this wouldmaximize the yield.

Equation (12) expresses the yield as a function of and ,the coordinates of the yield box. Our intent is to widen the di-mensions of the yield box to approach the tolerance box. Whiledoing this, the yield box should lie in the feasible region theentire time. To achieve this, as a first-order condition, it is suffi-cient to check the constraint violation at the extreme corners ofthe yield box, which are given by . For example, in twodimensions, there are corner points for the yield box, asshown in Fig. 7(b). Here, and are the possible nominaldesign solutions (center of the yield box). – are the cornersof the yield box around . In six dimensions, for each choiceof the nominal design, it is required to simulate atcorners for each design constraint to ensure that the yield boxlies in the feasible region. However, this number can be reducedsignificantly by applying the design understanding, e.g., as thedriver transistor is made stronger, the SNM improves, but de-grades with an increase in the strength of the access transistor,as shown in Fig. 7(a). Clearly, the SNM should be checked atonly in two dimensions, as shown in Fig. 7(b).For the other three corners, the SNM is only going to be better.Using this approach, the number of constraint evaluation cor-ners can be minimized. By using constraint minimization in sixdimensions, the total number of constraint evaluations for everychoice of the nominal design is reduced to six. Finally, the fol-lowing additional constraints are added:

(13)

(14)

Consider Fig. 7(b) again. For the chosen nominal design ,it is considered sufficient to evaluate at , becauseSNM is the worst at this point. and all other design points onor within the yield box occur because of the interdie variationin the transistor dimensions. Since also varies with thetransistor dimensions, it is not clear if the constraint in (5) can

Fig. 8. CDF plot of deviation in � across dies. � is a measure of thewithin-die variation. It is observed that nearly 99.3% of the dies have their�within �1 mV of the nominal value.

be checked only at . To check this, 15 000 points are generatedwith variation in the transistor dimensions around a nominaldesign. Around a few of these design variants, a population of5000 points with random variation in all six transistors isgenerated. The value obtained from SNM simulations atthese 5000 points matches very well with the computedusing (2) and (4). Therefore, (2) and (4) can be reliably used toevaluate at each of the 15 000 design variants. The results,shown in Fig. 8, indicate that 99.3% of the points have the SNMsigma within 1 mV of the nominal value. This impliesthat, for the interdie variants around ( , , and so on),can be assumed to be the same, but if a different nominal designsuch as is chosen [Fig. 7(b)], then the can changeappreciably and should be reevaluated.

In other words, the within-die variation remains thesame for all dies. Thus, the constraint for within-die variation,in (5), can be evaluated only at the die which constitutes theglobal worst case corner (worst ) such as the pointin Fig. 7(b) in two dimensions. The same has been observed in[35].

C. Final Optimization Problem

Fig. 9 shows the bit-cell design procedure in detail, with allthe inputs, the objective function (yield), the design constraints,and the steps to compute the design constraints.

A sequential-quadratic-programming-based optimizer [29]is used to solve the constrained optimization problem in six di-mensions. The BSIM4-based simulator with predictive 45-nmtechnology models [30], [31] has been used. However, themethod proposed in this paper can be applied to any tech-nology.

IV. RESULTS AND DISCUSSION

HSPICE template files were prepared to simulate the bit cellfor the SNM, Vtrip, read current, and leakage. The optimizationengine dynamically provides the lengths and widths of the load,driver, and access transistors to these templates for simulation toobtain updated values for the design constraints. This continuesuntil the optimizer arrives at an optimal set of the sizes for thebit-cell transistors. The following setup has been used in thispaper.

1) m , and mV[11]. Sincedifferent design constraints are evaluated at different worst



TABLE IIGENERAL-PURPOSE HIGH-PERFORMANCE DESIGN. OPTIMIZATION RESULTS FOR VARYING READ-CURRENT BOUNDS WITH ��

Fig. 9. Proposed bit-cell design procedure.

case global corners, the designer can apply a different valueof for different constraints.

2) SNM, Vtrip, read current, and leakage cause failure onlyon one side of the statistical variation. Therefore, 1.35 bit

cells per 1000 fall outside the range [13]. The chosenmathematically corresponds to a single bit-

cell failure in an array of . Typically, the largestsize of an embedded SRAM block is 256 kbits [33]; forlarger blocks, performance begins to degrade. Therefore,the chosen value of covers a wide range of embeddedmemory sizes. With redundancy, the designer can reducethe value of .

3) The transistor dimension is altered in steps of 1 nm. This isthe step size available for altering the layout geometries inthe 45-nm technology. The ranges for transistor width andlength are set to 90–500 and 45–80 nm, respectively.

4) Usually, the required residuals for the SNM and Vtrip areset to zero, and the designers attempt to obtain a value of4–5 for [11]. However, in this paper, the SNM and Vtripresiduals are selected as 15 and 25 mV, respectively, to seta higher reliability margin. Note that these are the desiredbounds for the worst case voltage-temperature corners, asin Table I.

A. General-Purpose High-Performance Design

With the previous fixed inputs, different performance (readcurrent) and leakage targets are used to design a general-purposebit cell on the high-performance moderate-leakage side. The re-sults obtained in Table II and the associated trends are analyzedto understand how the proposed method works. For a maximumbit-cell leakage target of 60 nA (the conventional leakage valuesmentioned in [36]), the read current residual is increased from30 to 45 . The corresponding transistor sizes and bit-cellareas are shown in columns 2 and 3 of Table II, respectively.As explained in Section III-A, is a measure of the max-imum intradie variation (within-die) that the design can tolerate.This number, measured at the worst case interdie variant (globalcorner), is used as a typical figure of merit in the industry for theelectrical yield (e.g., SNM yield and Vtrip yield). The outputfor the respective design constraints are shown in columns 4–8.The yield, mentioned in the last column, is obtained by runningMC simulations with 10 000 points, where Gaussian variation isapplied to the widths, lengths, and threshold voltages of all sixtransistors. The yield is equal to the percentage of bit cells thatsatisfy the desired bounds for all the design constraints.

Several interesting observations can be made from theseresults. Fig. 10(a) shows the read-current and leakage valuesat the obtained nominal designs. Any gain in performance is



Fig. 10. For varying read-current residuals: (a) Nominal read current (in microamperes) and bit-cell leakage (in nanoamperes), (b) cell ratio and � �� , and(c) nominal SNM (in millivolts).

accompanied by an increase in the nominal leakage. The initialtarget of is relaxed and is achievedwith a small area. This target allows for a low nominal leakagevalue, and the bound is not violated forup to 14.536 sigmas (column 5 of Table II) of within-dievariation due to RDF at the worst case global corner. However,as the read-current residual target is increased, the nominalbit-cell leakage also increases (approaches ), andfewer sigmas of within-die leakage variation can be toleratedby the design. A similar trend is observed for the read-current

values (column 4). For a small , the chosennominal design can afford to have both theand at a safe distance from their respectivebounds. However, with an increase in the , the

has to be designed to be closer to ,so that the value does not increase too much.Therefore, the constraint value for the read current alsoreduces progressively. The values for the four cases inTable II are as follows: 5.25, 5.18, 5.42, and 5.77 .

Fig. 10(b) shows that the cell ratio reduces with the in-creasing read-current residuals. A higher read current can beachieved by sizing up the driver and the access transistor. How-ever, driver transistors contribute heavily to total leakage. As aresult, the optimizer increases the strength of the access tran-sistor more than that of the driver. Another reason for this is thechosen layout topology, in which the driver and the access areparallel to each other. Therefore, for a chosen large driver, thewidth of the access transistor can be increased to some extentwithout impacting bit-cell area (see (1) for and ).

It is expected that reducing the cell ratio would have a detri-mental effect on the nominal SNM value. However, Fig. 10(c)shows that the SNM for the obtained design solutions degradesby only a few millivolts with the falling . The plot of theof the load transistor in Fig. 10(b) explains this observation. Astronger PMOS not only results in a stronger “1” at VR but alsoincreases the gate drive of M1 for a stronger “0.” This improvesSNM as well as read current.

Fig. 11 shows the variation in the of the bit-cell transis-tors. Because of the smaller channel area of the load transistor,the of the load has a much higher absolute value than thatof the driver or access transistors. Therefore, even though theSNM sensitivity to the variation in the load transistor is rel-atively small, a reduction in the of the load helps to reduce

[from (4)]. Hence, increasing the strength of the load tran-sistor helps to mitigate the decline in the average SNM value

Fig. 11. Variation of the � of driver, access, and load transistors (normal-ized) with increasing read-current requirement.

as well as the SNM (column 6). It is evident that the pro-posed problem formulation works well to provide robust designsolutions.

B. General-Purpose Low-Leakage Design

A general-purpose bit cell on the moderate-performance low-leakage side is also designed, and Tables III and IV summa-rize the results. The resultant transistor sizes defy the conven-tional sizing strategy for the bit cell. The low-leakage require-ment drives the optimizer to reduce thesize of the driver significantly. This, however, considerably in-creases the of the driver transistor and, thus, , whichcan potentially degrade the SNM yield unless the average SNMvalue is also raised. Consequently, the load transistor is sizedto be the largest to achieve a nominal SNM value of 152.2 mV(Table IV), which is larger than those shown in Fig. 10(c). Itis difficult to analyze all the tradeoffs and manually arrive atthese transistor sizes. These results establish the benefits of theproposed method. A generic formulation of the bit-cell designoptimization problem is presented in this paper. To take careof the specific foundry guidelines to minimize the layout-in-duced variations, different variables and additional constraintscan be introduced. For example, for the horizontal polysilicon ofthe driver and load transistor [Fig. 1(b)], the designer can keep

in order to get rid of the awkward polyshape(L-shape) which will result because of different lengths for thedriver and the load. These modifications in the problem formu-lation, to a great extent, would depend on the chosen bit-celllayout topology and the extent of available advanced lithog-raphy correction mechanisms.



Fig. 12. Yield and average values of SNM, Vtrip, read current, and bit-cell leakage obtained by MC simulations for the low-leakage bit cell. In every figure, onlyone of the bit-cell dimensions is varied while the other dimensions are kept equal to the obtained optimal value.

TABLE IIILOW-LEAKAGE BIT-CELL DESIGN RESULTS. �� .

��

TABLE IVLOW-LEAKAGE BIT-CELL DESIGN RESULTS. �� .

��

Fig. 12 shows the variation of the MC yield in the neigh-borhood of the obtained low-leakage-design solution.and refer to SNM at low-voltage high-temperature andhigh-voltage high-temperature conditions, respectively, as perTable I. Running the MC simulations to explore the entiresearch space in order to find the globally maximum yield pointis infeasible. Therefore, in Fig. 12, it is verified that the proposedoptimization approach leads to, at least, a locally maximumyield. In each figure in Fig. 12, one design parameter is varied,whereas the others are kept constant at the values mentioned inTable III. For example, Fig. 12(a) shows the MC yield and the

average values of the design constraints when is variedfrom 143 to 155 nm, while , ,

, , and . It is evidentthat the yield degrades as the design point is moved away fromthe obtained optimum.

V. CONCLUSION

In this paper, a statistical method to design the SRAM bit cellhas been proposed. The method accounts for the manufacturingvariability in the transistor dimensions and the intrinsic vari-ations due to RDF. In addition, the widths and lengths of thetransistors are chosen so as to satisfy the constraints of SNM,Vtrip, read current, leakage, and area. The developed methodis flexible, involves a small infrastructure in terms of mathemat-ical computations, and uses readily available models and tools inthe industry, so that the extent of approximation in the proposedmethod is small. Robust bit-cell designs for high-performancemoderate-leakage and moderate-performance low-leakage con-ditions have been developed and analyzed to demonstrate theworking of the proposed method. The method can be upgradedto include the impact of other sources of variability such as theoxide thickness fluctuation and line-edge roughness. It is nec-essary to evaluate how much these other sources impact thethreshold voltage of the transistor and how they can be mod-eled mathematically.

ACKNOWLEDGMENT

The authors would like to thank the Associate Editor and thereviewers who helped improve the quality of this paper. The au-thors would also like to thank Prof. P. Kumaraswamy for pro-viding the preliminary optimization code.



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Vasudha Gupta received the B.E. degree (withhonors) in electronics and communication engi-neering from the University of Delhi, Delhi, India, in2002 and the M.A.Sc. degree in electrical and com-puter engineering from the University of Waterloo,Waterloo, ON, Canada, in 2008.

She was a Senior Design Engineer with TexasInstruments Incorporated, Bangalore, India, from2002 to 2006, to develop embedded single- and mul-tiport memories and memory flows. She is currentlywith the Department of Electrical and Computer

Engineering, University of Waterloo. Her research interests include memorydesign, statistical design methodologies, and organic LED displays.



Mohab Anis (S’98–M’03) received the B.Sc. degree(with honors) in electronics and communication engi-neering from Cairo University, Cairo, Egypt, in 1997and the M.A.Sc. and Ph.D. degrees in electrical en-gineering from the University of Waterloo, Waterloo,ON, Canada, in 1999 and 2003, respectively.

He is currently an Associate Professor with theDepartment of Electrical and Computer Engineering,University of Waterloo. He has authored/coauthoredover 80 papers in international journals and confer-ences and is the author of the book Multi-Threshold

CMOS Digital Circuits—Managing Leakage Power (Kluwer, 2003). He isthe Cofounder of Spry Design Automation. He is an Associate Editor of the

Journal of Circuits, Systems and Computers, the ASP Journal of Low PowerElectronics, and VLSI Design. His research interests include integrated-circuitdesign and design automation for VLSI systems in the deep-submicrometerregime.

Dr. Anis is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS

AND SYSTEMS—II: EXPRESS BRIEFS. He is also a member of the program com-mittee for several IEEE conferences. He was the recipient of the 2009 EarlyResearch Award from Ontario’s Ministry of Research and Innovation. He wasthe recipient of the 2004 Douglas R. Colton Medal for Research Excellencein recognition of his excellence in research, leading to new understanding andnovel developments in microsystems in Canada. He won the 2002 InternationalLow-Power Design Contest.


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