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Lecture 9

Memory Devices and

Xilinx Block SelectRAM

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Objectives

Show you whats inside the box of RAM chips

Be familiar with the general design of SRAMs andDRAMs

Understand the differences between these twomemory technologies

Understand the details of the Xilinx Block SelectRAMyoull be using in the labs

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Review Questions

Describe the concepts behind memory-mapped I/O

How is memory-mapped I/O used in ECE 412?

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Review Question

ProcessorAddress

Space

I/O DeviceMemoryand ControlRegisters

1. Describe the concepts behind Memory-Mapped I/O

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Review Question

2. How is Memory mapped IO used in ECE412

The PCMCIA attribute memory and common memory ismapped into the kernel space by the meta handler invokedby the insertion of the card.

The device driver uses memory mapped IO to read attributememory for device identification, etc.

Memory mapped I/O allows device drivers to be written in Cand compiled by a standard C compiler

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Whats a RAM?

Random Access Memory

Two main types: Static RAM (SRAM) and DynamicRAM (DRAM)

Differences lie in how bits are stored

Other types: Flash RAM, SDRAM, Video RAM, FERAM

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Basic RAM ArchitectureWord Lines

Bit Lines

Bit Cell

Sense Amplifier

Address

High

Low

Data

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Static RAM (SRAM)

Word

Line

Bit

!Bit

Read: Drive word line,

sense value on bit lines

Write: Drive word line,

drive new value

(strongly) on bit lines

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Accessing a Static RAM

CE

Addr

Data

Read Write

Note: CE signal is often active-low as opposed to how shown

here. SRAMs also generally have a write enable signal

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Dynamic RAM (DRAM)

Bit Line

Word Line

Read: Drive word line,

sense value on bit line

(destroys saved value)

Write: Drive word line,

drive new value on bit

line.

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Dynamic RAM Timing (Read)

RAS

CAS

Addr

Again, control signals are often active-low

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Static vs. Dynamic RAM

Static RAM

Fast (active drive)

Less dense (4-6 transistors/bit)

Stable (holds value as long as power applied)

Dynamic RAM Slower

High density (1 transistor/bit)

Unstable (needs refresh)

Neither device holds data if power removed

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Speeding up RAMs

Making random accesses faster is hard

Time to charge word, bit lines significant and growing

Trade-off between drive of bit cell and size

Because of caches, processors tend to access blocks

of memory in consecutive order Can take advantage of this

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Page Mode/EDO RAM

Latch

Normal RAM drives many bits(row) out of array, selects few to

output.

Adding latch at row outputs allows

us to save an entire row of the RAM

Later accesses to the RAM can

eliminate the row access time,

just need column access time

Most common in DRAM, page-

mode SRAMs also exist

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Page-Mode DRAM Timing

RAS

CAS

Addr

Data

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Other RAM Types

Video RAM

Optimized for high-speed regular accesses to frame buffer SDRAM

Uses clocked organization to pipeline for speed

Flash RAM

Non-volatile (holds data without power) FERAM

Uses magnetic technology (similar to hard disk) to store data

Holds value when power off

Capacity, access time similar to RAM (hard disks take ms)

Nanotech RAMs Molecular electronics, carbon nanotubes

Nowhere near ready for prime time

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Relative Memory Sizes

SRAM is primarily afast, but expensive,solution

DRAM is primarily a

pretty fast, but cheaper(dense) solution

FERAM is a non-volatile, expensive,special solution

Block SelectRAM isembedded SRAM onour Xilinx FPGAs

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Virtex Block SelectRAM 18Kb capacity and configurable at build time to be either:

1 x 16K2 x 8K

4 x 4K

8 x 2K

16 x 1K

32 x 512

136 of these on each XC2VP30 FPGA for total of 2.4Mb total

Later we will have access to much larger DIMMs

Dual ported, can be aggregated to form larger structures

Parity bits, possible to pre-load with data in VHDL

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Generic Block

Diagrams

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Interface Signals

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Supported Configurations

Your VHDL will instantiate using

primitives

Each reference is an individual BRAM

Could form larger memory block by assembling number ofprimitives, routing delay would determine total access time.

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Physical Location

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Read and Write TimingRefer to posted application notes for exact details:

XAPP-463 (says Spartan-3 but is applicable to our parts) XAPP-130 (basic operation, but is for early smaller BRAMS)

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Next Time

Interrupts