SPX Low-level RF System WBS APS-U1.03.03.02 (SPX) WBS APS-U1.02.01.03.02 (SPX0)

SPX Low-level RF SystemWBS APS-U1.03.03.02 (SPX)

WBS APS-U1.02.01.03.02 (SPX0)

Lawrence DoolittleStaff Engineer/ScientistEngineering Division/Lawrence Berkeley National Laboratory

DOE Lehman CD-2 Review of APS-Upgrade4-6 December 2012

SPX LLRF Team

SPX LLRF R&D is a collaboration between ANL and LBNL.

The LLRF collaboration team includes

2

ANL Ned Arnold (Controls)Tim Berenc (LLRF)Tom Fors (LLRF)Frank Lenkszus (Timing, SSI)Hengjie Ma (LLRF, lead)

Focus areasLLRF System design, testingRF components development, System integration, commissioning,Inter-system development

LBNLJohn Bryd Lawrence Doolittle Gang HuangKerri CambellJames Greer

Focus areasTechnology developmentLLRF/Timing control Firmware/softwareHardware prototyping

DOE Lehman CD-2 Review of the APS Upgrade Project 4-6 December 2012

Outline

Cost, Schedule, Scope– Cost summary, – Requirement, specifications,

Design – Methods, implementation, – Interfaces, system plans

Status – Hardware/code development – Near-term tests

Summary

3


SPX LLRF Scope - Cost, purpose, and requirement Cost Summary and WBS

Purpose - stabilizes the cavity rf field to meet SPX RF error Tolerance

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Spec. Name RMS Value Bandwidth CommentAmplitude Error, common Mode < 7% 0.01Hz – 271 kHzPhase Error, common Mode < 10 deg 0.01Hz – 271 kHzAmplitude Error, diff. Mode(between two sectors)

< 1.0%<0.77%

0.01Hz – 1 kHz1 kHz – 271 kHz

Phase Error, diff. Mode(between two sectors)

<0.038 deg< 0.077 deg<0.28 deg

0.01Hz-200Hz0.01Hz –1kHz1 kHz – 271 kHz

0.038o @2.816GHz = 35 fs -> 1 m of RG214 changing 0.15oC

Table 2: Tolerances for SPX for cross-phase operation on zero crossing.

Requirement 1. Closed-loop control of cavity field rf, and phase drift calibration2. Facilitates cavity resonance control with rf data through EPICS3. Interface with I/OC host and MPS interlock


Labor Non-Labor TOTAL ($k)

U1 Short Pulse X-Ray (SPX) 2,392 815 225 655 4,087 U1 02.01.03 - SPX R&D 1,006 419 26 266 1,718

02.01.03.02 - Low Level RF (LLRF) R&D 1,006 419 26 266 1,718 U1 03.03 - SPX Production 1,385 396 199 389 2,369

03.03.02 - Low Level RF (LLRF) 1,385 396 199 389 2,369

WBS DIV OH + ANL

G&A ($k)ESCALATION

($k)

DIRECT ($k)

SPX LLRF Design – RF Stabilization Methods Use of two closed-loop controls FAST RF-FEEDBACK LOOP - targets random, wide-band perturbations,

including cavity microphonics, through fast cavity field regulation. CALIBRATION LOOP – targets slower phase drifts in rf signal channels; detects

w/ pilot-tone, feeds the drifts data back to phase set-point for correction. Facilitate cavity resonance control of Tuner Loop with RF data

5DOE Lehman CD-2 Review of the APS Upgrade Project 4-6 December 2012

CAVITY

LLRF-DIGITALLLRF DRV K

SYNC-HEAD

CAVITY PROBE W/ CAL-TONE

CAL-TONE INJECTION

REFERENCEFROM TIMING/

SYNCHRONIZATIONSYSTEM

TUNERTUNING COMMAND

KLY PWRBEAM

&MICROPHONICS

ANALOG FRONT-END

RF LOOP (GDR+SEL)

CALIBRATION LOOP

BEAM LOOP

TUNER LOOP

RF DATA

SPX

Inte

rlock

Inte

rfac

e

LLRF PERMIT

LLRF OK

QUENCH DETECT

INTERLOCK

LOOP

I/OC EPICSReal-Time Deflection

control

REFERENCE W/ CAL-TONE

CONTROL DATA

RF Stabilization Methods(1) fast RF feedback loop, model

6

H(S)R(S)(S)G1H(S)R(S)(S)G

SPX(s)(S)G

eR(S),SSSKH(S)

SK1K(S)G

c

c

b

Sτ

b

bA

ipc

asfunction transfer loop-closed a rendersit

delay term loop and cavity, klystron, ofplant a and

as expressed controller I-P awith

Standard, fast RF-feedback loop provides a wide-band control of cavity field with• Proportional Control term to cover the full-bandwidth of 0.1Hz ~ 271kHz, and• Integral control action to add emphasis on low end from DC to 1kHz, 20~40dB suppression

Proven FPGA code implementation (SNS, in operation since 2006), enhanced with• Non-I/Q sampling scheme for improved measurement/control precision• 18-bit precision of internal signal data processing• Multi-channel digital radio receiver for processing rf and calibration tone frequencies

Analysis model in continuous-time

Implementation model in discrete-timeDOE Lehman CD-2 Review of the APS Upgrade Project 4-6 December 2012

RF Stabilization Methods (2) channel calibration loop Closed-loop control of phase drift in rf signal channels by

1. Inject calibration tone in rf signal transmission channels for phase drift detection, then 2. Real-time compensate the detected drift by applying correction to phase set-point in FPGA.

Technology developed in LBNL, demonstrated at LCLS/SLAC Phase stabilization performance of 3~15 milli-deg. was demonstrated and

reported (Byrd and Huang et al., BIW’10).

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Cavity Signal

Phase Reference

Temp ControlledSync Head

Double side-bandCal Tone

drift

ADC

LLRF Receiver

FPGADigital Signal Processing

ADC

Phase drift detection algorithm

where

ΦREF,CAV-the calculated phase difference between cavity and ref.ΦRF_REF, ΦRF_CAV-measured phase of cavity and reference signalΦCAL_U_REF, ΦCAL_L_REF-measured phase of upper and lower side-band of Cal-Tone signal in Reference cable.ΦCAL_U_CAV, ΦCAL_L_CAV-measured phase of upper and lower side-band of Cal-Tone in Cavity field cable.

2

2____

____

__,

CAVlCALREFlCAL

CAVUCALREFUCAL

CAVRFREFRECAVREF


LLRF Tuner Loop Support Performs cavity resonance locating (during startup) by 2 methods:

1. frequency sweep with LLRF DDS mode (digital freq. synthesis)2. Cavity resonance tracking with LLRF digital SEL control mode

(Self-Excited-Loop).LLRF in DDS control mode LLRF in SEL control mode

Facilitates EPICS closed-loop control of cavity resonance by sending rf data to I/OC for computing cavity detune.

8DOE Lehman CD-2 Review of the APS Upgrade Project 4-6 December 2012

Output RF vector spinning governed by cavity resonance detune (actual data)

Output RF vector spinning driven by LLRF’s DDS (actual signal data)

SPX LLRF Controller – Hardware & InterfacesR&D Model for SPX0

4+2 rf inputs for CAVITY, REF, FWD, REF, KLYOUT, KLY_IN Two RF outputs for KLY_DRV, CAL_OUTOne high-speed SDI to I/OC hostOne ext. timing trigger input One internal timing trigger outputOne serial interface to phase stabilizer board One 3-bit interface with MPS interlock

Considered additions in Production Model Real-time SDI interface (RTDL)Larger 7-series FPGA Additional rf I/O channelsExpanded I/O for more SRF exception handlingOptical isolation between AFE and DFE

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RF Inputs

A/D

FPGAXilinx

7-SERIES

A/D

A/D

RTDL

I/F

RF .

. IF

REF

8-CH

,12-

bit A

DC

D/A

D/A

RF

IF

KDRV

CAL-TONE

4-CH

,12-

bit

DAC

LO

EXT. TRIG. ININT. TRIG OUT

MPS I/F

RTDL toI/OC

GPIOs

SDI to Timing

RF Outputs

LO/CLK GEN.

A/D

A/D

A/D

CAV

FWD

REV

KOUT

KIN

EXP.

I/O

A/DSPARE IF IN

D/ASPARE IF OUT


LLRF System – Integration with Controls vs. data I/O The digital LLRF merges with SPX Controls as a device of EPICS I/OC

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LLRF DRV wfm

FWD PWR wfm

Cav. Field wfm

Phase Ref. wfm

High-level controls of LLRF via. writing control data to LLRF registers in FPGA

High-level controls read back rf and status data for analysis and uses in other processes

Other signals


LLRF System – Site installation planwith 8 LLRF controllers, 2 combined sync-heads, and Real-time data links

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x4 in Sector-5 (x2 in SPX0)

x4 in Sector-7 (absent in SPX0)

LLR

F C

ON

TRO

LLER

#1,

2,3,

4

TIMING/SYNCH.SYSTEM

LLRF DRV OUT KLYSTRON DRV

CALIBRATION -TONE OUT

RF MONITOR

APS RF REF/SYNC

PHASE REFERENCE IN

CAVITY FIELD IN

RTDL

I/F

RTDL

RF I/

O

TIMINGTRIG

SPX RF PHASE REF for Sector 5

SYN

C-HE

AD, #

1~4

LLR

F C

ON

TRO

LLER

#5,

6,7,

8

CAVITY #1,2,3,4

CAVITY #5,6,7,8

LLRF DRV OUTKLYSTRON DRV

CALIBRATION -TONE OUT

RF MONITOR

PHASE REFERENCE IN

CAVITY FIELD INRTDL

I/F

RTDL

RF I/

O

TIMINGTRIG

SYN

C-HE

AD, #

5~8 LO / CLK

SPX RF PHASE REF. for Sector 7

LO / CLK

KLY #1,2,3,4

KLY #5,6,7,8

TUNNEL

INTLK

INTLK


Status – development is actively taking place in both labs. Key component - Cavity field controller base model has been designed, and all four

units needed for SPX0 have been constructed and tested, (one has been delivered for test with SRF at ATLAS)

Supporting components – LLRF Frequency generation chassis, cavity emulator have been designed, constructed, and delivered

Two code versions have been developed and released 1st of the two core-functions – multi-channel LLRF digital transceiver with RF-Feedback

Control, released and tested in October, 2011. 2nd core-function - phase drift detection/correction, finished in July 2012, currently under

tests.

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FWD PWR


Status – code development, management Currently using two source-code version-controlled repositories,

both shared with LBNL's APEX project. Gateware:

369 commits from 3 authors since June 2011 260 files (158 Verilog), 17163 lines, large number of unit and system tests 81 files, 5726 lines specific to SPX 35 files, 2332 lines specific to APEX

Software (USB communications up through EPICS driver and test GUI): 339 commits from 4 authors since April 2011 600 files (some duplicate), 60877 lines 25 files, 798 lines specific to SPX 61 files, 2175 lines specific to APEX

(Both code bases have much longer histories, these dates just correspondto their entry into our version control system (git))

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Status – hardware development Hardware constructed (includes spares and LBNL development copies):

– 4 LLRF/Phase Control chassis– 2 LO/Frequency Generation chassis– 2 Cavity Emulator chassis– Documentation generated at LBNL and provided to ANL includes– Chassis schematics, BOM, and construction packets for five key circuit boards

(LLRF4 and Expansion board, up and down converter, and LO driver)

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Status – Core component: LLRF-Timing controller unit Construction of LLRF-Timing controller chassis with both LLRF

digital transceiver and Timing transceiver board integrated.

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FWD PWR

LLRF DRV

LO Dist. module

Fiber Optics Beat-Tone Module

Expansion Board(Sync-head Monitor)

LLRF Digital Transceiver Board

Timing Digital Transceiver Board


Status – performance tests: RF feedback loop (1) Initial result of rf input channel phase noise floor measurement

(AFE+DFE, with 2011 FPFA code version)Differential between 2 input channels

• <0.002 deg, integrated over 0.1Hz~1kHz; • <0.007 deg, integrated over 0.1Hz~100 kHz

Single channel relative to reference clock: • ~0.002 deg, integrated over 0.1Hz~1kHz; • <0.006 deg, integrated over 0.1Hz~100 kHz

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• This result indicates that LLRF electronics has a noise floor low enough to allow rf phase measurement resolution down to milli-degree level – a necessary condition for achieving a control precision within the total error budget

• An important basis for using LLRF measurement data for subsequent system characterization.


Status – performance tests: RF feedback loop (2)

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Total LLRF system noise floor level measured by looping LLRF drive back to cavity input ch. (thus the measured phase noise is relative to reference/clock)

Measurement BW: 1Hz~46kHz, @ 2/3 F-S level, no klystron– 10.5 mdeg rms in open-loop– 4.5 mdeg rms in closed-loop mode, no cavity, loop gain~=1

Phase noise spectra, open-loop Phase noise spectra, closed-loop


Status – performance tests: RF feedback loop (3)

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Bench measurement of differential phase error in closed-loop control Two LLRF controllers drive two cavity emulators, both run on a common clock and LO, thus only the differential error by the two LLRF controllers is seen.Measured ~6 mdeg rms differential phase error integrated over 0.1Hz~3kHz, and ~20 mdeg to 1MHz.


Status – performance tests with HLRF klystron (1)

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HLRF Klystron


LLRF system test rack

In preparation for coming-up Horizontal Cold Tuner Test at ATLAS, a complete LLRF test system rack was built, and tested with high-power RF klystron in EAA area.

Exercised GDR open-loop, closed-loop control with SRF cavity emulator, demonstrated a good control stability.

Effectiveness of rf loop in suppressing the phase noise of klystron HV power supply was also demonstrated (results in following slides).


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Spectrum and accumulated value of cavity rf phase noise when LLRF is in OPEN-LOOP control mode

Total accumulative phase noise of klystron and LLRF with LLRF in open-loop mode. Notice the klystron HV power supply contribution at 360Hz . (in-band measurement)

Power spectrum density of the total phase noise of klystron and LLRF with LLRF in open-loop mode. Note the 360Hz noise line


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Spectrum and accumulated value of cavity rf phase noise when LLRF is in CLOSED-LOOP control mode

Total accumulative phase noise of klystron and LLRF with LLRF in CLOSED-LOOP mode. Notice the 360Hz klystron HV noise has been suppressed. (in-band measurement)

Power spectrum density of the total phase noise of klystron and LLRF with LLRF in CLOSED-LOOP mode. Notice the scale of Y-axis has been down shifted by ~40dB.

Status – performance tests: channel calibration loop

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FPGA Code for calibration loop was completed in July 2012, and shortly after Function tests with simulated cable drifts were exercised at LBNL for verification Elaborated tests in ANL will follow

This exercise proved the calibration loop correctly detect and identify the phase drifts in the cables, and compensate them by applying the corrections to the phase set-point.

CAVITY-RF REF-RFCAVITY-CAL-LDRV-RFPHASE_REF

FINAL ERR=CAV-(PHASE_REF+SP)

Cav. Cable drift

Cal-tone Cable drift

Ref Cable drift

Set-point change


Technical Risks & Mitigation

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Overall, technical risk of LLRF area is low, and so in the costs and schedule, due to current development status we have, and to the fact that the key technology of digital LLRF control and phase drift calibration from LBNL is proven, and demonstrated (SNS, SLAC).

Concerns of unknown levels of perturbations • environment EMI, • beam loading, • Cavity microphonics (including helium pressure, vibrations, tuner jolt)

Mitigation - Collect data during development, work with the related-system developers to minimize these perturbations as much as possible.


SPX Low Level Radio Frequency Scope and WBSU1.02.01.03 & U1.03.03

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Labor Non-Labor TOTAL ($k)

U1 Short Pulse X-Ray (SPX) 2,392 815 225 655 4,087 U1 02.01.03 - SPX R&D 1,006 419 26 266 1,718

02.01.03.02 - Low Level RF (LLRF) R&D 1,006 419 26 266 1,718 02.01.03.02 - ACWP (includes ANL and LBNL) 255 86 - 61 402 02.01.03.02.02 - Controller 248 246 14 70 577 02.01.03.02.03 - Analog Front End (AFE) 122 25 1 34 181 02.01.03.02.04 - Control System Modeling 23 - - 5 28 02.01.03.02.05 - Cable Plant 95 58 2 32 188 02.01.03.02.06 - Slow Tuner Drive Electronics 99 4 2 26 132 02.01.03.02.08 - General LLRF R&D System Design 90 - 1 20 111 02.01.03.02.09 - Support SPX R&D Storage Ring Test 74 - 6 19 99

U1 03.03 - SPX Production 1,385 396 199 389 2,369 03.03.02 - Low Level RF (LLRF) 1,385 396 199 389 2,369 03.03.02 - ACWP 48 0 - 11 59 03.03.02.01 - LLRF Controller 426 62 48 111 647 03.03.02.02 - Analog Front End 128 148 32 41 348 03.03.02.03 - Slow Tuner Driver 343 107 58 101 608 03.03.02.05 - Cable Plant 109 36 15 38 199 03.03.02.06 - Storage Ring Phase Shifter 72 6 8 20 108 03.03.02.07 - General LLRF Production System Design 124 36 11 30 202 03.03.02.08 - Support SPX Storage Ring Test 135 - 26 37 197

WBS DIV OH + ANL

G&A ($k)ESCALATION

($k)

DIRECT ($k)

Director's CD-2 Review of the Advanced Photon Source Upgrade Project 11-13 September 2012

SPX Low Level Radio Frequency Obligation Profile U1.02.01.03 & U1.03.03

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SPX R&D and Production Milestones U1.02.01.03 & U1.03.03


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u START: Preliminary Design - SPX0 4/10

u START: Preliminary Design - SPX 2/12

u COMP: PDR - SPX0 7/12

u COMP: PDR - SPX 1/13

u SHIP: SPX0 Cryomodule to ANL 4/14

u COMP: SPX0 Cryomodule Test 6/14

u START: SPX0 Installation 8/14 (Note: Aug-14 Maintenance Shutdown)

u COMP: SPX0 Installation 10/14

u AVAIL: SPX0 Ready for Operation 1/15

u START: Final Design - SPX 6/14

u COMP: Final Design 9/15

u START: Major Procurement 10/15

u AWARD: Cryoplant Contract 10/15

u START: Cryoplant Installation 9/17

u COMP: Cryoplant 3/18

SHIP: Cryomodule #1 to ANL 10/17 uSTART: Cryom #1 Installation 5/18 u

COMP: Cryom #1 Installation 6/18 uAVAIL: Cryomodule #1 Ready for Operation 8/18 u

SHIP: Cryomodule #2 to ANL 8/18 uSTART: Cryom #2 Installation 12/18 u

COMP: Cryom #2 Installation 1/19 uAVAIL: Cryomodule #2 Ready for Operation 3/19 u

SPX SYSTEM

FY18 FY19 FY20FY10 FY11 FY12 FY13 FY14 FY15 FY16 FY17

SPX Low Level Radio Frequency Milestones U1.02.01.03 & U1.03.03


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q NEED: LLRF Controls for Single Cavity Test - SPX0 9/12

q AVAIL: AFE for Single Cavity Testing at ATLAS - SPX 0 9/12

q AVAIL: AFE for Two Cavity Testing at ATLAS - SPX0 9/13

q AVAIL: LLRF Controller for Two Cavity Testing at ATLAS - SPX0 9/13

q AVAIL: Slow Tuner Drive Electronics Ready for Installation - SPX0 3/14

q COMP: LLRF R&D 11/14

q START: Final Design 6/14

q AVAIL: LLRF Controller 6/17

LLRF

FY16 FY17 FY18 FY19 FY20FY10 FY11 FY12 FY13 FY14 FY15

SPX Low Level Radio Frequency Summary Schedule U1.02.01.03 & U1.03.03

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SPX Low Level Radio Frequency BOE Contingency U1.02.01.03 & U1.03.03

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Summary

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The total cost for LLRF is $3,982k. SPX LLRF R&D is progressing on schedule. LLRF controller hardware has been designed, and all four

units have been constructed. Two LLRF code versions are developed and delivered to

support near-term tests: rf-loop/calibration-Loop/Self-excited-loop.

Test results of current stage show llrf phase errors within tolerance.

Supporting documents (ESD, ICD) completed. LLRF test stand for supporting SRF Horizontal Tuner Test at

ATLAS has been built, and deployed at ATLAS.

We are ready for CD-2. Thank youDOE Lehman CD-2 Review of the APS Upgrade Project 4-6 December 2012

SPX Low-level RF System WBS APS-U1.03.03.02 (SPX) WBS APS-U1.02.01.03.02 (SPX0)

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Transcript of SPX Low-level RF System WBS APS-U1.03.03.02 (SPX) WBS APS-U1.02.01.03.02 (SPX0)