Spring 2006 1 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Advanced...
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Transcript of Spring 2006 1 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Advanced...
Spring 2006
Lillevik 437s06-l9 1University of Portland School of Engineering
EE 437
Advanced ComputerArchitecture
Lecture 9
DMA controller design
Spring 2006
Lillevik 437s06-l9 2University of Portland School of Engineering
EE 437
Direct memory access
• Objective: avoid the disadvantages of programmed I/O (eliminate the busy loop)
• Technique– CPU writes to special controller (word count
and memory address)– CPU tells controller to start data transfers– CPU continues with other computing– CPU responds to interrupt from controller: ISR
Spring 2006
Lillevik 437s06-l9 3University of Portland School of Engineering
EE 437
Role of DMA controller
• Accept initialization data from CPU
• Access I/O device and drive bus (master)– Input: read I/O device and write data to
memory– Output: read memory data and write to I/O
device
• Interrupt CPU when transfer complete
Spring 2006
Lillevik 437s06-l9 4University of Portland School of Engineering
EE 437
DMA hardware view
n words n words
adr X
adr X+(n-1)
Memory
I/O device
buffer
System bus adr 0
adr n-1
Spring 2006
Lillevik 437s06-l9 5University of Portland School of Engineering
EE 437
DMA controller architecture
Counts up from zero
Counts down to zero Preset counter
Word
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
5 key blocks
Spring 2006
Lillevik 437s06-l9 6University of Portland School of Engineering
EE 437
DMA initialization instructions?
1. Write start address
2. Write word count (or end address)
3. Write “go” command
Each write is to a specific DMA controller port address
Spring 2006
Lillevik 437s06-l9 7University of Portland School of Engineering
EE 437
DMA controller initialization 1
Start address
Word
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
Spring 2006
Lillevik 437s06-l9 8University of Portland School of Engineering
EE 437
DMA controller initialization 2
Word count
Word
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
Spring 2006
Lillevik 437s06-l9 9University of Portland School of Engineering
EE 437
DMA controller initialization 3
StartWord
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
Spring 2006
Lillevik 437s06-l9 10University of Portland School of Engineering
EE 437
DMA controller driving bus
• Must enable all tri-state drivers: D, A, and C buses
• D bus sources the data, memory agent sinks the data
• A bus contains the memory address decoded by memory agent
• C bus contains the memory write code
Spring 2006
Lillevik 437s06-l9 11University of Portland School of Engineering
EE 437
DMA controller driving bus
Memory write
Word
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
Memory adr
Memory data
Spring 2006
Lillevik 437s06-l9 12University of Portland School of Engineering
EE 437
Hard drive DMA
• Assumptions– Operation: Input, or read disk, or read file– HD buffer: represent with a ROM
• Initialization commands– Port 1: start address– Port 2: word count– Port 4: start
• Design contains 5 sections
Project 5
Spring 2006
Lillevik 437s06-l9 13University of Portland School of Engineering
EE 437
Buffer address section
• Objective: create an address for the HD buffer (ROM)
• Role: zero counter, count up
Spring 2006
Lillevik 437s06-l9 14University of Portland School of Engineering
EE 437
Buffer address block?
Spring 2006
Lillevik 437s06-l9 15University of Portland School of Engineering
EE 437
Data buffer section
• Objective: provide data for bus transfers
• Role: drive the data bus when enabled and addressed
Spring 2006
Lillevik 437s06-l9 16University of Portland School of Engineering
EE 437
Data buffer block?
Spring 2006
Lillevik 437s06-l9 17University of Portland School of Engineering
EE 437
Word count section
• Objective: keep track of how many data words have been transferred
• Role: preset to some number, then count down to zero, indicate zero condition
Spring 2006
Lillevik 437s06-l9 18University of Portland School of Engineering
EE 437
Word count block?
Spring 2006
Lillevik 437s06-l9 19University of Portland School of Engineering
EE 437
Memory address section
• Objective: provide address for bus transfer
• Role: accept start address, then count up, drive the address bus
Spring 2006
Lillevik 437s06-l9 20University of Portland School of Engineering
EE 437
Memory address block?
Spring 2006
Lillevik 437s06-l9 21University of Portland School of Engineering
EE 437
Updated block diagram
Word
Count
Data
Buffer
Memory
Address
Buffer
Address
Control
D
A
C
Xcvr
Xcvr
Xcvr
Port1Port2
BAclr
BAinc
WCdec
MAincZero
Ben
Ben
Ben
Cou
nt
Spring 2006
Lillevik 437s06-l9 22University of Portland School of Engineering
EE 437
Control section
• Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done
• Role– Contains three subsections: decoder, counters,
bus I/F– Bus I/F a FSM similar to CPU model
Spring 2006
Lillevik 437s06-l9 23University of Portland School of Engineering
EE 437
Control section block 1?Decode
Spring 2006
Lillevik 437s06-l9 24University of Portland School of Engineering
EE 437
Control section block 2?Counters
Spring 2006
Lillevik 437s06-l9 25University of Portland School of Engineering
EE 437
Control section block 3?Bus interface
Spring 2006
Lillevik 437s06-l9 26University of Portland School of Engineering
EE 437
Spring 2006
Lillevik 437s06-l9 27University of Portland School of Engineering
EE 437
Buffer address block?
Buffer
Address
BAclr
BAinc
BAdr
Spring 2006
Lillevik 437s06-l9 28University of Portland School of Engineering
EE 437
Data buffer block?
Data
Buffer
(ROM)
Data
Ben
BAdr
Assume ROM outputs are tri-state
Spring 2006
Lillevik 437s06-l9 29University of Portland School of Engineering
EE 437
Word count block?
Word
Count
Data
WCload
WCdecZero
Spring 2006
Lillevik 437s06-l9 30University of Portland School of Engineering
EE 437
Memory address block?
Memory
AddressA
Assume MA outputs are tri-state
D
MAload
MAinc
Ben
Spring 2006
Lillevik 437s06-l9 31University of Portland School of Engineering
EE 437
Control section block 1?
Decode
LogicC
A Port1 (MAload)
Port2 (WCload)
Port4 (Start)
Decode
Spring 2006
Lillevik 437s06-l9 32University of Portland School of Engineering
EE 437
Control section block 2?
Enables
Start
BAclr
BAinc
WCdec
MAincZero
Counters
One signal?
Spring 2006
Lillevik 437s06-l9 33University of Portland School of Engineering
EE 437
Control section block 3?
Bus
I/F
Bgnt
Breq
Int
BenAck
Inta C
Must drive C bus with memory write instruction
Bus interface