SPOC™+ 12V BTS54220-LBB Sheets/Infineon PDFs/BTS54220-LBB.pdf · MIPI™ of MIPI Alliance, Inc....

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Data Sheet Rev. 2.1, 2014-12-05

BTS54220-LBBSPI Power Controller

SPOC™+ 12V

BTS54220-LBB

Data Sheet 2 Rev. 2.1, 2014-12-05

Trademarks of Infineon Technologies AGAURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™, thinQ!™,TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.

Other TrademarksAdvance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,PRIMECELL™, REALVIEW™, THUMB™, μVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSARdevelopment partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ ofHilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared DataAssociation Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ ofMathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor GraphicsCorporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo YudenCo. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ ofDiodes Zetex Limited.Last Trademarks Update 2014-03-27

Revision HistoryPage or Item Subjects (major changes since previous revision)Rev. 2.1, 2014-12-05All Data Sheet released

BTS54220-LBB

Table of Contents

Data Sheet 3 Rev. 2.1, 2014-12-05

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Pin Assignment BTS54220-LBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.1 PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.2 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.1.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.2 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.3 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.4 Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.1.5 Operative mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.1.6 Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2.1 Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.1 Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.3 Input Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.4 Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.4.1 Bulb and LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.4.2 Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.4.3 Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.4.4 Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.4 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.5 Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.6 Loss of VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428.1 Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table of Contents

BTS54220-LBB

Table of Contents

Data Sheet 4 Rev. 2.1, 2014-12-05

8.2 Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.1 Current Sense Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.2 Current Sense Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.3 Open Load at ON Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458.3 Switch Bypass Monitor Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458.4 Gate Back Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569.6 SPI Diagnosis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599.6.1 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599.6.2 Errors Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609.6.3 Warnings Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609.7 SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.7.1 Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.7.2 Input Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.7.3 Swap Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.7.4 LED Mode Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.7.5 Gate Back Regulation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.7.6 Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.7.7 Diagnosis Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639.7.8 Configuration Register Bit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11 Package Outlines BTS54220-LBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

BTS54220-LBB

List of Figures

Data Sheet 5 Rev. 2.1, 2014-12-05

Figure 1 Block Diagram BTS54220-LBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 2 Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 3 Pin Configuration TSON-24-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 4 2s2p PCB Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 5 PC Board for Thermal Simulation with 600 mm² Cooling Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 6 PC Board for Thermal Simulation with 2s2p Cooling Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 7 Solder Area / Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 8 Typical Thermal Impedance. PCB setup according Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 9 Typical Thermal Resistance. PCB setup 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 10 Operation Mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 11 Limp Home Activation as function of VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 12 VS undervoltage behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 13 RDS(ON) variation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 14 Input Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 15 Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 16 Switching a Load (resistive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 17 Typical Current Limitation variation according to VDS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 18 Dynamic Temperature Sensor Operations - Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 19 Dynamic and Absolute Temperature Sensor Operations - Overload Condition . . . . . . . . . . . . . . . 38Figure 20 Different counter reset according to HWCR.RCR bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 21 Block Diagram: Diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 22 Current Sense Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 23 Current Sense Multiplexer Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 24 Current Sense Ratio in Open Load at ON condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 25 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 26 Combinatorial Logic for TER Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 27 Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 28 Data Transfer in Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 29 Timing Diagram SPI Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 30 Relationship between SI and SO during SPI communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 31 Register content sent back to µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 32 BTS54220-LBB response after an error in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 33 BTS54220-LBB response after coming out of Power-On reset at VDD . . . . . . . . . . . . . . . . . . . . . . 57Figure 34 BTS54220-LBB response in case of a negative battery voltage transient . . . . . . . . . . . . . . . . . . . 57Figure 35 Application Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 36 TSON-24-1 Package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 37 TSON-24 Package pads and stencil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

List of Figures

BTS54220-LBB

List of Tables

Data Sheet 6 Rev. 2.1, 2014-12-05

Table 1 Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 4 Device capability as function of VS and VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 5 Device function in relation to operation modes, VS and VDD voltages . . . . . . . . . . . . . . . . . . . . . . 22Table 6 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 7 Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 8 Electrical Characteristics Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 9 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 10 Electrical Characteristics Diagnosis kILIS 9 mΩ ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 11 Electrical Characteristics Diagnosis kILIS 27 mΩ ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 12 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 14 SPI Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 15 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 16 Suggested Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

List of Tables

TSON-24-1

Type Package MarkingBTS54220-LBB TSON-24-1 BTS54220-LBB

Data Sheet 7 Rev. 2.1, 2014-12-05

BTS54220-LBB

1 Overview

Features• 8-bit serial peripheral interface (daisy chain capable SPI) for control

and diagnosis• CMOS compatible parallel input pins for four channels• Selectable AND- / OR-combination for parallel inputs (PWM control)• Load type configuration via SPI (bulbs or LEDs) for optimized load

control• Very low stand-by current• Device ground independent from load ground• Green Product (RoHS-Compliant)• AEC Qualified

DescriptionThe BTS54220-LBB is a four channel high-side smart power switch in TSON-24-1 package providing embeddedprotective functions. It is specially designed to control standard exterior lighting in automotive applications. In orderto use the same hardware, the device can be configured to bulb or LED mode. As a result, both load types areoptimized in terms of switching and diagnosis behavior.It is designed to drive exterior lamps up to 65 W and 27 W, HIDL or the equivalent LED light.

Configuration and status diagnosis are done via SPI. An 8-bit serial peripheral interface (SPI) is used. The SPI isdaisy chain capable.

Table 1 Product SummaryOperating Voltage Power Switch VS 5.5 … 28 VLogic Supply Voltage VDD 3.8 … 5.5 VOver Voltage Protection VS(AZ,min) 42 VMaximum Stand-By Current at 25 °C IVS(STB) 1 µAMaximum ON State Resistance at Tj = 150 °C9 mΩ channels (Channel 1, 4)

RDS(ON,max) 18.2 mΩ

Maximum ON State Resistance at Tj = 150 °C27 mΩ channels (Channel 2, 3)

RDS(ON,max) 55 mΩ

SPI Access Frequency fSCLK(max) 3 MHz

BTS54220-LBB

Overview

Data Sheet 8 Rev. 2.1, 2014-12-05

The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can beenabled and disabled via SPI commands. An over temperature flag per output is provided in the SPI diagnosisword. A multiplexed switch bypass monitor provides short-circuit to VS diagnosis.27 mΩ channels can be configured to bulb or LED mode for maximum flexibility.The BTS54220-LBB provides a fail-safe feature via a Limp Home Input (LHI) pin and direct Input pins.The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device ismonolithically integrated in SMART technology.

Applications• High-side power switch for 12 V in automotive or industrial applications such as lighting, heating, motor driving,

energy and power distribution• Especially designed for standard exterior lighting like high beam, low beam, position light, tail light, brake light,

parking light, license plate light, indicators and equivalent in the LED technology • Replaces electromechanical relays, fuses and discrete circuits

Protective Functions• Reverse battery protection with external components• Short circuit to ground protection• Stable behavior at under voltage• Current limitation• Absolute and dynamic temperature sensor• Thermal shutdown with latch after a limited amount of retries• Overvoltage protection• Loss of ground protection• Electrostatic discharge protection (ESD)

Diagnostic Functions• Multiplexed proportional load current sense signal (IS)• Enable function for current sense signal configurable via SPI• High accuracy of current sense signal at wide load current range• Current sense ratio (kILIS) configurable for LEDs or bulbs• Very fast diagnosis in LED mode • Feedback on over temperature via SPI• Short circuit to VS detection• Monitoring of Input pins status

Application Specific Functions• Fail-safe activation via LHI pin and control via input pins• Enhanced electromagnetic compatibility (EMC) for bulbs as well as LEDs• LED mode selection available• SPI with daisy chain capability• Switch bypass monitoring for detecting short circuit to VS

BTS54220-LBB

Block Diagram

Data Sheet 9 Rev. 2.1, 2014-12-05

2 Block Diagram

Figure 1 Block Diagram BTS54220-LBB

432channel 1

power supply

driver logic

gate control &

charge pump

clamp for inductive

load

load current limitationload current

sense

temperature sensor

ESD protection

GND

SOSCLK

SI

CS

LHI

VS

OUT4

OUT3OUT2

OUT1

IN2IN3

IN1

IS

VDD

IN4

limp home control

SPI

current sense multiplexer

switch bypass monitor

LED mode control

BlockDiagram_4chnoED.emf

BTS54220-LBB

Block Diagram

Data Sheet 10 Rev. 2.1, 2014-12-05

2.1 TermsFigure 2 shows all terms used in this data sheet, with associated convention for positive values.

Figure 2 Voltage and Current Definition

In all tables of electrical characteristics, symbols related to channels without channel number are valid for eachchannel separately (e.g. VDS specification is valid for VDS1 … VDS4).All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.STB) with the exception of the bits inthe Diagnosis frames which are marked only with PARAMETER (e.g. VSMON).

IDD

VDD

VSO

VIN2

ISI

ICS

VS

I IS

IS

VDD

SO

SI

CS

IS

VS

VSI

VCS

VSCLK

VIN 1

IIN1

IN1

IN2

ISCLK

SCLK

VIS

GND

IGND

VLHI

ILHI

LHI

OUT1IL1

OUT2IL2

OUT3IL3

OUT4IL4

VOUT4

VOUT3

VDS4

VDS3

VOUT2

VOUT1

VDS2

VDS1

ISO

IIN2

V IN3

IIN3

IN3

VIN4

IIN4

IN4

Terms_4chnoED.emf

BTS54220-LBB

Pin Configuration

Data Sheet 11 Rev. 2.1, 2014-12-05

3 Pin Configuration

3.1 Pin Assignment BTS54220-LBB

Figure 3 Pin Configuration TSON-24-1

(top view )

OUT2OUT2OUT3

24

23

22

2120

1

2

3

45

67

8

1918

OUT1OUT1OUT1OUT1

OUT317

16

1514

13

9

1011

12

OUT4OUT4OUT4OUT4

CSSCLK

SISO

LHI

IS

25VS

exposed pad (bottom )

VDDGND

IN2IN1

IN3IN4

Pinout_220noED.emf

BTS54220-LBB

Pin Configuration

Data Sheet 12 Rev. 2.1, 2014-12-05

3.2 Pin Definitions and Functions

Pin Symbol I/O FunctionPower Supply Pins25 VS – Positive power supply for high-side power switch1 GND – Ground connection2 VDD – Logic supply (5 V)SPI & Diagnosis Pins3 SO O Serial output of SPI interface4 SI I Serial input of SPI interface (“high” active)5 SCLK I Serial clock of SPI interface (“high” active)6 CS I Chip select of SPI interface (“low” active); Integrated pull up to VDD12 IS O Current sense output signalLimp Home Input Pin (integrated pull-down, leave unused Limp Home Input pin unconnected)7 LHI I Limp home activation signal (“high” active)Parallel Input Pins (integrated pull-down, leave unused pins unconnected)8 IN1 I Input signal of channel 1 (“high” active)9 IN2 I Input signal of channel 2 (“high” active)10 IN3 I Input signal of channel 3 (“high” active)11 IN4 I Input signal of channel 4 (“high” active)Power Output Pins21, 22, 23, 24 1)

1) All outputs pins of each channel must be connected together on the PCB. All pins of an output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow.

OUT1 O Protected high-side power output of channel 119, 20 1) OUT2 O Protected high-side power output of channel 217, 18 1) OUT3 O Protected high-side power output of channel 313, 14, 15, 16 1) OUT4 O Protected high-side power output of channel 4

BTS54220-LBB

Electrical Characteristics

Data Sheet 13 Rev. 2.1, 2014-12-05

4 Electrical Characteristics

4.1 Absolute Maximum RatingsTj = -40 to +150 °C; all voltages with respect to groundTypical resistive loads connected to the outputs (unless otherwise specified):9 mΩ channels: RL = 2.2 Ω27 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”)

Table 2 Absolute Maximum Ratings1)

Parameter Symbol Values Unit Note / Test Condition

NumberMin. Typ. Max.

Supply VoltagePower supply voltage VS -0.3 28 V – P_4.1.1Logic supply voltage VDD -0.3 5.5 V – P_4.1.2Reverse polarity voltage -VS(rev) – 16 V 2)

TjStart = 25 °C t ≤ 2 min.See Chapter 10 for setup

P_4.1.3

Supply voltage for short circuit protection (single pulse)

VS(SC) 0 28 V 3)

RECU = 20 mΩ l = 0 or 5 m RCable = 16 mΩ/mLCable = 1 µH/m

P_4.1.5

Permanent short circuit number channel activationsAll channels

nRSC1 - 100 k 3) VDD = 5 V tON = 300 ms

P_4.1.6

Voltage at power transistor VDS – 42 V – P_4.1.8Supply voltage for load dump protection

VS(LD) – 42 V 4)

RI = 2 Ω t = 400 ms

P_4.1.9

Current through ground pin IGND -100 25 mA t ≤ 2 min. P_4.1.10Current through VDD pin IDD -25 30 mA t ≤ 2 min. P_4.1.11Power StagesLoad current |IL| – IL(LIM) A 5) P_4.1.12Maximum energy dissipationsingle pulse - IL(nom)9 mΩ ch.

EAS – 145 mJ 6)

Tj(0) = 150 °C IL(0) = IL(nom) = P_6.6.15

P_4.1.13

Maximum energy dissipationsingle pulse - IL(nom)27 mΩ ch.

EAS – 135 mJ 6)

Tj(0) = 150 °C IL(0) = IL(nom) = P_6.6.16

P_4.1.14

BTS54220-LBB


Data Sheet 14 Rev. 2.1, 2014-12-05

Diagnosis PinVoltage at sense pin IS VIS -0.3 VS V – P_4.1.24Current through sense pin IS IIS -10 40 mA t ≤ 2 min. P_4.1.25Input PinsVoltage at input pins VIN -0.3 6.0 V – P_4.1.26Current through input pins IIN -0.75 0.75 mA – P_4.1.27Current through input pins IIN -2.0 10 mA t ≤ 2 min. P_4.1.28SPI PinsVoltage at chip select pin VCS -0.3 6.0 V – P_4.1.29Current through chip select pin ICS -0.75 0.75 mA – P_4.1.30Current through chip select pin ICS -2.0 10 mA t ≤ 2 min. P_4.1.31Voltage at serial input pin VSI -0.3 6.0 V – P_4.1.32Current through serial input pin ISI -0.75 0.75 mA – P_4.1.33Current through serial input pin ISI -2.0 10 mA t ≤ 2 min. P_4.1.34Voltage at serial clock pin VSCLK -0.3 6.0 V – P_4.1.35Current through serial clock pin ISCLK -0.75 0.75 mA – P_4.1.36Current through serial clock pin ISCLK -2.0 10 mA t ≤ 2 min. P_4.1.37Current through serial output pin SO ISO -0.75 0.75 mA – P_4.1.38Current through serial output pin SO ISO -10 2.0 mA t ≤ 2 min. P_4.1.39Limp Home Input PinVoltage at Limp Home Input pin VLHI -0.3 6.0 V – P_4.1.40Current through Limp Home Input pin ILHI -0.75 0.75 mA – P_4.1.41Current through Limp Home Input pin ILHI -2.0 10 mA t ≤ 2 min. P_4.1.42TemperaturesJunction temperature Tj -40 150 °C – P_4.1.45Dynamic temperature increase while switching

∆Tj – 60 K – P_4.1.46

Storage temperature Tstg -55 150 °C – P_4.1.47ESD SusceptibilityESD susceptibility HBMOUT pins vs. VS

VESD -4 4 kV 7) HBM

P_4.1.48

ESD susceptibility HBMall pins vs. VDD

VESD -1.5 1.5 kV 7) HBM

P_4.1.54

ESD susceptibility HBMother pins vs. GND incl. OUT pins vs. GND

VESD -2 2 kV 7) HBM

P_4.1.49

Table 2 Absolute Maximum Ratings1) (cont’d)



BTS54220-LBB


Data Sheet 15 Rev. 2.1, 2014-12-05

Notes1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

ESD Resistivity to GND VESD-500 500

V 8) CDM

P_4.1.51

ESD Resistivity Pin 1, 12, 13, 24 (corner pins) to GND

VESD1, 12,

13, 24 -750 750V 8)

CDMP_4.1.52

1) Not subject to production test, specified by design.2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip and

package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer.

3) EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability at the end of this document.

4) RI is the internal resistance of the load dump pulse generator.5) Current limitation is a protection feature. Protection features are not designed for continuous repetitive operation.6) Pulse shape represents inductive switch OFF: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse

7) ESD resistivity, HBM according to ANSI/ESDA/JEDEC JS-001-20108) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1

Table 2 Absolute Maximum Ratings1) (cont’d)



BTS54220-LBB


Data Sheet 16 Rev. 2.1, 2014-12-05

4.2 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org.

4.2.1 PCB Setup

Figure 4 2s2p PCB Cross Section

Table 3 Thermal ResistanceParameter Symbol Values Unit Note / Test Condition Number

Min. Typ. Max.Junction to Soldering Point RthJSP – 2 – K/W 1)

Tj(0) = 105 °Cmeasured to pin 25

1) Not subject to production test, specified by design.

P_4.2.1

Junction to Ambient RthJA – 21 – K/W 1)2)

Tj(0) = 105 °C

2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer.

P_4.2.2

1.5mm

70µm

35µm

0.3mm Zth_PCB_2s2p.emf

http://www.jedec.org

BTS54220-LBB


Data Sheet 17 Rev. 2.1, 2014-12-05

Figure 5 PC Board for Thermal Simulation with 600 mm² Cooling Area

Figure 6 PC Board for Thermal Simulation with 2s2p Cooling Area

BTS54220-LBB


Data Sheet 18 Rev. 2.1, 2014-12-05

Figure 7 Solder Area / Vias

4.2.2 Thermal Impedance

Figure 8 Typical Thermal Impedance. PCB setup according Figure 6

0,01

0,1

1

10

100

0,0001 0,001 0,01 0,1 1 10 100 1000

ZthJA[K

/W]

Time[s]

BTS54220LBx

2s2p1s0p600mm²1s0p300mm²1s0pfootprint

BTS54220-LBB


Data Sheet 19 Rev. 2.1, 2014-12-05

Figure 9 Typical Thermal Resistance. PCB setup 1s0p

20

25

30

35

40

45

50

55

60

0 100 200 300 400 500 600 700

RthJA[K

/W]

Area[mm²]

BTS54220LBx

1s0p

BTS54220-LBB

Power Supply

Data Sheet 20 Rev. 2.1, 2014-12-05

5 Power SupplyThe BTS54220-LBB is supplied by two voltage sources:• VS (analog supply voltage)• VDD (digital supply voltage)The VS supply line is connected to a battery feed and used for the driving circuitry of the power stages, while VDDis used for the SPI logic and for driving SO pin.VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the associatedfunction in case the measured voltage is below the undervoltage threshold. More in detail:• An undervoltage on VDD supply prevents SPI communication. SPI registers are reset to default values. The

retry counters used to protect the channels are reset therefore the channels are in “unlimited restart” mode.• An undervoltage on VS supply switches OFF all channels, even in Limp Home mode. The channels are

enabled again as soon as VS = VS(OP).The voltage at pin VS is also monitored. In case of a negative voltage transient resulting in VS < VSMON withDCR.MUX ≠ “111B”, any SPI command sent by the micro-controller is not accepted (see Chapter 9.5 for furtherdetails).An overview of channel behavior according to different VS and VDD supply voltages is shown in Table 4 (the tableis valid after a successful supply voltage ramp-up).

Table 4 Device capability as function of VS and VDD

VDD ≤ VDD(PO)(VDD(PO) = P_5.3.17)

VDD > VDD(PO)

VS ≤ VSMON(VSMON = P_5.3.12)

Channels are OFF Channels are OFF SPI registers reset SPI registers protected1)

1) If DCR.MUX ≠ 111B, othervise SPI registers are available.

SPI communication not available (fSCLK = 0 MHz)

SPI communication available2)

(fSCLK = 3 MHz)

2) SPI response depends on DCR.MUX value. See Chapter 9.5 for further details.

Limp Home mode not available Limp Home mode not availableVSMON < VS ≤ VS(UV)(VS(UV) = P_5.3.2)

Channels are OFF Channels are OFF SPI registers reset SPI registers available SPI communication not available (fSCLK = 0 MHz)

SPI communication available(fSCLK = 3 MHz)

Limp Home mode available (channels are OFF)

Limp Home mode available(channels are OFF)

VS > VS(UV)3)

3) The undervoltage condition on VS supply must be considered. See Chapter 5.2.1 for further details.

Channels cannot be controlled by SPI Channels can be switched ON and OFF

SPI registers reset SPI registers available SPI communication not available (fSCLK = 0 MHz)

SPI communication available(fSCLK = 3 MHz)

Limp Home mode available Limp Home mode available

BTS54220-LBB

Power Supply

Data Sheet 21 Rev. 2.1, 2014-12-05

5.1 Operation modesBTS54220-LBB has the following operation modes:• Stand-by mode• Idle mode• Ready mode• Operative mode• Limp Home modeThe transition between operation modes is determined according to these variables:• logic level at LHI pin• logic level at INn pins• DCR.MUX bits state• OUT.OUTn bits stateThe state diagram including the possible transitions is shown in Figure 10. The behavior of BTS54220-LBB aswell as some parameters may change in dependence from the operation mode of the device. Furthermore, dueto the undervoltage detection circuitry which monitors VS and VDD supply voltages, some changes within the sameoperation mode can be seen accordingly.

Figure 10 Operation Mode state diagram

There are three parameters describing the behavior of BTS54220-LBB:• status of output channels• status of SPI registers• status of SPI communicationIt is necessary to set DCR.MUX to a value different from 111B to command a switch ON of one or more channels.In alternative it is necessary to set the LHI to “high” - in this case the logic state of the Input pins is reflected to theoutputs (if there is no undervoltage condition on VS supply).

PowerSupply_OpModes.emf

DCR.MUX≠ "111"

Power -up

IdleDCR.MUX = "111" orVDD < VDD(PO) orHWCR.RST = "1"

OUT.OUTn = "1"or INn = "high"

OUT.OUTn = "0"& INn = "low"

DCR.MUX ≠ "111"

DCR.MUX = "111" or(VDD < VDD(PO ) & INn = "high") or(HWCR.RST= "1" & INn = "high")

OUT.OUTn = "1"or INn = "high"

OUT.OUTn= "0" or(VDD < VDD(PO) & INn = "low") orHWCR.RST= "1"

LHI = "high"

LHI = "low"& INn = "high"

LHI = "high"

LHI = "high"

LHI = "low"& INn = "low"

LHI = "high"

(VDD< V DD

(PO)

& INn =

„low“) o

r

(HWCR.RST

= "1" &

INn =

„low“)

Operative Ready

Limp Home

Stand-by

Note: Registers which are not mentioned are considered to be in default state

BTS54220-LBB

Power Supply

Data Sheet 22 Rev. 2.1, 2014-12-05

Table 5 shows the correlation between device operation modes, VS and VDD supply voltages, and the state of themost important functions (channel status, SPI communication and SPI registers).

5.1.1 Power-upThe Power-up condition is entered when one of the supply voltages (VS or VDD) is applied to the device. Bothsupplies are rising until they are above the undervoltage thresholds VS(OP) and VDD(PO) therefore the internal power-on signals are set.

5.1.2 Stand-by modeWhen BTS54220-LBB is in Stand-by mode, all outputs are OFF. The SPI registers can be programmed if VDD >VDD(PO). The current consumption is minimum (see parameter IVS(STB)). The circuitry that monitors VS versus thethreshold VSMON is disabled, allowing the programming of the registers. Even if one Input pin is set to “high” or ifone OUT.OUTn bit is set to “1”, all outputs stay switched OFF.

5.1.3 Idle modeIn Idle mode, the internal supply circuitry is working and the device current consumption is increased. All channelsare OFF and a command to switch ON one or more outputs (either via SPI or via Input pins) is accepted andexecuted, bringing the device into Operative mode.

Table 5 Device function in relation to operation modes, VS and VDD voltagesOperation Mode Function VS ≤ VSMON VSMON > VS ≤ VS(UV) VS > VS(UV)

Stand-by Channels OFF OFF OFF SPI comm. available1)

1) If VDD > VDD(PO), otherwise not available or in reset.

available1) available1)

SPI registers available1) available1) available1)

Idle Channels OFF OFF OFF SPI comm. all commands

rejected1)available1) available1)


Ready Channels OFF OFF OFF SPI comm. available1) available1) available1)


Operative Channels OFF OFF follow OUT.OUTn and/or Input pins

SPI comm. all commands rejected1)

available1) available1)


Limp Home Channels OFF OFF follow Input pins SPI comm. available

(read-only)1)2)

2) HWCR.CTC and HWCR.RST commands are accepted.

available(read-only)1)2)

available(read-only)1)2)

SPI registers reset reset reset

BTS54220-LBB

Power Supply

Data Sheet 23 Rev. 2.1, 2014-12-05

5.1.4 Ready modeIn Ready mode, one or more outputs received a command to switch ON (either via SPI or via Input pins).Nevertheless all outputs are OFF because of DCR.MUX bits still set to 111B. It is necessary to change the value ofthose bits to bring the device into Operative mode and switch ON the channels.

5.1.5 Operative modeOperative mode is the normal operation mode of BTS54220-LBB when no Limp Home condition is set and one ormore outputs are switched ON. Device current consumption is specified by parameter IGND. An undervoltagecondition on VDD supply voltage brings the device into Stand-by mode (if all Input pins are set to “low”) or intoReady mode (if at least one Input pin is set to “high”).

5.1.6 Limp Home modeBTS54220-LBB enters Limp Home mode when LHI pin is set to “high”. SPI registers are reset to the default valuesafter tLHI(ac) from the rising edge at pin LHI (see Figure 11 for further details). SPI communication is possible butonly in read-only mode (SPI registers can be read but cannot be written, meaning that current sensing is notavailable). When VS ≤ VSMON and DCR.MUX ≠ 111B the logic state detected at pin LHI is ignored and the devicedoesn’t enter Limp Home mode. Note: The only write commands excepted in Limp Home mode are HWCR.CTC and HWCR.RST to clear the

protection latches.

Figure 11 Limp Home Activation as function of VS

5.2 Reset conditionOne of the following 3 conditions resets the SPI registers to their default values:• VDD is not present or below the undervoltage threshold VDD(PO)

• LHI pin is set to “high” and VS > VSMON

• a reset command (HWCR.RST = 1B) is executed

In particular, all channels are switched OFF (if the device is not in Limp Home mode with one or more Input pinsset to “high”). In case of lack of VDD supply the internal retry counters are disabled therefore all channels are in“unlimited restart” mode.

LHIpin

LHIbit

SPI state

tLHI(ac)

t < tLHI(ac),min

tLHI(ac)

t < tLHI(ac),min

PowerSupply_LimpHomeActive.emf

Normal operation Reset Normal operation

VS

VSMON

BTS54220-LBB

Power Supply

Data Sheet 24 Rev. 2.1, 2014-12-05

5.2.1 Undervoltage on VSBetween VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative and the supplyvoltage drops below the undervoltage threshold VS(UV), the logic switches OFF the channels. As soon as the supplyvoltage VS is above the minimum operative voltage threshold VS(OP), the channels having either the correspondingInput pin set to “high” or the OUT.OUTn bit set to “1” are switched ON again (as shown in Figure 12).

Figure 12 VS undervoltage behavior

PowerSupply_UVRVS.emf

t

VS(OP)

VS(UV)VS(HYS)

t

VOUT

VS

BTS54220-LBB

Power Supply

Data Sheet 25 Rev. 2.1, 2014-12-05

5.3 Electrical CharacteristicsUnless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °CTypical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °CTypical resistive loads connected to the outputs (unless otherwise specified):9 mΩ channels: RL = 2.2 Ω27 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”)

Table 6 Electrical Characteristics Power SupplyParameter Symbol Values Unit Note /

Test ConditionNumber

Min. Typ. Max.VS pinOperating voltage power switch VS(OP) 5.5 – 281) V VDS < 0.5 V P_5.3.1Undervoltage shutdown VS(UV) – – 4.5 V OUTn = ON

From VDS < 1 Vto ILn = 0 A(see Figure 12)

P_5.3.2

Undervoltage shutdown Hysteresis

VS(HYS) – 350 – mV 1) P_5.3.3

Stand-by current for whole device with loads

IVS(STB) – 0.1 1 μA 1) VDD = 0 VVLHI = 0 VTj = 25 °C

P_5.3.7


IVS(STB) – 0.1 2.5 μA 1) VDD = 0 VVLHI = 0 VTj = 85 °C

P_5.3.8


IVS(STB) – 8 20 μA VDD = 0 VVLHI = 0 VTj = 150 °C

P_5.3.9

Idle current for whole device with loads, all channels OFF

IVS(idle) – 2.25 5 mA VDD = 5 VDCR.MUX = 110B

P_5.3.10

Operating current for whole device

IGND – 11 18 mA fSCLK = 0 MHz P_5.3.11

VS threshold for Limp Home validation

VSMON 0.6 1.2 1.8 V VSMON = 1 P_5.3.12

VDD pinLogic supply voltage VDD 3.8 – 5.51) V fSCLK = 3 MHz P_5.3.13Logic supply current Normal operation

IDD – 125 220 μA fSCLK = 0 MHzVCS = VDD= 5 VDCR.MUX ≠ 111B

P_5.3.14

Logic Stand-by current IDD(STB) – 35 70 μA fSCLK = 0 MHzVCS = VDD= 5 VDCR.MUX = 111B

P_5.3.16

BTS54220-LBB

Power Supply

Data Sheet 26 Rev. 2.1, 2014-12-05

Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VS = 13.5 V, VDD = 4.3 V and Tj = 25 °C

Power-On reset threshold voltage

VDD(PO) 2.3 2.75 3.8 V SI = 0 VSCLK = 0 VCS = 0 VSO from 0 to Z

P_5.3.17

LHI Input CharacteristicsL-input level at pin LHI VLHI(L) -0.3 – 1.0 V LHI = 1 (see

Chapter 9.6.1)P_5.3.18

H-input level at pin LHI VLHI(H) 2.6 – 6.0 V – P_5.3.19L-input current through pin LHI ILHI(L) 3 27 75 μA VLHI = 1.0 V P_5.3.20H-input current through pin LHI ILHI(H) 7 30 75 μA VLHI = 2.6 V P_5.3.21TimingsPower-On wake up time tWU(PO) – 200 – μs 1) P_5.3.22Limp Home acknowledgement time

tLHI(ac) 5 – 30 μs VDD = 5 Vpolling of Standard Diagnosis (see Chapter 9.6.1) until LHI = STB = 1

P_5.3.23

Reset command delay time td(RST) – – 100 μs 1) P_5.3.251) Not subject to production test, specified by design.

Table 6 Electrical Characteristics Power Supply (cont’d)



BTS54220-LBB

Power Stages

Data Sheet 27 Rev. 2.1, 2014-12-05

6 Power StagesThe high-side power stages are built by N-channel vertical power MOSFETs with charge pumps. There are fourchannels implemented in the device. Each channel can be switched on via SPI register OUT or via an input pin,when available. Channels 2 and 3 provide a load type configuration for bulbs or LEDs in register LGCR (seeChapter 9.7.4). The load type configuration can be changed in ON- as well as in OFF-state.

6.1 Output ON-State ResistanceThe ON-state resistance RDS(ON) depends mainly on the junction temperature Tj. Figure 13 shows the variation ofRDS(ON) across the whole temperature range. The value “1” corresponds to the typical RDS(ON) measured atTJ = 25°C.

Figure 13 RDS(ON) variation factor

The behavior in reverse polarity mode is described in Chapter 7.

6.2 Input CircuitThere are two ways of using the input pins in combination with the register OUT by programming bit HWCR.COL inregister HWCR (see Chapter 9.7.6).• HWCR.COL = 0: A channel is switched ON either by the according OUT.OUTn bit or by the input pin.• HWCR.COL = 1: A channel is switched ON by the according OUT.OUTn bit only, when the input pin is “high”. In

this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT (see Chapter 9.7.1).

The default state (HWCR.COL = 0) is the OR-combination of the input signal and the SPI-bit. In Limp Home Mode(LHI pin set to “high”) the combinatorial logic is switched to OR-mode to enable a channel activation via the inputpins only.Figure 14 shows the complete input switch matrix.

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00

-40 -20 0 20 40 60 80 100 120 140 160

RD

S(O

N)va

riatio

n fa

ctor

Junction Temperature (°C)

RDS(ON) variation factor ("1" = RDS(ON) typical @ 25°C)

BTS54220-LBB

Power Stages

Data Sheet 28 Rev. 2.1, 2014-12-05

The zener diode protects the input circuit against ESD pulses. The current sink to ground ensures that the inputsignal is low in case of an open input pin.

6.3 Input Status MonitorThe level of the input stage can be monitored via the input status monitor. The input status is indicated in the OUTregister for the available input pin. After setting the bit SWCR.SWR = 1B, the readout of OUT.INSTn shows the stateof the input pins.

Figure 14 Input Switch Matrix

PowerStage_InputMatrix_4chnoED.emf

IN1

IN2

Gate Driver 3

Gate Driver 2

Gate Driver 1

Gate Driver 4

&

OR

OUT3 OUT2 OUT1OUT4

&

OR

I IN1

I IN2

COLINST

INST2 INST1

IN3

IN4

&

OR

&

OR

I IN2

I IN3

INST3INST4

BTS54220-LBB

Power Stages

Data Sheet 29 Rev. 2.1, 2014-12-05

6.4 Power Stage OutputThe power stages are built to be used in high side configuration (Figure 15).The power DMOS switches with a dedicated slope, which is optimized in terms of electromagnetic emission(EME). Defined slew rates allow lowest EME during PWM operation at low switching losses.

Figure 15 Power Stage Output

6.4.1 Bulb and LED ModeChannel 2 and channel 3 can be configured in bulb and LED mode via the SPI initialization registers LGCR whenSWCR.SWR = 0. The default state is LGCR.LEDn = 0. During LED mode the following parameters are changed foran optimized functionality with LED loads: ON-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON,tOFF), slew rates dV/dtON and dV/dtOFF, load current protections IL(LIM) and current sense ratio kILIS.

6.4.2 Switching Resistive LoadsWhen switching resistive loads the following switching times and slew rates can be considered.

Figure 16 Switching a Load (resistive)

PowerStage_Output.emf

OUTGND VOUT

VS

VDS

VS

VOUT

t

PowerStage_SwitchON.emft

90% of Vs

10% of Vs

70% of Vs

dV /dtON

30% of Vs

70% of Vs

dV /dtOFF

30% of Vs

tdelay(ON) tdelay(OFF )

IN /OUT.OUTn

tON tOFF

BTS54220-LBB

Power Stages

Data Sheet 30 Rev. 2.1, 2014-12-05

6.4.3 Switching Inductive LoadsWhen switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,because the inductance intends to continue driving the current. To prevent the destruction of the device due toovervoltage, there is a voltage clamp mechanism implemented which limits that negative output voltage to acertain level (VDS(CL) (Chapter 6.5)). See Figure 15 for details.Please refer also to Chapter 7.4. The maximumallowed load inductance is limited.

6.4.4 Switching Channels in ParallelIn case of appearance of a short circuit with channels in parallel driving a single load, BTS54220-LBB outputstages are not synchronized in the restart event. When all channels connected to the same load are in temperaturelimitation, the channel which has cooled down the fastest doesn't wait for the other ones to be cooled down as wellto restart. Thus, it is not recommended to use the device with channels in parallel.

Note: In case of parallel channel operation, short circuit robustness may be reduced and nRSC1 is not guaranteed any more.

BTS54220-LBB

Power Stages

Data Sheet 31 Rev. 2.1, 2014-12-05

6.5 Electrical CharacteristicsUnless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °CTypical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °CTypical resistive loads connected to the outputs (unless otherwise specified):9 mΩ channels: RL = 2.2 Ω27 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”)

Table 7 Electrical Characteristics Power StagesParameter Symbol Values Unit Note / Test Condition Number

Min. Typ. Max.Output CharacteristicsOn-State resistance9 mΩ ch.

RDS(ON) – 9 – mΩ 1) VS = 9 V to 18 VIL = 7.5 A Tj = 25 °C

P_6.6.1

On-State resistance9 mΩ ch.

RDS(ON) – – 18.2 mΩ VS = 9 V to 18 V IL = 7.5 A Tj = 150 °C

P_6.6.2


RDS(ON) – 27 – mΩ 1) VS = 9 V to 18 VIL = 2.6 A Tj = 25 °C LGCR.LEDn = 0

P_6.6.5


RDS(ON) – – 55 mΩ VS = 9 V to 18 VIL = 2.6 A Tj = 150 °C LGCR.LEDn = 0

P_6.6.6

On-State resistance27 mΩ ch. in LED mode

RDS(ON) – 97 – mΩ 1) VS = 9 V to 18 VIL = 0.6 A Tj = 25 °C LGCR.LEDn = 1

P_6.6.7

On-State resistance27 mΩ ch. in LED mode

RDS(ON) – – 195 mΩ VS = 9 V to 18 VIL = 0.6 A Tj = 150 °C LGCR.LEDn = 1

P_6.6.8

Nominal load current9 mΩ ch.(all channels active)

IL(nom) – 5 – A 1)

TA = 85 °CTj < 150 °C

P_6.6.15

Nominal load current27 mΩ ch.(all channels active)

IL(nom) – 3 – A 1)

TA = 85 °CTj < 150 °C

P_6.6.16

Output clamp VDS(CL) 42 47 54 V IL = 20 mA P_6.6.19

BTS54220-LBB

Power Stages

Data Sheet 32 Rev. 2.1, 2014-12-05

Output leakage current per channelTj ≤ 85°C9 mΩ ch.

IL(OFF) – 0.02 1.4 µA 2) VIN = 0 V or floating OUT.OUTn = 0Tj ≤ 85°CStand-by or Idle mode

P_6.6.20

Output leakage current per channelTj ≤ 85°C27 mΩ ch.

IL(OFF) – 0.02 0.5 µA 2) VIN = 0 V or floating OUT.OUTn = 0Tj ≤ 85°CStand-by or Idle mode

P_6.6.21

Output leakage current per channelTj = 150°C9 mΩ ch.

IL(OFF) – 6 18 µA VIN = 0 V or floatingOUT.OUTn = 0Tj = 150°CStand-by or Idle mode

P_6.6.24

Output leakage current per channelTj = 150°C27 mΩ ch.

IL(OFF) – 1.7 6 µA VIN = 0 V or floatingOUT.OUTn = 0Tj = 150°CStand-by or Idle mode

P_6.6.25

Input CharacteristicsL-input level VIN(L) -0.3 – 1.0 V – P_6.6.28H-input level VIN(H) 2.6 – 6.0 V – P_6.6.29L-input current IIN(L) 3 27 75 µA VIN = 1.0 V P_6.6.30H-input current IIN(H) 7 30 75 µA VIN = 2.6 V P_6.6.31TimingsTurn-ON delay to10% VS (Logical propagation delay from input INn to output OUTn)9 mΩ ch.

tdelay(ON) 30 75 140 µs VS = 13.5 VTj = -40 °C

P_6.6.32

Turn-ON delay to10% VS (Logical propagation delay from input INn to output OUTn)9 mΩ ch.

tdelay(ON) – 45 – µs 1)

VS = 13.5 VTj = 25 °C

P_6.6.96


tdelay(ON) 15 30 55 µs VS = 13.5 VTj = 150 °C

P_6.6.97


tdelay(ON) 10 30 70 µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.34

Table 7 Electrical Characteristics Power Stages (cont’d)

Parameter Symbol Values Unit Note / Test Condition NumberMin. Typ. Max.

BTS54220-LBB

Power Stages

Data Sheet 33 Rev. 2.1, 2014-12-05

Turn-ON delay to10% VS (Logical propagation delay from input INn to output OUTn)27 mΩ ch. in LED mode

tdelay(ON) 3 10 25 µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.35

Turn-OFF delay to90% VS (Logical propagation delay from input INn to output OUTn)9 mΩ ch.

tdelay(OFF) 20 50 100 µs VS = 13.5 V P_6.6.39

Turn-OFF delay to90% VS (Logical propagation delay from input INn to output OUTn)27 mΩ ch.

tdelay(OFF) 10 30 70 µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.41

Turn-OFF delay to90% VS (Logical propagation delay from input INn to output OUTn)27 mΩ ch. in LED mode

tdelay(OFF) 3 10 25 µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.42

Turn-ON time to90%9 mΩ ch.

tON 45 95 170 µs VS = 13.5 VTj = -40 °C

P_6.6.46

Turn-ON time to90% VS9 mΩ ch.

tON – 65 – µs 1)

VS = 13.5 VTj = 25 °C

P_6.6.100


tON 30 55 90 µs VS = 13.5 VTj = 150 °C

P_6.6.101


tON 30 75 180 µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.48

Turn-ON time to90% VS27 mΩ ch. in LED mode

tON 10 25 55 µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.49

Turn-OFF time to10% VS9 mΩ ch.

tOFF 30 70 120 µs VS = 13.5 V P_6.6.53

Turn-OFF time to10% VS27 mΩ ch.

tOFF 30 85 180 µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.55

Turn-OFF time to10% VS27 mΩ ch. in LED mode

tOFF 10 30 55 µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.56



BTS54220-LBB

Power Stages

Data Sheet 34 Rev. 2.1, 2014-12-05

Turn-ON/OFF matching9 mΩ ch.

tON - tOFF -20 25 80 µs VS = 13.5 VTj = -40°C

P_6.6.60


tON - tOFF – -5 – µs 1) VS = 13.5 VTj = 25°C

P_6.6.61


tON - tOFF -50 -20 10 µs VS = 13.5 VTj = 150°C

P_6.6.62


tON - tOFF -50 -10 30 µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.66

Turn-ON/OFF matching27 mΩ ch. in LED mode

tON - tOFF -25 -5 15 µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.67

Turn-ON slew rate30% to 70% VS9 mΩ ch.

dV/ dtON 0.3 0.6 0.9 V/µs VS = 13.5 V P_6.6.71

Turn-ON slew rate30% to 70% VS27 mΩ ch.

dV/ dtON 0.1 0.25 0.5 V/µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.73

Turn-ON slew rate30% to 70% VS27 mΩ ch. in LED mode

dV/ dtON 0.35 0.88 1.75 V/µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.74

Turn-OFF slew rate70% to 30% VS9 mΩ ch.

-dV/dtOFF 0.3 0.6 0.9 V/µs VS = 13.5 V P_6.6.78

Turn-OFF slew rate70% to 30% VS27 mΩ ch.

-dV/dtOFF 0.1 0.25 0.5 V/µs VS = 13.5 VLGCR.LEDn = 0

P_6.6.80

Turn-OFF slew rate70% to 30% VS27 mΩ ch. in LED mode

-dV/dtOFF 0.35 0.88 1.75 V/µs VS = 13.5 VLGCR.LEDn = 1

P_6.6.81

Output Voltage DropOutput voltage drop limitation at small load currents All channels

VDS(NL) - 10 25 mV IL = 50 mALGCR.GBRn = 1

P_6.6.93

1) Not subject to production test, specified by design.2) Tested at Tj = -40 °C



BTS54220-LBB

Protection Functions

Data Sheet 35 Rev. 2.1, 2014-12-05

7 Protection FunctionsThe device provides embedded protective functions, which are designed to prevent IC destruction under faultconditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.Protective functions are neither designed for continuous nor for repetitive operation.

7.1 Over Load ProtectionThe load current IL is limited by the device itself in case of over load or short circuit to ground. All channels have2 steps of current limitation which are selected automatically depending on the voltage VDS across the powerDMOS as show in Figure 17. Please note that VOUT = VS - VDS. The current limitation threshold when VDS = 5 V istaken as reference.Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads tofast DMOS temperature rise.

Figure 17 Typical Current Limitation variation according to VDS voltage

7.2 Over Temperature ProtectionEach channel incorporates both an absolute (Tj(SC)) and a dynamic (∆Tj(SW)) temperature sensor. An increase ofjunction temperature Tj above one of the two thresholds (Tj(SC) or ΔTj(SW)) switches OFF an overheated channel toprevent destruction. Any protective switch OFF deactivates the output until the temperature has reached anacceptable value.Each protective switch OFF event increments the error counter by one. The number of automatic reactivations islimited by nretry. If this number of retries is reached the channel turns OFF and latches OFF.The error information related to the given channel is available on the Standard Diagnosis and Errors Diagnosis.Executing HWCR.CTC = 1B will clear all thermal counters and errors on all channels. If the channel is active (eitherOUT.OUTn = 1B or INn = “high” and DCR.MUX ≠ 111B) it is turned on immediately after the SPI command. Inaddition the execution of the reset command (HWCR.RST = 1B) will clear the thermal counters.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

4 8 12 16 20 24 28

Cur

rent

lim

itatio

n va

riatio

n fa

ctor

Drain Source Voltage (V)

Current limitation variation ("1" = IL(LIM) @ VDS = 5 V)

BTS54220-LBB


Data Sheet 36 Rev. 2.1, 2014-12-05

For the condition n < nretry the counter of automatic reactivations is reset by every channel activation if HWCR.RCRbit is set to 1. In Figure 20 the different behavior of retry counters according to HWCR.RCR bit value can be seen.

In Limp Home Mode, the thermal counters of the protection functions are only operative if VDD is provided in thespecified range. Otherwise the counters are not active and all channels are in „unlimited restart“ mode.In case of the short circuit to ground, current sense ratio (kILIS) is deactivated as soon as VDS > VDS(SB) (Switchbypass monitor threshold). Usually a short circuit to ground condition tends to set VDS = VS therefore in most ofthe cases no current sensing diagnostic is possible in short circuit.The error information related to the given channel are available also on Warnings Diagnosis (ERRn bits).Refer to Figure 18 and Figure 19 for details.

BTS54220-LBB


Data Sheet 37 Rev. 2.1, 2014-12-05

Figure 18 Dynamic Temperature Sensor Operations - Short Circuit

Protection_DynT_SC.emf

IN /OUT.OUTn

* ERR reset by : HWCR.CTC = 1

t

I IS

IL(LIM)

IL

Tj

ΔT j

SW

ΔT j

SW

ERR_COUNTER

0 1 ... nretry

ERR

Internal counter

0 1

0 1

0 1

0

2

1

0

t

t

t

t

t

t

ΔT j

SW

ΔT j

SW

Tj (SC)

BTS54220-LBB


Data Sheet 38 Rev. 2.1, 2014-12-05

Figure 19 Dynamic and Absolute Temperature Sensor Operations - Overload Condition

IL(LIM )

IL

t

ΔTjSW

Tj

IIS

Protection_DynT_OverLoad.emf

IN /OUT.OUTn

* ERR reset by: HWCR.CTC = 1

ERR_COUNTER

0 1 ... n retry

ERR

Internal counter

0 1

0 1

0

0

2

0

ΔTjSW

ΔTjSW

t

t

t

t

t

t

Tj(SC)

BTS54220-LBB


Data Sheet 39 Rev. 2.1, 2014-12-05

Figure 20 Different counter reset according to HWCR.RCR bit value

7.3 Reverse Polarity ProtectionIn reverse polarity condition, power dissipation is caused by the intrinsic body diode of each DMOS channel aswell as each ESD diode of the logic pins. The reverse current through the channels has to be limited by theconnected loads.The current through ground pin GND, sense pin IS, logic power supply pin VDD, SPI pins, inputpins and Limp Home Input pin has to be limited as well (please refer to the maximum ratings listed onChapter 4.1).Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity.

7.4 Over Voltage ProtectionIn the case of supply voltages between VS(SC)max and VS(AZ) the output transistors are still operational and followthe input or the OUT register. Parameters are not warranted and lifetime is reduced compared to nominal voltagesupply.In addition to the output clamp for inductive loads as described in Chapter 6.4.3, there is a clamp mechanismavailable for over voltage protection for the logic and all channels.

7.5 Loss of GroundIn case of complete loss of the device ground connection, but loads connected to ground, the BTS54220-LBBsecurely changes to or stays in OFF-state. Please refer to Chapter 10 where an application setup is described.

7.6 Loss of VSIn case of loss of VS connection in ON-state, all inductances of the loads have to be demagnetized through theground connection or through an additional path from VS to ground. For example, a suppressor diode isrecommended between VS and GND.

Internal counter

IN /OUT.OUTn

Protection_RCR.emf

0 1

ILIL(LIM )

t

2 3 4 5

ERR

HWCR.RCR 0 (default ) 1

0 1

1 2 0 1

0 1

0

1 0

t

t

t

t

BTS54220-LBB


Data Sheet 40 Rev. 2.1, 2014-12-05

7.7 Electrical CharacteristicsUnless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °Ctypical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °CTypical resistive loads connected to the outputs (unless otherwise specified):9 mΩ channels: RL = 2.2 Ω27 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”)

Table 8 Electrical Characteristics Protection FunctionsParameter Symbol Values Unit Note /


Min. Typ. Max.Over Load ProtectionLoad current limitation9 mΩ ch.

IL(LIM) 63 82 99 A 1)

VDS = 5 V P_7.7.1

Load current limitation9 mΩ ch.

IL(LIM) – 41 – A 1) VDS = 26 V

P_7.7.2


IL(LIM) 30 42 56 A 1)

VDS = 5 V LGCR.LEDn = 0

P_7.7.5


IL(LIM) – 21 – A 1) VDS = 26 VLGCR.LEDn = 0

P_7.7.6

Load current limitation27 mΩ ch. in LED mode

IL(LIM) 9.5 12 17 A VDS = 5 V Tj = -40 °CLGCR.LEDn = 1

P_7.7.7

Load current limitation27 mΩ ch. in LED mode

IL(LIM) – 5 – A 1) VDS = 26 V LGCR.LEDn = 1

P_7.7.8

Over Temperature ProtectionThermal shut down temperature

Tj(SC) 150 170 200 °C 1) P_7.7.14

Thermal hysteresis of thermal shutdown

∆Tj(SC) – 20 – K 1) P_7.7.15

Dynamic temperature increase limitation while switching

∆Tj(SW) – 80 – K 1) P_7.7.16

Number of automatic retries at dynamic temperature sensor or over temperature shut down

nretry – 8 9 1) P_7.7.17

Reverse PolarityDrain source diode voltage during reverse polarity9 mΩ ch.

VDS(REV) 400 600 740 mV IL = IL(nom) = P_6.6.15Tj = 150 °C

P_7.7.18

BTS54220-LBB


Data Sheet 41 Rev. 2.1, 2014-12-05

Drain source diode voltage during reverse polarity27 mΩ ch.

VDS(REV) 400 650 800 mV IL = IL(nom) = P_6.6.16Tj = 150 °C

P_7.7.19

Over VoltageOvervoltage protection VS(AZ) 42 47 54 V IS = 4 mA P_7.7.221) Not subject to production test, specified by design.

Table 8 Electrical Characteristics Protection Functions (cont’d)



BTS54220-LBB

Diagnosis

Data Sheet 42 Rev. 2.1, 2014-12-05

8 DiagnosisFor diagnosis purpose, the BTS54220-LBB provides a current sense signal at pin IS and a diagnosis word via SPI.There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabledby SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the batteryvoltage.Please refer to Figure 21 for details.

Figure 21 Block Diagram: Diagnosis

For diagnosis feedback at different operation modes, please see Table 9.

channel 1

loadcurrentsense

RIS

IIS0

current sense multiplexer

T

gate control

load current limitation

latch temperature sensor

ERR1

OR

latch

DCR.MUX

OUT4OUT3OUT2OUT1

VS

IS

VS

VDS(SB)

SBM

DCR.

Diagnosis_4ch.emf

BTS54220-LBB

Diagnosis

Data Sheet 43 Rev. 2.1, 2014-12-05

8.1 Diagnosis Word at SPI

Diagnostic information about the status of each channel is provided through SPI. In the Standard Diagnosis theERR_MUX bit reports if there is a channel which had already enough restarts to reach the maximum allowednumber of retries nretry (P_7.7.17). If 2 or more channels are latched OFF due to that, ERR_MUX bits aren't enoughto identify which channels are OFF. In such cases, it is possible to get an overview channel by channel usingERR_COUNTERn bits in Errors Diagnosis (see Chapter 9.6.2)It is possible to check if one or more channels had some retries during switching ON, although the limit of nretry wasnot reached. An overview channel by channel of thermal counter status is available using ERRn bits in WarningsDiagnosis (see Chapter 9.6.3).For both ERR_COUNTERn and ERRn the information on channel n is given at bit n-1 (e.g. bit 0 indicates status ofchannel 1).

Table 9 Operation Modes 1)

1) L = “low” level, H = “high” level, Z = high impedance, potential depends on leakage currents and external circuit. X = undefined.

Operation Mode Input Level OUT.OUTn

Output Level VOUT

Current Sense IIS

Error Flag ERR_COUNTERn2)

2) The over temperature flag is set latched and can be cleared by setting HWCR.CTC = 1B.

Warning Flag ERRn3)

3) The warning flags are latched until they are reset (see HWCR.RCR description).

DCR.SBM bit

Normal Operation (Channel OFF) L / 0(OFF-state)

GND Z 0 0 1Short Circuit to GND GND Z 0 0 1Thermal shut down Z Z 02) 02) XShort Circuit to VS VS Z 0 0 0Open Load Z Z 0 0 X

Normal Operation (Channel ON) H / 1(ON-state)

~VS IL / kILIS 0 0 0Current Limitation < VS Z 0 0 XDynamic or Absolute Thermal Limitation → Channel switched OFF

Z Z 0 1 X

Dynamic or Absolute Thermal Limitation nretry reached → Channel latched OFF

Z Z 12) 1 X

Short Circuit to GND ~GND Z 0 0 1Short Circuit to VS VS < IL / kILIS 0 0 0Open Load VS Z 0 0 0

BTS54220-LBB

Diagnosis

Data Sheet 44 Rev. 2.1, 2014-12-05

8.2 Load Current Sense DiagnosisThere is a current sense signal available at pin IS which provides a current proportional to the load current of oneselected channel. The selection is done by a multiplexer which is configured via SPI.

8.2.1 Current Sense SignalThe current sense signal (ratio kILIS = IL / IS) is provided during ON-state as long as no failure mode occurs. Fordedicated channels the ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register LGCR. Theaccuracy of the ratio kILIS depends on the load current and temperature. Usually a resistor RIS is connected to thecurrent sense pin. It is recommended to use resistors 1.5 kΩ < RIS < 5 kΩ. A typical value is 2.7 kΩ.The current sense signal of a channel is not active when the channel is OFF or when the protection functions(current limitation, over temperature or dynamic temperature sensors) are active. If the maximum number ofautomatic reactivations nretry is reached (n = nretry), the current sense signal of the affected channel is deactivateduntil the reset of the counters by setting HWCR.CTC bit to 1.Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL canbe found in Figure 22.

Figure 22 Current Sense Signal Timings

8.2.2 Current Sense MultiplexerThere is a current sense multiplexer implemented in the BTS54220-LBB that routes the sense current of theselected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense currentcan also be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please referto Figure 23.

Diagnosis_SenseTiming.emf

VOUT

IIS

t

t

t

ILt

ON

tON

tsIS (ON) tsIS (LC)

OFF

tOFF

tdIS(OFF)

OFFIN /

OUT.OUTn

BTS54220-LBB

Diagnosis

Data Sheet 45 Rev. 2.1, 2014-12-05

Figure 23 Current Sense Multiplexer Timings

8.2.3 Open Load at ON DiagnosisIf a channel is ON in Open Load condition, a small current can still flow, for example because of humidity. Theparameter IL(OL) gives the threshold of recognition for such leakage current. If the voltage measured at the senseresistor RSENSE corresponds to a current IIS(OL) (4 µA), then the current flowing at the output in ON state is withinthe limits given by IL(OL). Figure 24 shows the sense current behavior once a channel in Open Load at ONcondition is selected with the sense current multiplexer. The red curve show a typical product curve. The blue lineshows the ideal kILIS ratio.

Figure 24 Current Sense Ratio in Open Load at ON condition

8.3 Switch Bypass Monitor DiagnosisTo detect short circuit to VS, there is a switch bypass monitor implemented. In case of short circuit between theoutput pin OUT and VS in ON-state, the current flows through the power transistor as well as through the shortcircuit (bypass) with undefined share between the two. As a result, the current sense signal shows lower valuesthan expected by the load current. In OFF-state, the output voltage remains close to VS potential which leads to asmall VDS.The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of thatchannel which is selected by the current sense multiplexer (DCR.MUX). The result of the comparison can be readin SPI register DCR.SBM.

Diagnosis_MuxTiming.emf

CS

IIS

t

000DCR.MUX 001110 110

tsIS (EN) t sIS(MUX) tdIS (MUX) t

IIS

IL

IIS(OL )

IL(OL )

IIS(en)

BTS54220-LBB

Diagnosis

Data Sheet 46 Rev. 2.1, 2014-12-05

8.4 Gate Back RegulationTo increase the current sense accuracy, the Gate Back Regulation (GBR) function is implemented. This functionmonitors the VDS voltage at the output and if the value is equal to or lower than VDS(NL) the output DMOS gate ispartially discharged. This increases output DMOS resistance so that VDS = VDS(NL) even for very small outputcurrents. The VDS increase allows the current sensing circuitry to work with better accuracy, providing tighter kILISvalues for output currents in the low range.This function is active by default (LGCR.GBRn bits set to “1” after a reset). According to output current, GBRfunction can be left active or disabled. Even if left active, Gate Back Regulation circuitry may not be workingbecause the measured VDS is bigger than VDS(NL) (depending on output current, junction temperature, outputDMOS resistance).Due to production and temperature variations, GBR circuitry can affect kILIS performance in negative way forsome output current values. For this reason, Table 10 and Table 11 indicate for which output currents it isnecessary to deactivate GBR (setting the corresponding LGCR.GBRn bit to “0”) to reach the desired currentaccuracy. If no indication is given, then the GBR function is assumed to be enabled (LGCR.GBRn bit set to “1”). Itis recommended to keep GBR circuitry enabled for Open Load at ON diagnosis.The circuitry that controls GBR function can be deactivated with the following SPI command sequence:• SWCR.SWR = 1 (SPI command: 11001100B)• LGCR.GBRn = 0 (SPI command: 1101aaaaB where “aaaa”B is the new value for LGCR.GBRn bits)• (optional but recommended: SWCR.SWR = 0 (SPI command: 11000100B)Refer to Chapter 9.7 for more details.

BTS54220-LBB

Diagnosis

Data Sheet 47 Rev. 2.1, 2014-12-05

8.5 Electrical CharacteristicsUnless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °CTypical values: VS = 13.5 V, VDD= 4.3 V, Tj = 25 °CTypical resistive loads connected to the outputs (unless otherwise specified):9 mΩ channels: RL = 2.2 Ω27 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”)

Measurement setup used for kILIS (unless otherwise specified):Channel 1, 4: when IL ≤ 1.3 A both channels are ON at the same time with equal IL, channels 2, 3 have IL = 0Channel 2, 3: when IL ≤ 1.3 A both channels are ON at the same time with equal IL, channels 1, 4 have IL = 0When IL ≥ 2.0 A only the measured channel is ON, all other channels have IL = 0

Table 10 Electrical Characteristics Diagnosis kILIS 9 mΩ ch.Parameter Symbol Values Unit Note /


Min. Typ. Max.Current sense ratioIL04 = 450 mA

kILIS04 -67 % 4500 +142 % – P_8.5.5

Current sense ratioIL05 = 600 mA

kILIS05 -56 % 4500 +56 % – P_8.5.6

Current sense ratioIL07 = 1.3 A

kILIS07 -33 % 4500 +41 % LGCR.GBRn = 0 P_8.5.8


kILIS09 -18 % 4500 +18 % LGCR.GBRn = 0 P_8.5.10

Current sense ratioIL10 = 4 A

kILIS10 -15 % 4500 +15 % – P_8.5.11


kILIS11 -11 % 4500 +11 % – P_8.5.12

Table 11 Electrical Characteristics Diagnosis kILIS 27 mΩ ch.Parameter Symbol Values Unit Note /


Min. Typ. Max.Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition27 mΩ ch.Current sense ratioIL03 = 300 mA

kILIS03 -42 % 2000 +42 % – P_8.5.28


kILIS05 -33 % 2000 +33 % – P_8.5.30


kILIS07 -21 % 2000 +21 % – P_8.5.32


kILIS09 -12 % 2000 +12 % – P_8.5.34


kILIS10 -11 % 2000 +11 % – P_8.5.35

BTS54220-LBB

Diagnosis

Data Sheet 48 Rev. 2.1, 2014-12-05

Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition27 mΩ ch. in LED modeCurrent sense ratioIL00 = 20 mA

kILIS00 -52 % 620 +52 % – P_8.5.37


kILIS02 -33 % 570 +33 % – P_8.5.39


kILIS03 -25 % 570 +25 % LGCR.GBRn = 0 P_8.5.40


kILIS05 -14 % 570 +14 % – P_8.5.42


kILIS06 -11 % 570 +11 % – P_8.5.43

Table 12 Electrical Characteristics DiagnosisParameter Symbol Values Unit Note /


Min. Typ. Max.Sense pin maximum voltage

VIS(AZ) 42 47 54 V IIS = 5 mA P_8.5.75

Current Sense Drift Over Current and Temperature per DeviceCurrent sense drift over current and temperature per device9 mΩ ch.

ΔkILIS(T) -10 – 10 % 1) kILIS11 versus kILIS09

P_8.5.76

Current sense drift over current and temperature per device27 mΩ ch.

ΔkILIS(T) -8 – 8 % 1) kILIS09 versus kILIS07LGCR.LEDn = 0

P_8.5.77

Current sense drift over current and temperature per device27 mΩ ch. in LED mode

ΔkILIS(T) -9.5 – 9.5 % 1) kILIS05 versus kILIS03LGCR.LEDn = 1

P_8.5.78

Table 11 Electrical Characteristics Diagnosis kILIS 27 mΩ ch. (cont’d)



BTS54220-LBB

Diagnosis

Data Sheet 49 Rev. 2.1, 2014-12-05

Current Sense Drift of Unaffected Channel during Inverse Current of other Channels One channel with IL(IC) = - ILn, all other channels with ILnDCR.MUX ≠ <111, 110> and set to sense any of the channels not in Inverse current conditionCurrent sense drift of unaffected channels during inverse current of one channel

ΔkILIS(IC) -20 – 20 % 1) IL1 = 7.5 AIL2 = 2.6 AIL3 = 2.6 AIL4 = 7.5 A

P_8.5.83

Sense Pin - CurrentsMaximum steady state current sense output current9 mΩ ch.

IIS(MAX) 4.5 – 15 mA VIS = 0 VVS ≥ 8 V

P_8.5.86

Maximum steady state current sense output current27 mΩ ch.

IIS(MAX) 3.8 – 15 mA VIS = 0 VVS ≥ 8 V

P_8.5.87

Current sense leakage / offset current

IIS(en) – – 1 μA 1) Tj ≤ 85 °CIL = 0 mA DCR.MUX ≠ <111,110>B

P_8.5.118

Current sense leakage / offset current

IIS(en) – – 3.2 μA Tj = 150 °CIL = 0 mA DCR.MUX ≠ <111,110>B

P_8.5.90

Open load detection threshold in ON state9 mΩ ch.

IL(OL) – – 48.5 mA IIS(OL) = 4 μA P_8.5.91

Open load detection threshold in ON state27 mΩ ch.

IL(OL) – – 21.5 mA IIS(OL) = 4 μALGCR.LEDn = 0

P_8.5.93

Open load detection threshold in ON state27 mΩ ch. in LED mode

IL(OL) – – 7.5 mA IIS(OL) = 4 μALGCR.LEDn = 1

P_8.5.94

Current sense leakage, while diagnosis disabled

IIS(dis) – 0.01 1 μA IL2 = 2.6 ADCR.MUX = 110B

P_8.5.98

Sense Pin - TimingsCurrent sense settling time after channel activation9 mΩ ch.

tsIS(ON) – – 250 μs VS = 13.5 VRIS = 2.7 kΩ

P_8.5.99

Current sense settling time after channel activation27 mΩ ch.

tsIS(ON) – – 250 μs VS = 13.5 VRIS = 2.7 kΩLGCR.LEDn = 0

P_8.5.101

Table 12 Electrical Characteristics Diagnosis (cont’d)



BTS54220-LBB

Diagnosis

Data Sheet 50 Rev. 2.1, 2014-12-05

Current sense settling time after channel activation27 mΩ ch. in LED mode

tsIS(ON) – – 100 μs VS = 13.5 VRIS = 2.7 kΩLGCR.LEDn = 1

P_8.5.102

Current sense desettling time after channel deactivation

tdIS(OFF) – – 25 μsVS = 13.5 V RIS = 2.7 kΩ

P_8.5.106

Current sense settling time after change of load current9 mΩ ch.

tsIS(LC) – – 25 μs 1)

IL = 4 A to 2.6 AVS = 13.5 V RIS = 2.7 kΩ

P_8.5.107

Current sense settling time after change of load current27 mΩ ch.

tsIS(LC) – – 25 μs 1)

IL = 2.6 A to 1.3 AVS = 13.5 V RIS = 2.7 kΩLGCR.LEDn = 0

P_8.5.109

Current sense settling time after change of load current27 mΩ ch. in LED mode

tsIS(LC) – – 25 μs 1)

IL = 1.3 A to 0.6 AVS = 13.5 V RIS = 2.7 kΩLGCR.LEDn = 1

P_8.5.110

Current sense settling time after current sense activation

tsIS(EN) – – 25 μsRIS = 2.7 kΩIL2 = 2.6 ADCR.MUX: 110B → 001B

P_8.5.114

Current sense settling time after multiplexer channel change

tsIS(MUX) – – 25 μsRIS = 2.7 kΩIL2 = 2.6 AIL3 = 4 ADCR.MUX: 001B → 010B

P_8.5.115

Current sense deactivation time

tdIS(MUX) – – 25 μs 1)

RIS = 2.7 kΩ DCR.MUX: 010B → 110B

P_8.5.116

Switch Bypass MonitorSwitch bypass monitor threshold

VDS(SB) 1.5 3.3 4.5 V OFF state P_8.5.117

1) Not subject to production test, specified by design.

Table 12 Electrical Characteristics Diagnosis (cont’d)



BTS54220-LBB

Serial Peripheral Interface (SPI)

Data Sheet 51 Rev. 2.1, 2014-12-05

9 Serial Peripheral Interface (SPI)The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSindicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out online SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counterensures that data is taken only when a multiple of 8 bit has been transferred. The interface provides daisy chaincapability with 8-bit SPI devices.

Figure 25 Serial Peripheral Interface

9.1 SPI Signal Description

CS - Chip SelectThe system micro controller selects the BTS54220-LBB by means of the CS pin. Whenever the pin is in “low” state,data transfer can take place. When CS is in “high” state, any signals at the SCLK and SI pins are ignored and SOis forced into a high impedance state.

CS “high” to “low” Transition• The requested information is transferred into the shift register.• SO changes from high impedance state to “high” or “low” state depending on the signal level at pin SI.

Figure 26 Combinatorial Logic for TER Flag

6 5 4 3 2 1

LSB6 5 4 3 2 1CS MSBSO

SI

CS

SCLKtime

SPI _8bit.emf

LSBMSB

SPI _TER.emf

SI

SPI

OR

TER

0

1 SO

CSSCLK

S

SOS

SI

BTS54220-LBB


Data Sheet 52 Rev. 2.1, 2014-12-05

CS “low” to “high” Transition• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK

signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored.

• Data from shift register is transferred into the addressed register.

SCLK - Serial ClockThis input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the fallingedge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.It is essential that the SCLK pin is in “low” state whenever chip select CS makes any transition, otherwise thecommand may be not accepted.

SI - Serial InputSerial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edgeof SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 9.5 forfurther information.

SO Serial OutputData is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pingoes to “low” state. New data will appear at the SO pin following the rising edge of SCLK.Please refer to Chapter 9.5 for further information.

9.2 Daisy Chain CapabilityThe SPI of BTS54220-LBB provides daisy chain capability. In this configuration several devices are activated bythe same CS signal MCS. The SI line of one device is connected with the SO line of another device (seeFigure 27), in order to build a chain. The end of the chain is connected to the output and input of the master device,MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK lineof each device in the chain.

Figure 27 Daisy Chain Configuration

In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. Thebit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device is finished. In singlechip configuration, the CS line must turn “high” to make the device acknowledge the transferred data. In daisychain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices indaisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must turn “high”(see Figure 28).

SI

device 1

SPI

SCLK

SO

CS

SI

device 2

SPI

SCLK

SO

CS

SI

device 3

SPI

SCLK

SO

CS

MO

MIMCS

MCLKSPI_DaisyChain.emf

BTS54220-LBB


Data Sheet 53 Rev. 2.1, 2014-12-05

Figure 28 Data Transfer in Daisy Chain Configuration

9.3 Timing Diagrams

Figure 29 Timing Diagram SPI Access

MI

MO

MCS

MCLK

SI device 3 SI device 2 SI device 1

SO device 3 SO device 2 SO device 1

timeSPI_DaisyChain_2.emf

CS

SCLK

SI

tCS(lead) tCS(td)tCS(lag)

tSCLK(H) tSCLK(L)

tSCLK(P )

tSI (su) tSI(h)

SO

tSO(v)tSO(en) tSO (dis)

SPI _Timings.emf

VCS(H)

VCS(L)

VSCLK(H)

VSCLK(L)

VSI(H)

VSI(L)

VSO(H)

VSO(L)

BTS54220-LBB


Data Sheet 54 Rev. 2.1, 2014-12-05

9.4 Electrical CharacteristicsUnless otherwise specified: VS = 7 V to 18 V, Tj = -40 °C to +150 °C, VDD = 3.8 V to 5.5 VTypical values: VS = 13.5 V, Tj = 25 °C, VDD = 4.3 V

Table 13 Electrical Characteristics Serial Peripheral Interface (SPI)Parameter Symbol Values Unit Note /


Min. Typ. Max.Input Characteristics (CS, SCLK, SI) - L Level of pinCS VCS(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.1SCLK VSCLK(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.2SI VSI(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.3Input Characteristics (CS, SCLK, SI) - H Level of pinCS VCS(H) 2.6 – VDD V VDD = 4.3 V P_9.4.4SCLK VSCLK(H) 2.6 – VDD V VDD = 4.3 V P_9.4.5SI VSI(H) 2.6 – VDD V VDD = 4.3 V P_9.4.6L-input pull-up current at CS pin -ICS(L) 7 30 75 μA VDD = 4.3 V

VCS = 1.0 VP_9.4.7

H-input pull-up current at CS pin -ICS(H) 3 27 75 μA VDD = 4.3 VVCS = 2.6 V

P_9.4.8

L-Input Pull-Down Current at PinSCLK ISCLK(L) 3 27 75 μA VSCLK = 1.0 V

VDD = 4.3 VP_9.4.9

SI ISI(L) 3 27 75 μA VSI = 1.0 VVDD = 4.3 V

P_9.4.10

H-Input Pull-Down Current at PinSCLK ISCLK(H) 7 30 75 μA VSCLK = 2.6 V

VDD = 4.3 VP_9.4.11

SI ISI(H) 7 30 75 μA VSI = 2.6 VVDD = 4.3 V

P_9.4.12

Output Characteristics (SO)L level output voltage VSO(L) 0 – 0.5 V ISO = -0.5 mA P_9.4.13H level output voltage VSO(H) VDD -

0.5 V– VDD V ISO = 0.5 mA

VDD = 4.3 VP_9.4.14

Output tristate leakage current ISO(OFF) -1 – 1 μA VCS =VDDVSO = 0 VVSO = VDD

P_9.4.15

TimingsEnable lead time (falling CS to rising SCLK)

tCS(lead) 200 – – ns –1) P_9.4.16

Enable lag time (falling SCLK to rising CS)

tCS(lag) 200 – – ns –1) P_9.4.17

Transfer delay time (rising CS to falling CS)

tCS(td) 1 – – μs –1) P_9.4.18

BTS54220-LBB


Data Sheet 55 Rev. 2.1, 2014-12-05

Output enable time (falling CS to SO valid)

tSO(en) – – 1 μs 1)

CL = 50 pFP_9.4.19

Output disable time (rising CS to SO tristate)

tSO(dis) – – 1 μs 1)

CL = 50 pFP_9.4.20

Serial clock frequency fSCLK 0 – 3 MHz –1) P_9.4.22Serial clock period tSCLK(P) 333 – – ns –1) P_9.4.24Serial clock “high” time tSCLK(H) 150 – – ns –1) P_9.4.26Serial clock “low” time tSCLK(L) 150 – – ns –1) P_9.4.28Data setup time (required time SI to falling SCLK)

tSI(su) 65 – – ns –1) P_9.4.30

Data hold time (falling SCLK to SI) tSI(h) 65 – – ns –1) P_9.4.32Output data valid time with capacitive load

tSO(v) – – 166 ns 1)

CL = 50 pFP_9.4.34

1) Not subject to production test, specified by design

Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)



BTS54220-LBB


Data Sheet 56 Rev. 2.1, 2014-12-05

9.5 SPI ProtocolThe relationship between SI and SO content during SPI communication is shown in Figure 30. SI line representsthe frame sent from the µC and SO line is the answer provided by BTS54220-LBB. The “(previous response)”means that the frame sent back depends on the command frame sent from the µC before.

Figure 30 Relationship between SI and SO during SPI communication

The SPI protocol provides the answer to a command frame only with the next transmission triggered by the µC.Although the biggest majority of commands and frames implemented in BTS54220-LBB can be decoded withoutthe knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmissionto decode BTS54220-LBB response frame completely.More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:

Figure 31 Register content sent back to µC

There are 3 special situations where the frame sent back to the µC doesn't depend on the previous received frame:• in case an error in transmission happened during the previous frame (for instance, the clock pulses were not

multiple of 8), shown in Figure 32• when BTS54220-LBB logic supply comes out of Power-On reset condition, as shown in Figure 33• when VS < VSMON and DCR.MUX ≠ 111B, as shown in Figure 34

Figure 32 BTS54220-LBB response after an error in transmission

SI

SO

frame A frame B

(previous response )

response to frame A

frame C

response to frame B

SPI_SI2SO.emf

SI

SO

write register A read register A

Standard diagnostic

register A content

(new command )

SPI_RWseq.emf

(previous response )

frame A(error in transmission )

SPI_SO_TER.emf

SI

SO

(new command)

Standard diagnostic + TER(previous response )

BTS54220-LBB


Data Sheet 57 Rev. 2.1, 2014-12-05

Figure 33 BTS54220-LBB response after coming out of Power-On reset at VDD

Figure 34 BTS54220-LBB response in case of a negative battery voltage transient

A summary of all possible SPI commands is presented in Table 14, including the answer that BTS54220-LBB willsend back at the next transmission.

SI

SO

frame A frame B

(SO = „Z“)

frame C

response to frame BStandard Diagnosis

+ TER

VDD(PO)

SPI _SO_POR.emf

VDD

SI

SO

SPI_SO_VSMON.emf

VSMON,max

t

VS

VSMON,min

0VSMON x 1

t

x 0

(response )

frame A frame B frame C frame D

Std. Diag. + TER+ VSMON

Std. Diag. + TER+ VSMON

(response toframe C)

BTS54220-LBB


Data Sheet 58 Rev. 2.1, 2014-12-05

Table 14 SPI Command SummaryRequested Operation Frame sent to SPOC+ (SI pin) Frame received from SPOC+ (SO pin)

with the next commandWrite OUT register 100xaaaaB

where:“xaaaaB” = new OUT register content(“xxB” = don't care)

0aaaaaaaB(Standard Diagnosis)

Read OUT register 00xx0000B(“xxB” = don't care)

10aaaaaaB(“aaaaaaB” = OUT register content)

Write Configuration register 11aabbbbBwhere:“aaB” = register address“bbbbB” = new register content


Read Configuration register 01aa0000Bwhere:“aaB” = register address

11aabbbbBwhere:“aaB” = register address“bbbbB” = register content

Read Standard Diagnosis 0xxx0001B(“xxxB” = don't care)


Read Errors Diagnosis 0xxx0011B(“xxxB” = don't care)

00aaaaaaB(Error Diagnosis)

Read Warnings Diagnosis 0xxx0101B(“xxxB” = don't care)

00aaaaaaB(Warning Diagnosis)

BTS54220-LBB


Data Sheet 59 Rev. 2.1, 2014-12-05

9.6 SPI Diagnosis Registers

9.6.1 Standard Diagnosis

SO 7 6 5 4 3 2 1 0 Default

0 TER LHI STB VSMON ERR_MUX 50H

Field Bits Type DescriptionTER 6 r Transmission Error

0B Previous transmission was successful (modulo 8 clocks received)

1B (default) Previous transmission failed or first transmission after reset

LHI 5 r Limp Home monitor0B (default) Normal mode operation1B Limp Home Mode

STB 4 r Standby mode monitor0B Normal mode operation1B (default) Stand-by mode

VSMON 3 r VS monitor0B (default) VS always > VSMON since last Standard Diagnosis

readout1B VS < VSMON at least once

ERR_MUX 2:0 r Diagnosis of Channel n in error000B (default) No channel latched OFF001B Channel one latched OFF010B Channel two latched OFF011B Channel three latched OFF100B Channel four latched OFF101B Not used 110B Not used 111B More than one channel latched OFF

BTS54220-LBB


Data Sheet 60 Rev. 2.1, 2014-12-05

9.6.2 Errors Diagnosis

9.6.3 Warnings Diagnosis

SO 7 6 5 4 3 2 1 0 Default

0 0 0 1 ERR_COUNTERn 10H

Field Bits Type DescriptionERR_COUNTERnn = 4 to 1

3:0 r Diagnosis of Channel n0B (default) No failure1B Over temperature counter reached to nretry

SO 7 6 5 4 3 2 1 0 Default

0 0 1 0 ERRn 20H

Field Bits Type DescriptionERRnn = 4 to 1

3:0 r Warning Diagnosis of Channel n0B (default) No failure1B Over temperature counter > 0

BTS54220-LBB


Data Sheet 61 Rev. 2.1, 2014-12-05

9.7 SPI Configuration RegistersThe following table provides an overview on the registers available and the available addressing space.

9.7.1 Output Configuration Register

9.7.2 Input Status Register

9.7.3 Swap Configuration Register

Table 15 Register OverviewRegister name Register Bank Address SWCR.SWR bit ContentOUT 0 (na) 0 Output configurationOUT 0 (na) 1 Input statusSWCR 1 00 (na) Swap configurationLGCR 1 01 0 LED mode configurationLGCR 1 01 1 Gate Back Regulation configurationHWCR 1 10 (na) Hardware configurationDCR 1 11 (na) Diagnostic configuration

SWCR.SWR = 0Bit 7 6 5 4 3 2 1 0Name W = 1

R = 0RB 5 4 3 2 1 0 Default

OUT W/R 0 0 x OUT.OUTn 80H

SWCR.SWR = 1Bit 7 6 5 4 3 2 1 0Name W = 1

R = 0RB 5 4 3 2 1 0 Default

OUT R 0 LHI 1 OUT.INSTn 90H

Bit 7 6 5 4 3 2 1 0 DefaultName W = 1

R = 0RB ADDR 3 2 1 0

SWCR W/R 1 00 SWCR.SWR 1 0 0 C4H

BTS54220-LBB


Data Sheet 62 Rev. 2.1, 2014-12-05

9.7.4 LED Mode Configuration Register

9.7.5 Gate Back Regulation Register

9.7.6 Hardware Configuration Register

SWCR.SWR = 0Name W = 1

R = 0RB ADDR 3 2 1 0 Default

LGCR W/R 1 01 0 LGCR.LEDn 0 D0H

SWCR.SWR = 1Name W = 1

R = 0RB ADDR 3 2 1 0 Default

LGCR W/R 1 01 LGCR.GBRn DFH

Name W = 1R = 0

RB ADDR 3 2 1 0 Default

HWCR R 1 10 HWCR.RCR HWCR.COL HWCR.STB 0 E2H

W 1 10 HWCR.RCR HWCR.COL HWCR.RST HWCR.CTC -

BTS54220-LBB


Data Sheet 63 Rev. 2.1, 2014-12-05

9.7.7 Diagnosis Control Register

9.7.8 Configuration Register Bit Overview

Name W = 1R = 0

RB ADDR 3 2 1 0 Default

DCR R 1 11 DCR.SBM DCR.MUX F7H

W 1 11 0 DCR.MUX -

Field Bits Type DescriptionRB 6 rw Register Bank

0B (default) Read / write to OUT register1B Read / write to other registers

OUT.OUTnn = 4 to 1

3:0 rw Output Control Register of Channel n0B (default) channel is OFF1B Channel is ON

OUT.INSTnn = 4 to 1

3:0 r Input Status Monitor Channel n0B (default) Input signal is “low”1B Input signal is “high”

LGCR.LEDnn = 3 to 2

2:1 rw Set LED Mode for Channel n0B (default) Channel n is in bulb mode1B Channel n is in LED mode

LGCR.GBRnn = 4 to 1

3:0 rw Gate Back Regulation for Channel n0B Gate back regulation for Channel n is forced OFF1B (default) Gate back regulation for Channel n is active

HWCR.CTC 0 w Clear Thermal Counter0B (default) Thermal latches are untouched1B Command: Clear all thermal latches

HWCR.RST 1 w Reset Command0B (default) Normal operation1B Execute reset command

HWCR.STB 1 r Standby Mode0B Device is awake1B (default) Device is in Standby mode

HWCR.COL 2 rw Input Combinatorial Logic Configuration0B (default) Input signal OR-combined with according OUT register bit1)

1B Input signal AND-combined with according OUT register bitHWCR.RCR 3 rw Retry Counter Reset

0B (default) Retry Counter is reset only for HWCR.CTC=1 (and VDD reset)1B Retry Counter is reset for every IN-pin or OUT.OUTn “high” to “low”

transition for nretry < nretry,max and also for HWCR.CTC=1 (and VDD reset)

BTS54220-LBB


Data Sheet 64 Rev. 2.1, 2014-12-05

SWCR.SWR 1 rw Switch Register0B (default) OUT.OUTn and LGCR.LEDn can be written and read1B OUT.INSTn can be read and LGCR.GBRn can be written and read

DCR.SBM 3 r Switch Bypass Monitor2)

0B VDS < VDS(SB)1B VDS > VDS(SB)

DCR.MUX 2:0 rw Set Current Sense Multiplexer Configuration in OFF-state000B IS pin is high impedance001B IS pin is high impedance010B IS pin is high impedance011B IS pin is high impedance100B IS pin is high impedance101B IS pin is high impedance110B IS pin is high impedance111B Stand-by mode (IS pin is high impedance)

Set Multiplexer Configuration in ON-state000B Current sense of channel 1 is routed to IS pin001B Current sense of channel 2 is routed to IS pin010B Current sense of channel 3 is routed to IS pin011B Current sense of channel 4 is routed to IS pin100B IS pin is high impedance101B IS pin is high impedance110B IS pin is high impedance111B Stand-by mode (IS pin is high impedance))

1) In Limp Home Mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode.2) The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel

which is selected by the current sense multiplexer (DCR.MUX).

Field Bits Type Description

BTS54220-LBB

Application Description

Data Sheet 65 Rev. 2.1, 2014-12-05

10 Application DescriptionThe following figure describes a typical operating circuit. It shall not be considered as a warranty of a certainfunctionality, condition or quality of the device. The Table 16 shows suggested component values and purposes.

Figure 35 Application Circuit Example

SPI

VS

OUT4

OUT3

OUT2

OUT165W

27W

27W65W

IS

SO

SCLK

SI

CS

GND

LHI WD-OUTRLHI

VDD

GND

VDDCVDD

µCe.g. XC2267

VSS

VCC

Vbat

AD

5VRVDD

SPIRSO

RSI

RSCLK

RCS

GPIO IN2

IN3

IN1

WD-OUT

CVS1

CGND

IN4

CADC

Z1Z2CVS2

DGND

RIN

RIN

RIN

RIN

Application _220noED.emf

RR

EC

RG

ND

COUT

RSE

NS

E

R1

RA

DC

BTS54220-LBB

Application Description

Data Sheet 66 Rev. 2.1, 2014-12-05

Table 16 Suggested Component Values Reference Value PurposeRVDD 500 Ω Device logic protection (Size 1206 recommended)RIN 8 kΩ Protection of the µC during overvoltage, reverse polarity and

loss of groundR1 4.7 kΩ Protection resistor for overvoltage, reverse polarity and loss

of ground. Value to be tuned with µC specificationRIS 2.7 kΩ Sense resistor RADC 1 kΩ µC-ADC voltage spikes filtering RCS 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSCLK 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSO 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSI 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RLHI 8 kΩ Protection of the µC during overvoltage and reverse polarity CADC 1 nF µC-ADC voltage spikes filtering CVDD 100 nF Logic supply voltage spikes filtering CVS1 68 nF Battery voltage spikes filtering CVS2 100 nF Battery voltage spikes filtering COUT 10 nF For improved electromagnetic compatibility (EMC)CGND 8.2 nF Ground voltage spikes filtering (optional for improved

robustness against battery voltage transients)RGND 100 Ω Ground voltage spikes filtering (optional for improved

robustness against battery voltage transients)RREC 1 kΩ Ground voltage recycling path (optional for providing a

recycle path in case of loss of Battery)Z1 7 V Protection of µC during overvoltage. Zener diode Z2 P6SMB30 Protection of device during overvoltage. Zener diodeDGND BAS70 Protection of device during reverse polarity. Schottky diode

BTS54220-LBB

Package Outlines BTS54220-LBB

Data Sheet 67 Rev. 2.1, 2014-12-05

11 Package Outlines BTS54220-LBB

Figure 36 TSON-24-1 Package drawing

BTS54220-LBB

Package Outlines BTS54220-LBB

Data Sheet 68 Rev. 2.1, 2014-12-05

Figure 37 TSON-24 Package pads and stencil

Green Product (RoHS Compliant)To meet the world-wide customer requirements for environmentally friendly products and to be compliant withgovernment regulations the device is available as a green product. Green products are RoHS-Compliant (i.ePb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).Note: You can find all of our packages, sorts of packing and others in our Infineon Internet Page

“Products”: http://www.infineon.com/products.

http://www.infineon.com/products

Edition 2014-12-05Published byInfineon Technologies AG81726 Munich, Germany© 2014 Infineon Technologies AGAll Rights Reserved.

Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Legal Disclaimer for short-circuit capabilityInfineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below the threshold limit.

InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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