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Avionics sensor simulation and prototype design workstation

using COTS reconfigurable computing technology

James Falasco, GE Fanuc Embedded Systems

1240 Campbell RoadRichardson, Texas 75081

Abstract

This paper reviews hardware andsoftware solutions thatallowfor rapid

prototyping of newor modifiedembeddedavionics sensor designs,mission

payloads andfunctional sub assemblies.We define reconfigurable

computing in the contextof being able toplace various PMCmodules

depending upon mission scenarios ontoa base SBC(Single Board

Computer).This SBC couldbe either a distributedor sharedmemory archi-

tecture conceptand have either two or four PPC7447A/7448processor

clusters.In certain scenarios,various combinations of boards could be

combinedin order to provide a heterogeneous computing environment.

Keywords: Sensor simulation,reconfigurable computing,videocompres-

sion,video,reflective memory,payloadintegration,sensor fusion,high

speeddata acquisition,videosurveillance

1. Introduction

The design of avionics sensors andmission payloa ds can be a complex and

time-consuming process. However, the design cycle can be significantly

shortenedif the system designer has access toa flexible,reconfigurable

developmentenvironmentthatclosely mimics the capabilities and tech-

nologies of the deployedsystem.

By integrating various PMCmodules with a scalable,reconfigurable multi-

processor architecture,itis possible to create a developmenttool thatwill

allowthe system designer to rather quickly andaccurately simulate and

testwith real data sets the various sensor designs and mission compo-

nents tobe fielded.

Specifically,we present a rapidprototyping andrapid evaluation system

thatwill simplify the establishmentof performance requirements,andallow

the quick evaluation of hardware andsoftware components being

consideredfor inclusion in a new sensor system design or a legacy

platform upgrade.

2. An Open Systems, COTS Platform  

The system hardware andsoftware usedto evaluate sensor designs and

mission payloadcomponents and algorithms shouldbe open and recon-

figurable toallowfor the mixing andmatching of various vendor offerings.

Provision for hardware independence is critical,sin ce the hardware is very

likely torapidly evolve atthe pace of newcomputer technology.The

software infrastructure shouldbe scalable andflexible allowing the algo-

rithm developers the ability tospendtheir time and budgetaddressing the

importantfunctionality andusability aspects of the systems design.The

system proposedhere,a test andevaluation workstation builtaround

reconfigurable hardware anda component-basedsoftware toolset,

provides the necessary tools toensure the success andcosteffectiveness

of initial sensor design andpayloaddevelopment.

Atth e center of any scalable prototyping system is a reconfigurable multi-

processing CPU engine with associatedmemory.The system depictedin

Fig.1 provides developers a scalable environmentfor application design

andtest.A COTS single boardcomputer (SBC) tightly integratedto a PMC

FPGAcardfor design experimentation forms the core system.Other PMC

modules can then be selecteddepending on the type of sensor inputthat

needs tobe processed.

One of the main advantages of this approach is the ability to rapidly proto-

type mockups for testand evaluation withouta concern for the limitations

of embeddeddevelopmentatthis early stage.The COTS SBC shown has the

ability tohosttwo PMCmodules per card.The Video cardcan efficiently

manage real sensor inputcoming in from an E/O sensor/camera,andalso

display thatdata in a fused fashion.This approach allows the system

builder towork in the lab andthe f ieldusing the same hardware/software

environment.This system configuration alsoprovides the developer with a

testbed todefine/design newhardware requirements andprocessing

streams.

3. Prototyping System StructureModern embedded avionics sensor design is primarily driven by the goal of 

providing a net-centricflow of data from platform to platform.The achieve-

mentof this vision depends on transferring andprocessing vastamounts of 

data from multiple sources.Let’s examine how one coulduse this approach

tocontrol andmanage various sensors in a rapidprototyping environment.

As depictedin Figure 1,the hostserver for the embeddedavionics sensor

design workstation is a COTS Dual 7447APowerPCVMEbus SBC.The board’s

architecture provides a distributedprocessing environmentthatallows

scaling of multiple processing nodes toachiev e high performance for the

mostdemanding signal and imaging applications associatedwith various

sensor andmission payloaddesign requirements.

Fig.1. FPGAvision andgraphics platform

The COTS SBC architecture combinedwith the FPGA/Videocards allows for

seamless mapping of imaging applications oriented toward change detec-

tion andsensor fusion which will allowthe systems designer toview

multiple data streams in a simulations real time display environment.

The SBC implements processing nodes using the latestMotorola

7447A/7448PowerPC®processors running atup to a 1.4 GHz clock rate.

Using the distributedprocessing architecture of the SBC,one bridge chip

per node allows the FrontSide Bus (FSB) of each PowerPCtorun in MPX

mode up toits maximum rate of 133MHz. The high performance data

transfer mechanism facilitatedby the built-in 64-bitfull duplex crossbar in

the Discovery II bridge permits concurrentdata transfers between different

interfaces as well as transaction pipelining for same source and

destination transactions.

The prototyping architecture outlinedhere is basedon a combination of 

tightly integratedreconfigurable computing,video andgraphics.It will

place the embeddedavionics sensor design community in position toutilize

the proposedsystem architecture in developmentof the actual controller

for payloadpackages as well as the sensor itself and in its actual deploy-

mentintegration.Mostimportantly itwill allowfor cost-effectively

maintaining andextending the system when newtechnologies are avail-

able in the future.

3.1An Example: Infrared (IR)scene projection

Increasedsensor performance andbandwidth has begun tooverwhelm

existing backendprocessing capability.Current testand evaluation

methods are notadequate for fully assessing the operational performance

of imaging infraredsensors while they are installedon the weapon system

platform.However,the use of infrared(IR) scene projection in testand

evaluation can augmentandredefine test methodologies currently being

usedto testandevaluate forwardlooking infrared(FLIR) andimaging

IR sensors.

One couldprojectaccurate,dynamicandrealisticIR imagery intothe

entrance aperture of the sensor,such thatthe sensor wouldperceive and

respondtothe imagery as itwouldto the real-worldscenario.This

approach includes development,analysis,integration,exploitation,training,

andtestand evaluation of groundandaviation basedimaging IR

sensors/subsystems/systems.This applies toFLIR systems,imaging IR

missile seekers/guidance sections, as well as non-imaging thermal sensors.

The systems approach proposedi n this paper has the scalability toaccom-

plish this type of reconfigurable sensor mix and match.Algorithms such as

the one depictedin Figure 2couldbe transformedinto a Mathlab®

Simulink®Blocksetfor easy execution in a reconfigurable system utilizing

FPGA-andPPC-basedcomputing elements.Embeddedavionics

HWIL Simulation demands include low latency,high data rates and

interfacing.It is essential tohave a capable platform for handling and

processing of the data streams.Tools mustalsocomplementthis sothat a

systems designer is able to constructthe final system leveraging design

tools,such as Mathlab andSimulink,with a reconfigurable

computing platform.

Fig.2. Example:sensor images

This approach allows one todemonstrate howalgorithms can be imple-

mentedandsimulatedin a familiar rapid application development

environmentbefore they are automatically transposedfor downloading

directly tothe distributedmultiprocessing computing platform. This

complements the establishedcont rol tools,which usually handle the

configuration and control of the processing systems leading toa tool suite

for system developmentandimplementation.

3.2The advantagesof FPGA Computing

As the developmenttools have evolved, the core-processing platform has

alsobeen enhanced.These improvedplatforms are basedon dynamically

reconfigurable computing,utilizing FPGAtechnologies andparallel

processing methods thatmore than double the performance anddata

bandwidth capabilities.This offers support for processing of images in

InfraredScene Projectors with 1024X 1024resolutions at400 Hz frame

rates.Simulink Blocksets couldaddthe programming involvedto organize

algorithms thatcouldthen be partitionedto operate on a multiprocessor

basedFPGA/PPCbasedconfiguration.

Another key componentof reconfigurable scalable embeddedavionics

sensor design andprototyping capability is access toFPGAbased

processing.FPGA(Field Programmable Gate Array) is definedas an array of 

logicblocks thatcan be ‘glued’ together (or configured) toproduce higher

level functions in hardware.Basedon SRAM technology,i.e., configurations

are definedon power up andwhen power is removedthe configuration is

lost– until itis ‘reconfigured’again. Since an FPGAis a hardware device,itis

faster than software.

The FPGAcan bestbe describedas a parallel device thatmakes it faster

than software.FPGAs as programmable “ASICs”can be configuredfor high

performance processing,excelling atcontinuous,high bandwidth applica-

tions. FPGAs can provide inputs from digital andanalog sensors —LVDS,

Camerink,RS170—with which the designer can interactively apply filters,

doprocessing ,compression,image reconstruction andencryption time of 

applications. Examples of the flexibility of this approach using COTS PMC

Modules hosted by a COTS multiprocessing base platform are shown in

Figures 3& 4.

Fig.3. Example:FPGAapplication.PMC FPGAprocessor for capture and

compression.PMCmodule for graphics anddisplay.

Fig.4. RS-170/MPEG-4video PMC.Integratedbundle of PMC,mezzanine and

MPEG-4.

3.3The ‘Mix and Match’ Platform Advantage

Today’s soldier,who is the ultimate customer of the embeddedsystems

designer,is facedwith a continuously fluidchain of worldevents. These

changing events are closely mappedintothe deploymentof various air,sea

andlandplatforms which contain the reconfigurable embeddedsystems

architecture under discussion in this paper.For example,basedon

changing mission requirements,any of the following three differentareas

mightbe neededby the soldier: sonar processing;SIGINT;or

videosurveillance.

The system designer addressing these defined application areas could

place various PMCmodules together in the prototyping system with relative

ease.Specifically,these applications mightcollectively require the following

listof PMCmodules:PMC#1—Graphics;PMC#2—VideoCompression;

PMC#3—Reflective Memory; PMC#4—1553;PMC#5—High Speed Data Acqui-

sition;PMC#6—Race++.Akey cornerstone of the ‘mix andmatch’strategy is

thatwhile the PMCmodule may change from application toapplication,the

core SBC‘multiprocessor’engine andits associatedsoftware tool chain

remains constant.The same can be saidfor the VME enclosure that

contains the processing cards.

Let’s nowexamine the application areas andunderstandhowwe could

place various PMCcombinations together toaddress the processing

requirements of each application.

3.4Sonar Processing: PMC #1—Graphics,PMC #5

—HighSpeed Data Acquisition

In this example the PMCGraphics cardwouldbe utilizedtodisplay sonar

waterfall display data perhaps with an overlay of tactical positions.The

High SpeedData Acquisition PMCcouldbe used tofacilitate the information

coming in from a high speedsensor interface.The combination of the two

modules hostedby the multiprocessor-enabledSBCcould move

from this application area toanother type of sonar processing,triggeredby

software or the base modules couldbe switchedto those shown in the

SIGINT example below.

3.5SIGINT: PMC #6—Race ++, PMC #3—Reflective memory

In a SIGINT application scenarioa RACE ++PMCmodule is tied toother

Race++peripherals allowing for interfacing while the reflective memory

module stores real time acquireddata thatcouldbe used for post

processing data analysis.

3.6Video Surveillance: PMC #2—Video Compression,PMC #4—1553

In the videosurveillance application area,the video compression PMC

module wouldpre-process andreduce the incoming data stream and pass

itto the multiprocessor base system for potential change detection

analysis.Then using the PMC1553module,one couldcommunicate toan

external avionics platform to perhaps control or guide ordnance

being placedupon the target under surveillance.

In each of the three examples above, the modules are interchangeable

depending upon the specificmission.This approach wouldallowthe soldier

tomove module packages between platforms achieving differentmission

scenarios through software loading while maintaining the core base multi-

processing andpackagedenvironment.

4. Conclusions

The goal of integrating a COTS system such as the one depicted here is to

allowdesigners touse the same environmentin the lab thatthey could

then take tothe fieldfor live data collection activity.This is of particular

value toa system engineer whocoulduse such an environmenttoperform

newdevelopmentactivities.Because of these eff iciencies,the

outlinedprototyping system wouldpay off in acceleratedproductdevelop-

menttime.

Systems designers are traditionally facedwith the challenge thattoday’s

sensors are generating data ata rate far faster than the backendend

systems are configuredto process.Combine this factwith the reality thata

sensor fusion “paradigm”is nowmandatory for designers wishing to turn

concepts intoreality rapidly.A key componenttoa flexible hardware

system,of course,is a software structure thatenables designers togofrom

their ideas andalgorithmicconcepts tocode or HDL.

Packaging of the system is largely dependenton the user’s requirements

for flexibility.Shouldthe user desire a system thatcan be scaledup by

adding additional cards,then a larger slot chassis couldbe configuredto

allowfor the addition of other cards.The key pointis that the core

hardware outlinednotonly has the potential for scalability by adding addi-

tional modules tothe base processing units,butthe entire system has

scalability as well.

PPC toPCI-X Bridge

(64360)

PPC toPCI-X Bridge

(64360)

1GHz7448or7447A

PowerPC

32MBUser Flash

32MBUser Flash

VMEBusP1

Up to

320MB/sPeak

Up to

1064MB/sPeak

PMC 1

PMC 2

PCI-XBridge

PCI-XBridge

NVRAM NVRAM

256 MB DDR 256 MB DDR

64-bit/133MHz

64-bit/133MHz

GigabitEthernet

MultifunctionSerial

GigabitEthernet

MultifunctionSerial

Up to1064MB/s

Peak

64-bit/133MHz

64-bit/133MHz

2eSSTVMEBridge

1GHz7448or7447A

PowerPC

OPTICAL FILTER

FILTER WHEEL

INTENSIFIER

FOCAL BACKPLANE

INTENSIFIERHIGH VOLTAGE

POWERSUPPLY

MICROCONTROLLERELECTRONICS

CCDIMAGING CHIP

ANDVIDEO ELECTRONICS

Video RateCamera

• 30framesper second

• Average image size (after registration):

642x 343pixels(8bit)

SpinningFilterWheel

• Creates6-band multispectralimage

Representative Sensor

Graphics PMC Module

High Speed Data Acquisition PMC Module

Multiprocessor BSP

Graphics SW Layer (OpenGL)

Adding Applications Layer

Mix & Match Platform Advantage Example 1Sonar Processing

SIGINT Reconfigurable S ystem Environment

RFReceiver

Real-TimeCapabilities

Real-time SignalDetectionSignalTrackingOperatorEvent MarkingSignalClassificationFusion of Data

Incoming Information Pre-Processed-Processed &Post Processed and storedforfuture analysis

DigitalCaptureof SignalData

Near-Real-TimeCapabilitiesAutomaticDetectionSignalLocalization

Displayand Analyze ResultsOperatorin the Loop

DataTapes

Processing &analysismaybe performed on the ground at near-real-timeratesbytransferof information from platform to ground station.

SignalAnalysis Function(SAF)

Mix & Match Platform Advantage Example 3Video Surveillance

1553 PMC

Video Compression PMC

Multiprocessor BSP

Adding Applications Layer

Battle Damage Assessment

ElectronicSurveillance

Cross-cueing Sensors

FOPEN Radar

Minefield Detection

LADAR

Data Link Compression

AllWeatherTarget Acquisition

SensorFusion

Mission Planning

UAV Application Examples

Existing Platforms& NewDesignsWill Continue Flying ForDecades

IncrementalMission Payload ResponsibilitiesWill Be Added

RequirementsForInteroperabilityContinue To Increase

DevelopersWillNeed To Shrink Payload Processing System

Conclusions

Overcoming Data Compression Bottlenecks

Pentium enabled SBC’sVMIC Product Line

PPC enabled SBC’s single,dual&quad configurationsRichardson Product Line

DisplayCapabilityCDI Product Line

Storage CapabilityCamarillo Product Line

1553Data link

Step3

The processof the first two stepsallows

the system developerto combine real

world data with simulated scenariosand

compare and contrast in orderto hone

overallsystem design efficiency

Step1

Data acquired in realtime

Step2

Data ispassed to PMC module to be

processed &on NexusSingle Board

Computer forbackend processing &

matching fordecisions(mission driven

scenarios)

PMC Module

Collect & Process Data fromsuspension subassembly

Data Acquisition Sensor

Solving The Bandwidth Problem

PPCtoPCI-XBridge

(64360)

PPCtoPCI-XBridge

(64360)

1GHz7448or7447A

PowerPC

32MBUser Flash

32MBUser Flash

VME BusP1

Up to320MB/s

Peak

Up to1064MB/s

Peak

PMC1

PMC2

PCI-XBridge

PCI-XBridge

NVRAM NVRAM

256MB DDR 256 MB DDR

64-bit/133MHz

64-bit/133MHz

GigabitEthernet

MultifunctionSerial

GigabitEthernet

MultifunctionSerial

Up to1064MB/s

Peak

64-bit/133MHz

64-bit/133MHz

2eSSTVME Bridge

1GHz7448or7447A

PowerPC

RS170PMC

Graphics PMC

FPGAPMC

1553Technology

Chassis Technology

Display Technology

VideoCompression

PMC

InputFormat

MatrixProcessor

DemeanWindowAverager

TargetWindowAverage

Background/Guard

WindowAverager

CrossProduct

Generator

BandInterleaved

ImageInput

RXImageOutput

VideoInputProcessing

VideoServer Application

WAVESoftware

Drivers(PCIBus)

MPEG-4Bit-stream

Input1MPEG-4Compression

Input2MPEG-4Compression

TS-PMCwith Stratix FPGA

RTPEncapsulatedMPEG-4Bit-stream

Server Configuration via TCP/IP

VideoServer CPU

Dual RS-170MezzanineFPGAPMC

VideoCompression PMCIntegratedBundle

VideoCompression Encoderwith HostDecode

Multiprocessor SBC

+ =+

VideoCameraAudioInput

• Capture• Filter,Format• Encrypt• Compress

GPU PMCOverlay

andDisplay

TS-PMCCapture

andCompress

VideoCameraAudioInput

TS-PMCCapture

andCompress

TS-PMCCapture

andCompress

TS-PMCCapture

andCompress

• Capture• Filter,Format• Encrypt• Compress

• GraphicGeneration• Overlay• Display

• GraphicGeneration• Overlay• Display

Thin Pipe Network

Encrypter WirelessNetwork

Multiprocessor SBC

Race ++ PMC Module

Reflective Memory PMC

Module

Multiprocessor BSP

Adding Applications Layer

Mix & Match Platform Advantage Example 2SIGINT