Spidergon a NoC for future SMP architecturesusers-tima.imag.fr/sls/petrot/Coppola_mpsoc04.pdf ·...

Spidergon a NoC for future SMP architectures

Marcello CoppolaAdvanced System Technology

2

Advanced System Technology Confidential

Progression of The Architecture

Vacuum tubes -- 1940 – 1950

Transistors -- 1950 – 1964

Integrated circuits -- 1964 – 1971

Microprocessor chips -- 1971 – present

uP1

uP3uP4

uP2

DisplaySub-

System

Video Encoder

InterfaceSub-

System

Clocks

MPEG

2

LMI

Blitter

EMI

Comms

DVD

ecoder

DACs

On-Chip Network

3


Typical Complex Multimedia Chip today:

AudioDecoder

AudioAudioDecoderDecoder

ST220ST220

Display UnitDisplay UnitAudio

EncoderAudioAudio

EncoderEncoder

ST220ST220

VideoEncoder

VideoVideoEncoderEncoder

ST220ST220 DVDecoder

DVDVDecoderDecoder

MPEGVideo

Decoder

MPEGMPEGVideoVideo

DecoderDecoderEMIEMIFDMAFDMA COMMsCOMMs LLILLI

Central CPU:

SH4Central Central CPU: CPU:

SH4SH4FEIFEI

CPXMCPXMHDDIHDDI

LL

MM

II

USBUSBH/DH/D

STBus Interconnect

STm8000 block diagram

Not scalable/flexible enough

4


Multi Processor SoCScalability is limited by:– Complexity– Programming models limitations– Inadequacy of on-chip communication– Power consumption, both dynamic and static

Costs issues– NRE as complexity increases– SW complexity and verification– HW verification time and costs

5


New challenging factorsEmbedded S/W content growing fast (very fast…)– Technological reasons

H/W NRE costs exponential growth (mask, design, etc.)=> ASSP’sDesign productivity gap, time to market, flexibility

– Growing services which require programmabilityCurrent application S/W complexity– Some internal examples

Set-top box: >1 million lines of codeDigital audio processing: >1 million lines of codeRecordable DVD: Over 100 person-years effortHard-disk drive: eS/W represents 100 person-years effort

– Multi-media mobile platforms, likely worse…

Programming Model for embedded platforms is key– Productivity for providers as well as for their clients

6


Solutions

Building multiprocessor SoC with highly symmetric IP blocks– Still accommodating heterogeneous system– Support for both symmetric multiprocessing and

classical approaches– Easier to design and verify separately and then

integrate with a well defined system templateFlexible interconnect fabrics– Introduction of Noc for SoC wide communication– Local ‘bus like’ communication structures can

still be used when required

7


Scalable MPSoc based on a NoC

ST2xx ST2xxST2xx

SnoopInterconnect Unit

MP Interrupt and Message passing Unit

MP-DMA

MP-SDI

MP-DSU

L1 cache L cacheL1 cache

Ch0Ch1ChN

Ext I

ntlin

es

Mul

ticor

em

essa

ging

(e.g

.N

UM

A)

Jtag

HW Accellerators

Display Unit

EMI COMMS USB H/D LLI

NoC InterconnectLMIHost CPU

FDMA

SHE

ILA

...

8


uP1

uP3uP4

uP2

DisplaySub-

SystemVideo Encoder

InterfaceSub-

System

Clocks

MPEG

2

LMI

Blitter

EMI

Comms

DVD

ecoder

DACs

On-Chip Network

A NoC Motivating example:STm8000 recordable dvd chipStbus based,more than 40 bus targets/initiatorsLarge chip areacross-talks problemsclock skew

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Spidergon: main goals

NoC ARCHITECTURE DEFINITION

To be low cost as main drive-factor

To differentiate from literature

To exploit OCTAGON as starting point

with STBus experience in mind

10


applicationtransportnetworkdata linkphysical

applicationtransportnetworkdata linkphysical

SubSystem

SubSystem

SubSystem

SubSystem

SubSystem

On-ChipNetwork

networkdata linkphysical








NoC is a set of

Router up to Layer 3 - NI Layer 4

Transport packet from

sending to receiving sub

systems (uP,IP,etc.)

On-chip RoutersNetwork Interfaces

Packet

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NoC topology: our idea

We think that a fixed topology approach leads to an optimized

and low cost NoC

We want a regular topology

We look for a good complexity vs. performance trade-off

– Complexity: router arity, number of links, routing

– Performance: diameter, connectivity, scalability

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Spidergon topology (1/2)The Spidergon network connects a generic even number of nodes

N as a bi-directional ring in both clockwise, and anti-clockwise

directions with in addition a cross connection for each couple of nodes.

Each node i, with 0≤ i <N is connected by two unidirectional links to:

1. node (i+1) mod N (clockwise)

2. node (i-1) mod N (anti-clockwise)

3. node (i+N/2) mod N (cross)

0 1 2 3 4

5

6

7

89101112

15

14

13

13


Spidergon topology (2/2)

SPIDERGONTOPOLOGY

PROPERTIES

Number of nodes: N = 2n with n=1,2,3,… e.g. N=14, n=7

Diameter: d = ceil(N/4) hops e.g. d=4 hops

Number of links: L = 3/2 N e.g. L=21

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N = 20 | L = 30dmax = 5 hops

Spidergon vs. 2D-Mesh (1/3)

N = 20 | L = 31dmax = 7 hops

15


Spidergon vs. 2D-Mesh (2/3)Links L vs. Nodes N

0

20

40

60

80

100

120

0 10 20 30 40 50 60 70

Nodes N

Link

s L

2D-Mesh SPIDERGON

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Spidergon vs. 2D-Mesh (3/3)(Normalized) Max delay d x Links L

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 10 20 30 40 50 60 70

Nodes N

d x

L

2D-Mesh SPIDERGON

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Spidergon Communication: Three Levels

Message– Unit of communication at the application level

Packet– Unit of transmission– Each packet has a header and is routed

independently– Large messages partitioned into multiple packets

Flit– Unit of flow control– Each packet divided into flits that follow each other

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Spidergon router design

Routing: virtual wormhole (pipeline + low buffer cost)

Routing: NO adaptive (ordered peer-to-peer transmission)

Routing: NO table-based (area cost)

Queuing: to explore the design space (output)

Error recovery: NO for the moment

Control flow node-to-node: very simple REQ/ACK

19


Spidergon packetSpidergon supports variable length packetsA packet is composed by flitsFlit Type: first – subsequent – last– Flit type is out of band Router-to-Router (2

bits)

2Flit Type

packet

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Spidergon first flitIn the first flit (Network dependent part of the packet header):– 1 bit for direction– ceil(log2d) bits for destination id

packet

DirDestid

header

21


Spidergon router scheme

SWITCHMATRIX

Out

put p

orts

Scheduling

Out queue

from NI

from R

from A

from L

Ligh

t R

outin

g L

ogic to NI

to R

to A

to L

Inpu

t por

ts

Arbitration

Input Status Register

2 VC

2 VC

2 VC

2 VC

22


Deadlock issue (1/3)

………….. ACROSS links

…….

…….

RIGHT links

LEFT links

Channel Dependency Graph of Spidergon

Cycles in CDG: NO DEADLOCK FREE [W.J. Dally]

Spidergon is a bidirectional ring with ACROSS links

Link ACROSS used only as first hop

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Deadlock issue (2/3)

To solve deadlock just consider bidirectional ring

Simple use of 2 Virtual Channels for deadlockavoidance

> 0 then VC1

(#dest - #node)

< 0 then VC2

Cycles of CDG broken thanks to 2 VCs

24


OccN OccN partnersOpen source -> http://occn.sourceforge.net

Bologna University

Ancona University

Pisa University

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Network interfaceNetwork Interface is the “access” to the NoC

It hides network dependent aspects

It cover the Transport Layer connection handling, (dis)assembling of messages, higher level services (end-to-end protocol)

Literature: effort to be OCP-IP compliantOpen Core Protocol International Partnership (OCP-IP)

AST target is STBus (Type3)

26


ConclusionsAST NoC activity

Spidergon NoC: a low cost architecture

novel NoC topology

relative routing algorithm

simple router scheme

Spidergon NoC: OCCN router model

very flexible TLM-CA SystemC model

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