S.Padmini SRM University Page 1 · SRM University Page 14 •74HC190 (Synchronous [BCD] Decade...

S.Padmini Assistant Professor/EEE Dept. of EEE SRM University


COUNTERS NEED FOR COUNTERS:

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting.A timing problem might require that a high-frequency pulse train, such as the output of a 10-MHz crystal oscillator, be divided to produce a pulse train of a much lower frequency, say 1 Hz. This application is required in a precision digital clock, where it is not possible to build a crystal oscillator whose natural frequency is 1 Hz.

A sequencing problem would arise if, for instance, it became necessary to apply

power to various components of a large machine in a specific order. The starting of a rocket motor is an example where the energizing of fuel pumps, ignition, and possibly explosive bolts for staging must follow a critical order.

Measuring the flow of auto traffic on roadway is an application in which an event

(the passage of a vehicle) must increment a tally. This can be done automatically with an electronic counter triggered by a photocell or road sensor. In this way, the total number of vehicles passing a certain point can be counted.

Counters are generally made up of flip-flops and logic gates. Like flip-flops,

counters can retain an output state after the input condition which brought about that state has been removed. Consequently, digital counters are classified as sequential circuits. While a flip-flop can occupy one of only two possible sattes, a counter can have many more than two states. In the case of a counter, the value of a state is expressed as a multidigit binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops that make up the counter. The number of states a counter may have is limited only by the amount of electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T flip-flops, which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how a J-K flip-flop works:

J input K input Output, Q

0 0 Q

0 1 0

1 0 1

1 1 not Q


T flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and toggle ([0,0] [1,1]) functions are used. Logic gates are used to decide when to toggle which outputs. Below is an example of a synchronous binary counter, implemented using J-K flip-flops and AND gate Difference between asynchronous and synchronous counters.

In an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop when it occurs. In a synchronous counter however, the external event is used to produce a pulse that is synchronised with the internal clock. An example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple counter is clocked by the output from the previous flip-flop. Only the first flip-flop is clocked by an external clock. Below is an example of a 4-bit ripple counter:

Digital ICs used in this chapter discussion

•74LS93A (4 Bit Asynchronous Binary Counter)

•74LS160 (Synchronous BCD Decade Counter/Asynchronous Clear)

•74HC161 (4Bit Synchronous Binary Counter/Asynchronous Clear)

•74HC163 (Synchronous 4 Bit Binary Counter/Synchronous Clear)


•74HC190 (Synchronous [BCD] Decade Up/DownCounter)

•74LS47 (Dual D Flip-Flop

Problems of asynchronous counters.

Although the asynchronous counter is easier to implement, it is more "dangerous" than the synchronous counter. In a complex system, there are many state changes on each clock edge, and some IC's (integrated circuits) respond faster than others. If an external event is allowed to affect a system whenever it occurs, a small percentage of the time it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. What is worse, these problems are difficult to test for and difficult to forsee because of the random time difference between the events.

Asynchronous counters:A binary ripple counter can be constructed using clocked JK or T flip-flops.When the output of a flip-flop is used as clock input for the next flip-flop, then the counter is called a ripple or asynchronous counter.

The A FF must change state before it can trigger B FF, and B FF has to change state before it can trigger C FF.The triggers move through FFs like a ripple in water. Usually a CLEAR input is applied to all the flip-flops before counting starts.

The 3-bit ripple counter circuit above has 23 different states, each one corresponding to a

count value. Similarly, a counter with n flip-flops can have 2n states. The number of states in a counter is known as its mod (modulo) number. Thus a 3-bit counter is a mod-8 counter.

Three bit asynchronours counter


• Here FFs are negatively edge triggered. CLK signal is supplied to only one flip-flop FF0. Every time on clock NT, FF0 will change state. So we have waveform of Q

0

• FF0 will act as the clock for FF1 and FF1 will act as clock for FF2. Each time the waveform Q

0 goes low Q

1 will change the state.

Propagation delay

The time required for a logic-level change to be transmitted through one or more digital elements.

Due to the “rippling” effect of toggling sequential FFs, there is a small delay associated

with this trggering event.The rippling effect is due to the input clock pulse triggering the first FF and then each additional FF triggering it’s adjacent neighbor. •Therefore, the switching of each FF is not instananeous.•This propagation delay is a disadvantage to using Asynchronous Binary Counters


4-Bit Asynchronous Counter

•Operation is the same as that of a 2 & 3-Bit Counters.The counter has 16 states instead of 4 & 8. •An additional FF is wired to the dual FFs of a 3-Bit Counter.Just like a 2 & 3 Bit Asynchronous Counters a Timing Diagram is used to analyze the counting sequence of the digital circuit

4-bit asynchrous binary counter and timing diagram


Calculating Total Propagation Delay (tp(tot))

To calculate the tp(tot) of an Asynchronous Binary Counter multiply the number FFs by the Propagation Delay (PD) of one digital device.

tp(tot) = nFF x PD

Calculating The Maximum Clock Frequency

To calculate the maximum clock frequency (fmax) of digital counter.

fmax = 1/tp(tot)

Determining the Number of States for an Asynchronous Binary Counter

To calculate number of states or count value for an Asynchronous Binary Counter:

states = 2n

“n” is the number of FFs

Asynchronous Decade Counters

An Asynchronous Decade Counter has an unique number states. The “modulus” is another way of describing an Asynchronous Decade Counter’s unique number of states. Counters can be designed to have a number of states in their counting sequence that is less than the maximum of 2n.The resulting sequence is called a “truncated” sequence.

Asynchronous Decade Counters continued

One common modulus for counters with truncated sequences is ten (called MOD 10). Counters with ten states in their sequence are called decade counters. The count sequence of zero (0000) through nine (1001) is a BCD (Binary Coded Decimal) decade counter. This counter is useful in display applications inwhich BCD is required for conversion to a decimal readout.


Partial Decoding Technique

•By wiring a NAND gate to Q1 and Q3 partial decoding is accomplished.Resets the counter to zero (0000) when the 10th clock pulse is reached. •Other counting sequences can be achieved using the Partial Decoding Technique

Asynchronous decade counter


SYNCHRONOUS COUNTERS

The term synchronous refers to events that have a fixed time relationship with each other.In synchronous counter, the clock pulses are applied to all the flipflops simultaneously. Hence there is minimum propagation delay.

2-bit synchronous counter

Timing diagram


3-BIT SYNCHRONOUS BINARY COUNTER

This counter uses a “AND” gate to detect Q0 and Q1 outputs of FF0 and FF1. This condition is unique because both outputs are “Hi” simultaneously. The “AND” is used to assure that FF2 toggles properly. The Timing Diagram is similar to a 3 Bit Asynchronous Binary Counter. The FFs are positive edge triggered devices.

3-bit synchronous binary counter

Timing diagram


4-BIT SYNCHRONOUS BINARY COUNTER

This counter uses an “AND” gates to detect Q0, Q1 and Q2 outputs of FF0 and FF1. This condition is unique because outputs are “Hi” simultaneously. The “AND” is used to assure that FF2 and FF3 toggles properly. The Timing Diagram is similar to a 4 Bit Asynchronous Binary Counter. The FFs are positive edge triggered devices.

4-bit synchronous binary counter and timing diagram


4BIT SYNCHRONOUS DECADE COUNTER

This counter uses a “AND” gates and “OR” gates to detect Q0, Q1 and Q2 outputs of FF0, FF1 and FF2 as well as truncating to the appropriate count sequence (MOD 10). This condition is unique because outputs are “Hi” simultaneously. The “AND” is used to assure that FF2 and FF3 toggles properly and the “OR” gate for partial decoding the correct truncate count sequence(1001).

The Timing Diagram is similar to a 4 Bit Asynchronous Decade Counter.The FFs are positive edge triggered devices. The “AND” and “OR” gates assist in the Partial Decoding for truncating the sequence for MOD 10 counting. The Timing Diagram is used to show the “Decade” counting sequence of the synchronous counter.

UP/DOWN 3 BIT SYNCHRONOUS COUNTER

An Up/Down 3 Bit Counter is capable of progressing in either direction through a certain sequence. An Up/Down Counter is also known as “bidirectional counter.” A 3 Bit Binary counter advances updward in sequence (0,1,2,3,4,5,6,7). It advances downward in reverse sequence (7,6,5,4,3,2,1,0). The counter advances to next output state on the positive edge of the input clock.

3-bit up/down synchronous counter.


Timing diagram


MOD-N/Divide-by-N Counters

The number of states in a counter is known as its mod (modulo) number.

Normal binary counter counts from 0 to 2N - 1, where N is the number od bits/flip-flops in the counter. In some cases, we want it to count to numbers other than 2N - 1. This can be done by allowing the counter to skip states that are normally part of the counting sequence. There are a few methods of doing this. One of the most common methods is to use the CLEAR input on the flip-flops.

In the example above, we have a MOD-6 counter. Without the NAND gate, it is a MOD-8 counter. Now, with the NAND gate, the output from the NAND gate is connected to the asynchronous CLEAR inputs of each flip-flop. The inputs to the NAND gate are the outputs of the B and C flip-flops. So, all the flip-flops will be cleared when B = C = 1 (1102 = 610 ). When the counter goess from state 101 to state 110, the NAND output will immediately clear the counter to state 000. Once the flip-flops have been cleared, the B = C = 1 condition no longer exists and the NAND output goes back to high. The counter will therefore count from 000 to 101, and for a very short period of time, be in state 110 before the counter is cleared. This state is called the temporary state and the counter usually only remains in a temporary state for a few nanoseconds. We can essentially say that the counter skips 110 and 111 so that it goes only six different states; thus, it is a MOD-6 counter. We also have to note that the temporary state causes a spike


or glitch on the output waveform of B. This glitch is very narrow and will not normally be a problem unless it is used to drive other circuitry outside the counter. The 111 state is the unused state here. In a state machine with unused states, we need to make sure that the unused states do not cause the system to hang, ie. no way to get out of the state. We don't have to worry about this here because even if the system does go to the 111 state, it will go to state 000, a valid state) on the next clock pulse.

Comparison between asynchronous and synchronous counter

ASYNCHRONOUS COUNTER SYNCHRONOUS COUNTER

All the flipflops are not clocked All the flipflops are clocked simultaneously.

Simultaneously.

The delay time of all the flipflops are There is minimum propagation delay.

added. Therefore there is considerable

propagation delay.

The maximum frequency depends on The maximum frequency does not depend on

modulus. Modulus.

Logic circuit is very simple. Ciruit is complex

Minimum number of logic devices are More logic devices than ripple counter.

Needed.

Cheaper Costlier


DESIGNING OF COUNTERS

Design a synchronous sequential circuit whose state diagram is shown in Figure 1. The type of flip-flop to be use is J-K.

Figure 1:State diagram

From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section for this circuit. Two flip-flops are needed to represent the four states and are designated Q0Q1. The input variable is labelled x.

Table 9. State table.

Present State

Q0 Q1

Next State

x = 0 x = 1

0 0

0 1

1 0

0 0 0 1

1 0 0 1

1 0 1 1


1 1

1 1 0 0

We shall now derive the excitation table and the combinational structure. The table is now arranged in a different form shown in Table 11, where the present state and input variables are arranged in the form of a truth table. Remember, the excitable for the JK flip-flop was derive in

Table 10. Excitation table for JK flip-flop

Output Transitions

Q PQ(next)

Flip-flop inputs

J K

0 0

0 1

1 0

1 1

0 X

1 X

X 1

X 0

Table 11. Excitation table of the circuit

Present State

Q0 Q1

Next State

Q0 Q1

Input

x

Flip-flop Inputs

J0 K0 J1 K1

0 0

0 0

0 1

0 1

1 0

0 0

0 1

1 0

0 1

1 0

0

0

1

0

0 X 0 X

0 X 1 X

1 X X 1

0 X X 0

X 0 0 X


1 0

1 1

1 1

1

1 1

0 0

1

0

1

X 0 1 X

X 0 X 0

X 1 X 1

In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in the present state to 0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first row under J1 and K1. This process is continued for each row of the table and for each flip-flop, with the input conditions as specified in Table 10.

The simplified Boolean functions for the combinational circuit can now be derived. The input variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from the truth table is plotted on the Karnaugh maps shown in Figure 2.

Figure 2. Karnaugh Maps

The flip-flop input functions are derived:

J0 = Q1*x' K0 = Q1*x

J1 = x K1 = Q0'*x' + Q0*x = Q0x


Note: the symbol P is exclusive-NOR.

The logic diagram is drawn in Figure 3

Figure 3. Logic diagram of the sequential circuit.

Design a 3-bit binary counter.


State diagram of a 3-bit binary counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are taken off each flip-flop in the counter). The next state of the counter depends entirely on its present state, and the state transition occurs every time the clock pulse occurs.

Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table, which is derived from the state diagram

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

Since there are eight states, the number of flip-flops required would be three. Now we want to implement the counter design using JK flip-flops.

Next step is to develop an excitation table from the state table

Excitation table

Output State Transitions Flip-flop inputs


Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

J2 K2 J1 K1 J0 K0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

0 X 0 X 1 X

0 X 1 X X 1

0 X X 0 1 X

1 X X 1 X 1

X 0 0 X 1 X

X 0 1 X X 1

X 0 X 0 1 X

X 1 X 1 X 1

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a simplified Boolean expression for each flip-flop input.


Figure 20. Karnaugh maps

The 1s in the Karnaugh maps are grouped with "don't cares" and the following expressions for the J and K inputs of each flip-flop are obtained:

J0 = K0 = 1

J1 = K1 = Q0

J2 = K2 = Q1*Q0

The final step is to implement the combinational logic from the equations and connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary counter is shown in


Design a 3 bit binary counter using T flip-flops.

Excitation table.

Output State Transitions Flip-flop inputs

T2 T1 T0

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0 0 0

0 0 1

0 0 1

0 1 0

0 0 1

0 1 1


0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

0 0 1

1 1 1

0 0 1

0 1 1

0 0 1

1 1 1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean expressions, which is shown in Figure 23.

Figure 23. Karnaugh maps

The following expressions are obtained:

T0 = 1; T1 = Q0; T2 = Q1*Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of the counter is as shown below


Logic diagram of 3-bit binary counter.

The Shift Register

The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle, hence the name shift register. It basically consists of several single bit "D-Type Data Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. The data bits may be fed in or out of the register serially, i.e. one after the other from either the left or the right direction, or in parallel, i.e. all together. The number of individual data latches required to make up a single Shift Register is determined by the number of bits to be stored with the most common being 8-bits wide, i.e. eight individual data latches.

Shift Registers are used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock (Clk) signal making them synchronous devices. Shift register IC's are generally provided with a clear or reset connection so that they can be "SET" or "RESET" as required.

Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being:

• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored data being available in parallel form.

• Serial-in to Serial-out (SISO) - the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control.


• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.

• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can be presented graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right, (right shifting).


Serial-in to Parallel-out (SIPO)

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops (FFA to FFD) have just been RESET (CLEAR input) and that all the outputs QA to QD are at logic level "0" i.e, no parallel data output. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. The logic "1" has now moved or been "shifted" one place along the register to the right as it is now at QA. When the third clock pulse arrives this logic "1" value moves to the output of FFC (QC) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level "0" because the input to FFA has remained constant at logic level "0".

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows.


Basic Movement of Data through a Shift Register

Clock Pulse No QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 5 0 0 0 0

Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1) are stored in the register and will remain there provided clocking of the register has stopped. In practice the input data to the register may consist of various combinations of logic "1" and "0". Commonly available SIPO IC's include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO)

This shift register is very similar to the SIPO above, except were before the data was read directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow


straight through the register and out of the other end. Since there is only one output, the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Register or SISO.

The SISO shift register is one of the simplest of the four configurations as it has only three connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format i.e. all the data bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out sequentially in the normal shift-right mode from the register at Q representing the data present at PA to PD. This data is outputted one bit at a time on each clock cycle in a serial format. It is


important to note that with this system a clock pulse is not required to parallel load the register as it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. The data is presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown below.


4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections, the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required.

Universal Shift Register

Today, high speed bi-directional "universal" type Shift Registers such as the TTL 74LS194, 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, and as a parallel-to-parallel multifunction data register, hence the name "Universal". These devices can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device.


4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory, delay information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division

Applications of Shift Registers

One of the most common uses of a shift register is to convert between serial and parallel interfaces. This is useful as many circuits work on groups of bits in parallel, but serial interfaces are simpler to construct. Shift registers can be used as simple delay circuits. Several bidirectional shift registers could also be connected in parallel for a hardware implementation of a stack.

SIPO registers are commonly attached to the output of microprocessors when more output pins are required than are available. This allows several binary devices to be controlled using only two or three pins - the devices in question are attached to the parallel outputs of the shift register, then the desired state of all those devices can be sent out of the microprocessor using a single serial connection. Similarly, PISO configurations are commonly used to add more binary inputs to a microprocessor than are available - each binary input (i.e. a switch or button, or more

http://en.wikipedia.org/wiki/Stack_%28data_structure%29


complicated circuitry designed to output high when active) is attached to a parallel input of the shift register, then the data is sent back via serial to the microprocessor using several fewer lines than originally required.

Shift registers can be used also as pulse extenders. Compared to monostable multivibrators, the timing has no dependency on component values, however it requires external clock and the timing accuracy is limited by a granularity of this clock. Example: Ronja Twister, where five 74164 shift registers create the core of the timing logic this way (schematic).

In early computers, shift registers were used to handle data processing: two numbers to be added were stored in two shift registers and clocked out into an arithmetic and logic unit (ALU) with the result being fed back to the input of one of the shift registers (the accumulator) which was one bit longer since binary addition can only result in an answer that is the same size or one bit longer.

Many computer languages include instructions to 'shift right' and 'shift left' the data in a register, effectively dividing by two or multiplying by two for each place shifted.

Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner to the earlier delay line memory in some devices built in the early 1970s. Such memories were sometimes called circulating memory. For example, the DataPoint 3300 terminal stored its display of 25 rows of 72 columns of upper-case characters using fifty-four 200-bit shift registers, arranged in six tracks of nine packs each, providing storage for 1800 six-bit characters. The shift register design meant that scrolling the terminal display could be accomplished by simply pausing the display output to skip one line of characters.[1]

Summary of Shift Registers

• Then to summarise. • A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each

data bit. • The output from each flip-Flop is connected to the D input of the flip-flop at its right. • Shift registers hold the data in their memory which is moved or "shifted" to their required

positions on each clock pulse. • Each clock pulse shifts the contents of the register one bit position to either the left or the

right. • The data bits can be loaded one bit at a time in a series input (SI) configuration or be

loaded simultaneously in a parallel configuration (PI).

http://en.wikipedia.org/wiki/Ronja_Twister

http://ronja.twibright.com/schematics/twister.png

http://en.wikipedia.org/wiki/Arithmetic_logic_unit

http://en.wikipedia.org/wiki/Delay_line_memory

http://en.wikipedia.org/w/index.php?title=DataPoint_3300&action=edit&redlink=1

http://en.wikipedia.org/wiki/Characters_per_line

http://en.wikipedia.org/wiki/Shift_register#cite_note-0


• Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).

• One application of shift registers is converting between serial and parallel data. • Shift registers are identified as SIPO, SISO, PISO, PIPO, and universal shift registers.

In the next tutorial about Sequential Logic Circuits, we will look at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop. This then produces another type of sequential logic circuit called a Ring Counter that are used as decade counters and dividers.

The Ring Counter

In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a serial-in to serial-out shift register, the same sequence of data will exit from the last flip-flip in the register chain after a preset number of clock cycles thereby acting as a sort of time delay circuit to the original signal. But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop circuit that "recirculates" the DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring Counter. Then by looping the output back to the input, we can convert a standard shift register into a ring counter. Consider the circuit below.

4-bit Ring Counter

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The synchronous Ring Counter example above, is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0". To achieve this, a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are applied. This then places a single logic "1" value into the circuit of the ring counter . On each successive clock pulse, the counter circulates the same data bit between the four flip-flops over and over again around the "ring" every fourth clock cycle. But in order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0"'s or all logic "1"'s outputted at each clock cycle would make the ring counter invalid.

This type of data movement is called "rotation", and like the previous shift register, the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram:

Rotational Movement of a Ring Counter


Since the ring counter example shown above has four distinct states, it is also known as a "modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency.

The "MODULO" or "MODULUS" of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A "mod-n" ring counter will require "n" number of flip-flops connected together to circulate a single data bit providing "n" different output states. For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require sixteen flip-flops. However, as in our example above, only four of the possible sixteen states are used, making ring counters very inefficient in terms of their output state usage.

Johnson Ring Counter

The Johnson Ring Counter or "Twisted Ring Counters", is another shift register with feedback exactly the same as the standard Ring Counter above, except that this time the inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below. The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard ring counter then its modulo number is halved. So a "n-stage" Johnson counter will circulate a single data bit giving sequence of 2n different states and can therefore be considered as a "mod-2n counter".


4-bit Johnson Ring Counter

This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter, "0001"(1), "0010"(2), "0100"(4), "1000"(8) and repeat, the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0". A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. For example, "1000", "1100", "1110", "1111", "0111", "0011", "0001", "0000" and this is demonstrated in the following table below.

Truth Table for a 4-bit Johnson Ring Counter

Clock Pulse No FFA FFB FFC FFD 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1


As well as counting or rotating data around a continuous loop, ring counters can also be used to detect or recognise various patterns or number values within a set of data. By connecting simple logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit can be made to detect a set number or value. Standard 2, 3 or 4-stage Johnson ring counters can also be used to divide the frequency of the clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs are also available.

A 3-stage Johnson Ring Counter can also be used as a 3-phase, 120 degree phase shift square wave generator by connecting to the data outputs at A, B and NOT-B. The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used as a synchronous decade counter/divider circuit. The smaller 2-stage circuit is also called a "Quadrature" (sine/cosine) Oscillator/Generator and is used to produce four individual outputs that are each "phase shifted" by 90 degrees with respect to each other, and this is shown below.

2-bit Quadrature Generator

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Output A B C D QA+QB 1 0 0 0 QA+QB 0 1 0 0 QA+QB 0 0 1 0 QA+QB 0 0 0 1 2-bit Quadrature Oscillator, Count Sequence

As the four outputs, A to D are phase shifted by 90 degrees with regards to each other, they can be used with additional circuitry, to drive a 2-phase full-step stepper motor for position control or the ability to rotate a motor to a particular location as shown below.

Stepper Motor Control

2-phase (unipolar) Full-Step Stepper Motor Circuit

The speed of rotation of the Stepper Motor will depend mainly upon the clock frequency and additional circuitry would be require to drive the "power" requirements of the motor. As this section is only intended to give the reader a basic understanding of Johnson Ring Counters and

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its applications, other good websites explain in more detail the types and drive requirements of stepper motors.

Johnson Ring Counters are available in standard TTL or CMOS IC form, such as the CD4017 5-Stage, decade Johnson ring counter with 10 active HIGH decoded outputs or the CD4022 4-stage, divide-by-8 Johnson counter with 8 active HIGH decoded outputs.

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