Software Configuration Management: Build Control
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Jump to first page (C) 1998, Arun La khotia 1 Software Configurati on Management: Build Control Arun Lakhotia University of Southwestern Louisiana Po Box 44330 Lafayette, LA 70504, USA [email protected]
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Software Configuration Management: Build Control. Arun Lakhotia University of Southwestern Louisiana Po Box 44330 Lafayette, LA 70504, USA [email protected]. Software Configuration Management. Practice of handling changes systematically Three components Build control Version control - PowerPoint PPT Presentation
Transcript of Software Configuration Management: Build Control
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(C) 1998, Arun Lakhotia
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Software Configuration Management: Build Control
Arun Lakhotia
University of Southwestern Louisiana
Po Box 44330
Lafayette, LA 70504, USA
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(C) 1998, Arun Lakhotia
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Software Configuration Management Practice of handling changes
systematically Three components
Build control Version control Change control
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(C) 1998, Arun Lakhotia
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Build control
Maintaining the consistency between components, in particular the derived components.
Derived components Executables Hardcopy manuals Compact Disk Test results and summaries
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Dynamic dependencies
User Requirements
Test results
Test cases
Executable
Hardcopy document
Code
Electronic document
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Need for automated support Forgettng to create “derived
components” leads to incosistent executables, manuals, etc.
Creation of “derived components” manually is tedious, repetituous, and boring.
The relationship (inputs, outputs, transforms) are static
Over time one forgets the mechanisms for transforming inputs to outputs
The same transformation sequence can be applied else where.
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General pattern of deriving components
C1
C2
C3
C4
C5 C6
C7
I2
I1
I3
I4T4
T3
T2
T1T5 T6
D0
Ti: Transformers
Ci: Input components
Ik: Intermediate components
Di: Output (final) component
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Specific example: Deriving executable
WordDriver.c
WordDriver.h
acc
acc
acc
WordFile.c
WordFile.o
WordDriver.o
WordFile.h
Library
WordDriver
If any of the .c or .h file changes then WordDriver should
be recreated
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Information needed to build components The sources The targets The rules used to create
targets from sources Example
Source: file.c file.h Target: file.o Rule: acc -c file.c
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Make: A tool to manage builds
Requires Components Dependencies Transformation rules
Provides Language to describe the above Language allows expression of
very general rules Will check for consistency
between sources and targets Will invoke commands
necessary to create targets from sources
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Make language
Target ‘:’ source1 source2 source3
ruleTab
file.o : file.cacc -c file.c
Tab
WordDrive.o: WordDriver.c WordFile.h
acc -c WordDriver.c
WordFile.c: WordFile.c WordFile.h
acc -c WordFile.c
WordDriver: WordDriver.o WordFile.o
acc -o WordFile WordDriver.o WordFile.o
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Using Make Create Makefile. Place the dependencies
and generation rles in it. Run Make
% rm *.o % make WordDriver
Make will invoke the following commandsacc -c WordFile.c
acc -c WordDriver.c
acc -o WordFile WordFile.o WordDriver.o
% make WordDriver
Make will say‘WordDriver’ is up to date.
% touch WordFile.c (mark the file as changed)
% make WordDriver
acc -c WordFile.c
acc -o WordFile WordFile.c WordDriver.c
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How make detects change?
Make compares the date of creation of the sources and targets
If a source is more recent than a target, it assumes that the source has changed and that the target should be recreated
What are the drawbacks of this logic?
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Builtin rules
Make has a language to express dependencies based on file extensions .c, .o, .h, .etc
It has some predefined rules to create object files and executable files for various programming languages
So it can do a lot of processing without a Makefile
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Using Built-in rules
Assume Makefile has no rule for Formatter.o% make Formatter.o
cc -sun4 -c Formatter.c How do you say which
compiler to use? Introduce the following line in
the MakefileCC= gcc
It says use “gcc” for compiling. How do you provide compiler
options? Assign option values to
CFLAGSCFLAGS= -DFLAG=1 -g
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Using Make variables
CC and CFLAGS are make variables
You can introduce your own make variables
How do you assign value to a variable?VARIABLE= value
How do you USE value of a variable?$(VARIABLE) gives the variables
value. Variables can be used to
reduce repetition in Makefiles
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Example Makefile
# EXEC gives the name of the executable
EXEC = WordDriver
# The variable OBJS gives the name of the .o files needed to
# create the executable
OBJS = WordFile.o WordDriver.o
# The following define CC and CFLAGS to be used for compiling
# and linking the files
CC = gcc
CFLAGS = -g
# The following rule states how to generate $(EXEC) from $(OBJS)
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS)
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Using Make for testing
Components Input file: .dat Output file: .res
Dependencies:Program “pgm” transforms Input
file to Output file Transformation rule
% pgm input.dat > output.res Test case files:
file1.dat, file2.dat, file3.dat …file1.res : file1.dat
pgm file1.dat > file1.res
file2.res: file2.dat
pgm file2.dat > file2.res
...
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Introducing transformation rules Rule for transforming .dat file
to .res file.
% is a pattern match symbol.
%.res matches with any file name with .res extension.
The rule says a file “xxx.res” can be created from “xx.dat”
$< represents the source
$@ represents the target
%.res : %.dat
pgm $< > $@
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Generating filenames in Makefile You may like to generate the name
of .o file from the name of .c file, instead of hardcoding them.
This can be achieved by doing substitution within a pattern match variable, as below.
$(SRC:%.c=%.o) replaces all names with .c to names with .o. The match is performed a “word” at a time.
SRC = file1.c file2.c file3.c
OBJS = $(SRC:%.c=%.o)
EXEC = pgm
$(EXEC) : $(OBJS)
$(CC) -o $(EXEC) $(OBJS)
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Generating source filenames
Even typing in the name of the source files is not always desirable
One may want the names to be picked up from the directory
This is particularly useful for testcase files
In the following the suffix “:sh” says that execute the value being assigned to TESTCASES as a shell command and assign the output to TESTCASES.
Names of .res files are then generated from the names of .dat files
TESTCASES:sh = echo *.dat
RESFILES = $(TESTCASES:%.dat=%.res)
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Generating .h dependencies
The .o <-- .h dependency can be generated automatically using makedepend.% makedepend f1.c f2.c f3.c …
modifies the Makefile and introduces .o/.h dependency.
SRCS= f1.c f2.c f3.c
makedepend:
makedepend $(SRCS)
To generate the dependencies introduce
the above in your Makefile and give
the following command:
% make makedepend
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Summary: Make
Make provides a language to describe chains of dependencies and transformation rules to generate derived components
The transformation rules can be written for an individual set of files or for a whole class of files
Its language provides macro variables, mechanism to use pattern match to substitute values in variable, and for assigning output of shell command to a variable.
