Software Architecture Overview

CCU EE&CTR 1

Software Architecture Overview

Nick Wang & Ting-Chao HouNational Chung Cheng University

Control Plane-Platform Development Kit

CCU EE&CTR 2

Outline Managing Data Structures Microblock Core Component CP-PDK Overview Control Plane PDK Architecture

Control Plane Module Transport Plug-in Forwarding Plane Module

CPPUI

CCU EE&CTR 3

Managing Data Structures

Linked List Management Structure Ring Buffers SRAM Q_Array Controller The Many-to-One Problem

CCU EE&CTR 4

Memory Resource Utilization in Processing a Packet

Ethernet HeaderIPv4 Header

Payload OffsetSize

3FF02030...…...

N

Prefix Next-hop-idInterface#

FlagsDMAC…

Ethernet HeaderIPv4 Header

Offset, sizeHeader-Type

IPv6Next-hop-id N

Dl_buf_handleDl_next_blad

Source(1)

Classify(2)

IPv6(3)

Encap(4)

Sink(5)

Packet Processing Flow

Handle HOffsetSizePort

QueueManagerRX

MSFSPI

ProcessingScheduling

ShapingTransmit

TXMSFSPI

DRAM SRAM

Packet Buffer Buffer Descriptor

Route Table Next-Hop

Microengine ResourceLocal Memory GPRs

Header Cache Meta-Data DL_state

Microengine PacketProcessing Microblock-group

Descriptor Descriptor

Scratch orNextNeighbor

Ring

Scratch Ring

Ring Buffer Ring Ring

CCU EE&CTR 5

Linked List Management Structure

Head: A

Tail: D

Q_Count: 4

Cell_Count: N/A

EOP: 1

Buffer B Buffer C Buffer D No Link

A: B: C: D:

Q_Descriptor

Head: A

Tail: Z

Q_Count: 5

Cell_Count: N/A

EOP: 1

Buffer B Buffer C Buffer D Buffer Z

A: B: C: D:

Q_Descriptor

No Link

4 Links

5 Links

Enqueue之前的Transmit Queue

Enqueue之後的Transmit Queue

Z:

CCU EE&CTR 6


Head: A

Tail: D

Q_Count: 4

Cell_Count: N/A

EOP: 1

Buffer B Buffer C Buffer D No Link

A: B: C: D:

Q_Descriptor

Head: B

Tail: D

Q_Count: 3

Cell_Count: N/A

EOP: 1

Buffer C Buffer D No Link

B: C: D:

Q_Descriptor

4 Links

3 Links

Dequeue之前的Transmit Queue

Dequeue之後的Transmit Queue

CCU EE&CTR 7


Head: A

Tail: W

Q_Count: 5

Cell_Count: 4

EOP: 0

Buffer B Buffer C Buffer D Buffer T

A: B: C: D:

Q_Descriptor

Buffer U Buffer V Buffer W No Link

T: U: V: W:8 Links

SOP:Cell 1 Cell 2 Cell 3 EOP:Cell 4

Head: B

Tail: W

Q_Count: 5

Cell_Count: 3

EOP: 0

Buffer C Buffer D Buffer TB: C: D:

Q_Descriptor


T: U: V: W:7 Links

Cell 2 Cell 3 EOP:Cell 4

CCU EE&CTR 8


Head: D

Tail: W

Q_Count: 5

Cell_Count: 1

EOP: 1

Buffer TD:

Q_Descriptor


T: U: V: W:5 Links

EOP:Cell 4

Head: T

Tail: W

Q_Count: 4

Cell_Count: N/A

EOP: 0

Q_Descriptor


T: U: V: W:

4 Links

CCU EE&CTR 9

Ring and linked list Ring

Communication mechanism Fixed-Size Easy for maintenance Next-neighbor register, scratchpad,

SRAM

Linked List Packet buffering Variable-length SRAM

CCU EE&CTR 10

Enqueueing to Cached Q_Array

Q1 0

Q3 1

Q26 15

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Q1 0

Q3 1

Q26 15

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0x1100 20x10000

0x4000 20x30001

63

0x1900 30x10000

0x4000 20x30001

63

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Entry Head Tail Q_Count

Entry Head Tail Q_CountEntry

EntryQ# CAM

Q# CAM

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.

0x1000, 0x1100, 2

0x3000, 0x4000, 20x1600, 0x1700, 2

0x1000, 0x1100, 2

0x3000, 0x4000, 20x1600, 0x1700, 2

LRUQ0Q1Q2Q3Q4

Q0Q1Q2Q3Q4

ENQ Q1, 0x1900 Cached Q_Array Before

Cached Q_Array After

CCU EE&CTR 11

Enqueueing to Non-Cached Q_Array

Q1 0

Q3 1

- 15

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Q26 0

Q3 1

- 15

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0x1900 30x10000

0x4000 20x30001

- --63

0x1700 20x10000

0x4000 20x30001

- --63

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EntryQ# CAM

Q# CAM

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0x1000, 0x1100, 2

0x3000, 0x4000, 2

0x1600, 0x1700, 2

0x1000, 0x1100, 3

0x3000, 0x4000, 2

0x1600, 0x1700, 2

LRUQ0Q1Q2Q3Q4

Q0Q1Q2Q3Q4

Non-Cached Q-Array Before

Q-Array after Q_Descriptor Read

Enqueue後的SRAM

SRAM

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Q26

2

0x2000 30x10000

0x4000 20x30001

- --63

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Entry Head Tail

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Q26 0

Q3 1

- 15

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EntryQ# CAM

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Q26

ENQ Q26, 0x2000

Read_Q

Write_Q

Q_Count

CCU EE&CTR 12

Dequeueing to Cached Q_Array

Q1 0

Q3 1

Q26 15

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Q1 0

Q3 1

Q26 15

.

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0x1900 20x10000

0x4000 20x30001

63

10x11000

0x4000 20x30001

63

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EntryQ# CAM

Q# CAM

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0x1000, 0x1900, 2

0x3000, 0x4000, 20x1600, 0x1700, 2

0x1000, 0x1900, 2

0x3000, 0x4000, 20x1600, 0x1700, 2

LRUQ0Q1Q2Q3Q4

Q0Q1Q2Q3Q4

DNQ Q1, 0x1000

Q_Array BeforeSRAM

Q_Array After

CCU EE&CTR 13

Dequeueing to Non-Cached Q_Array

Q1 0

Q3 1

- 15

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Q26 0

Q3 1

- 15

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.

0x1900 20x10000

0x4000 20x30001

- --63

0x1900 20x16000

0x4000 20x30001

- --63

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EntryQ# CAM

Q# CAM

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0x1000, 0x1100, 2

0x3000, 0x4000, 2

0x1600, 0x1700, 2

0x1000, 0x1900, 3

0x3000, 0x4000, 2

0x1600, 0x2000, 3

LRUQ0Q1Q2Q3Q4

Q0Q1Q2Q3Q4

Q_Array Before

Q_Array after Q_Des Read

Enqueue後的SRAM

SRAM

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Q26

2 0x1700 20x16002

10x20000

0x4000 20x30001

- --63

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Entry Head Tail

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32

Q26 0

Q3 1

- 15

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EntryQ# CAM

2

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Q26

ENQ Q26, 0x2000

Write_Q

Read_Q

CCU EE&CTR 14

The Many-to-One Problem

EnQDeQ

Flow19

Flow101

Flow8

Flow2

Flow76

Queue43

Queue59

Queue111

Queue2

Queue3

EnQDeQ

Flow19

Flow101

Flow8

Flow2

Flow76

Queue59

Queue2

Many-to-Many

Many-to-One

CCU EE&CTR 15

Elements of the Intel IXA Portability Framework

Control Plane Protocol Stacks

Control Plane PDK

Core Components

Core Component Infrastructure Library

Resource Manager Library

Microblock Infrastructure Library

MicroBlock

MicroBlock

MicroBlock

ExternalProcessors

IntelXscale Core

(Control Plane)

Microengine(Data Plane)

Data Plane Libraries

OSSL

CCU EE&CTR 16

Microblock A building block represents a unit of pack

et-processing functionality IPV4 routing, Ethernet bridging

Intel Provides two kinds of building block Packet Processing Microblock Driver Microblock

CCU EE&CTR 17

Core component overview During initialization, each core component doe

s the following: Sets up memory for shared tables Patches symbols

Processing exception packets Non-IP Packets Packets with no route information Packets that require fragmentation Packets for local IP addresses Packets with IP options

CCU EE&CTR 18

Core component Functions Configures its microblock (static configuration by m

eans of imported variables and dynamic configuration through control blocks).

Initializes and maintains common data structures that may be updated by other applications.

Provides exception as well as control message handler to process packets/messages sent by the microblock.

CCU EE&CTR 19

Core component overview Core components need to register different typ

es of handlers. Packet Handlers Message Handlers

init() and fini() Functions ix_error ix_cc_<component-name>_init() ix_error ix_cc_<component-name>_fini()

CCU EE&CTR 20

CP-PDK Overview Three logical operational components

Control Plane Control and configure the Forwarding Plane Signaling and routing protocol

Forwarding Plane Manipulate the network traffic Forwarding, classification, filtering

Management Plane Manage the control and forwarding planes Start or stop routing process Performance logging Control Plane

Forwarding Plane M

anag

emen

t Pla

ne

CCU EE&CTR 21

NPF (Network Processing Forum) API

Standardized the APIs within the three planes mix and match components available from

different vendors presents a flexible and well-known

programming interface to the control plane applications

the protocol stacks and network processors available can be easily integrated with the NPF APIs

CCU EE&CTR 22

Control Plane PDK Architecture

CCU EE&CTR 23

Control Plane PDK Architecture

TransportPlugins

Forwarding Plane

TransportPlugins

Forwarding PlaneControl PlaneTransportPlugins

TransportPlugins

Forwarding Plane

Transport Protocol

CCU EE&CTR 24

Control Plane Module

CCU EE&CTR 25

Control Plane

NP Forum defines two sets of APIs NPF Application API

IPv4 API, MPLS API, DiffServ API NPF Management API

CCU EE&CTR 26

Features of Control Plane module

One-to-many mapping Inter-forwarding plane forwarding Binding and capability discovery of

the forwarding planes OS abstraction layer achieve

independence from the control plane hardware and OS

CCU EE&CTR 27

Application API Implementation Module

IPv4 and IPv6 Unicast Forwarding API Configuration and management objects

Ex. IP route and ARP tables Receiving notification

Ex. ARP events MPLS API

Configuring the MPLS Core Component Setup the labels required for label swapping

ATM API Configuring and management VP,VC parameters

Qos API Configuration the IntServ and DiffServ CC

CCU EE&CTR 28

Configuration and Management Module

Layer 2 objects bridges and forwarding databases

Ports Ethernet

Layer 3 IP object Interface, IP route table, IPv6, Diffserv

CCU EE&CTR 29

Namespace Module

CCU EE&CTR 30

Binding and Capability Discovery Module

Responsible for binding and capability discovery of the underlying forwarding planes

Provides consistent semantics for heterogeneous forwarding plane

CCU EE&CTR 31

Forwarding Plane Topology Manager

The forwarding plane could be connected in a bus, mesh, star

The control data being downloaded must also be slightly modified in some case to simulate the one virtual router

CCU EE&CTR 32

Inter-FE Forwarding Module Assigning labels to be used for inter-FE

forwarding on per-router label information base.

CCU EE&CTR 33

Callback and Event Handler Module

Maintaining all API callbacks registered by the applications and also the callbacks registered for event notifications

CCU EE&CTR 34

CP Module Manager

Initialization and shutdown of CP module

The CP module manager starts all the sub-modules in the CP in a well-defined order, including the CP Agent, which is a part of the transport plug-in

CCU EE&CTR 35

CP Multi-client Module

Allows the PDK to run with multiple clients on Linux

The multi-client module uses RPC.

CCU EE&CTR 36

Protocol Support Service

Virtual Interface Device Driver (VIDD) CE packet handler Routing Cache Manager (RCM)

CCU EE&CTR 37

Transport Plug-in Provide in-process communication between the

control plane and the forwarding plane in the case of co-location

Different forwarding plane can be connected to the control plane over different interconnects.

CCU EE&CTR 38

Forwarding Plane Module

CCU EE&CTR 39

CPPUI for conformance test

CCU EE&CTR 40

Remote CP-PDK

CCU EE&CTR 41

Co-located CP-PDK

Software Architecture Overview

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