SOC Development Trends in Home Applications

Seh-Woong JeongApril 25 2002

Media SOC Team

System LSI Business

Samsung Electronics Co., Ltd.

Outline of Talk

SOC Development in Samsung System LSI

Issues and Trends in Home Networking

DVD Players/Recorders

Case Study : S5H5002

Q & A

What is SOC ?

RF/AnalogFront End

RF/AnalogFront End

MODEM/Channel

MODEM/Channel

MCUCore

MCUCore

Embedded MemoryFor Data/Program

Embedded MemoryFor Data/Program

HardwiredLogic

HardwiredLogic

Whole systemin a single package

DSPCore

DSPCore

Peripheral InterfaceLogic

Peripheral InterfaceLogic

Driving Forces for SOC’s

Set makers face tough competition to reduce material cost

New applications need Low power

Explosive growth of mobile applications Cellular phones, PDA, ...

Small size Mobile applications normally mean portability Reduce number of parts for feature size reduction

High performance Should cope with system-level complexity Multi-media applications

including( MP3+AAC+MS+MPEG4 )

PC

HHP

(CDMA)

D-TV

Audio Decoder

Channel On a Chip

DTV 1Chip

Video Decoder

TS

Format Converter

OSGM

Channel Decoder

Channel EQ.

Video On a Chip

< 0.10um0.13um> 0.25/0.18um

5Chip

2Chip

IEEE1394, PCI

RF Rx

RF Tx

BBA Rx

BBA Tx

PLL

BBA/RF Rx

BBA/RF Tx

Modem PLL

7Chip 4Chip

BBA/RF Rx

BBA/RF Tx

Modem PLLCDMA2000 1x DAC+GPS+Bluetooth

CPU(Cache SRAM)

I/O SOUND

Graphics(DRAM)

2Chip

Memory

1Chip

CPU

Memory

PC 1Chip

Memory

‘03 ~ ‘05‘01 ~ ‘02‘00

2Chip

SRAMModem

SOC Trend

1 Chip

Key Ingredients of SOC Technology

SOC

IP Cores

•MCU, DSP•DRAM, SRAM, Flash•High speed I/O•Analog/RF cores•Hard / Soft macros

Technology

•DSM logic process•Embedded memory process

Firmware/Software

•Algorithm•Real time OS•Device drivers•System software•Application software

Design Methodology

•Platform-based chip design •Static timing verification•HW/SW co-design •IP Reuse

Implementation

•Product / Test engineering•Packaging technology

SOC Cooperation

SOC Requires Tighter Relationship Strategic Relationship between Set Makers & Silicon Vendors Getting

More Important Than Ever Early System Requirement Access : Key to Time-to-Market Working Sample to Design-In : at least 6 months or more

Full Dedication from Both Sides More System Application Engineers in SOC Vendors

10~20 % more than 50% of R&D Work Force Strategic Relationship between Silicon Vendors & IP Vendors

Competitive/Proven IP Portfolio : Bare Minimum for SOC Business You can’t develop everything for yourself !!

Strategic Relationship between Silicon Vendors & Software Algorithm Firmware RTOS/Device Driver/BSP/Application Software Support Hardware Only Makes No Sense to Set-Makers !!

Cooperation Model

SystemIntegration

Process&

Fab

IP Cores

ProductEng.

Assembly / Test

DesignService

IP Provider

Des

ign

Hou

se

Customers

Silicon Vendors

Algorithm/Firmware/Software

SOC’s

System Idea

Software House

Well-Educated

Engineersfrom

Academ

ia

Leading The Digital EraLeading The Digital Era

Semiconductor Infra

ProcessTech.

AnalogModule

IP &Library

Package ProductEngineering

DesignService

SOC 개발 / 연구

SOC 공통 IP(CPU, DSP, 통신 /Media IP)

SOC Infra( 설계방법론 , IP Reuse, 인력양성 )

차세대 SOC

Solution

WirelessPDA

N/B PC

MP3Player

MobilePhone

MobileMobileNetworkNetwork

Printer

IP Terminal

PC

Display

OfficeOfficeNetworkNetwork

Digital TV

DVDP

HomeServer

HomeGateway

HomeHomeNetworkNetwork

Samsung SOC Future Goal

Home Networking

Why Home Networking ?

From End-User’s Standpoint

Remote Monitoring/Security 9%

Distributed Video 13%

0% 30%25%20%15%10%5%

Multiplayer Gaming

Home Control

Connect Laptop from Work

Share Files

Share Printers

Share Internet

15%

17%

20%

22%

23%

26%

Digital Home Example – Cisco View

Home Networking

Home Server + Home Gateway with • Convenient Access to Internet• Easy Connectivity between Home Appliances• Media Streaming Capability with Mass Storage

Each major company has a different view and its own strategies• PC-Centric View• CE-Centric View

PC-Centric View – Samsung HMC

Home Media Home Media CenterCenter

IEEE1394IEEE1394EthernetEthernetPLCPLCWireless PANWireless PAN

CE-Centric View

Home Server + Home Gateway will be• Set-Top Box or D-TV• DVD-Box (DVD Player/Recorder or iDVD)• Game Console : PS3 from Sony• “If Sony's aspirations succeed, then the Playstation 3 will not be a pure video game

console, but rather measure the amount of milk left in the fridge, record TV programs to hard-disk, automatically download new software, perform Tera-flop operations and a variety of other things. In short, if one can automate, computerize, network or electrify a process, then the PS3 should be able to take on the task.”

Chances are : some form of a convergence box. For example,

• DVD + Set-Top Box with broad-band access capability and mass storage

Key Technologies Connectivity Technologies

• In-House Connectivity : 802.11e (QoS), IEEE1394, …• Out-Door Connectivity : xDSL, Cable Modem, ….• Broadcast Connectivity : VSB, OFDM, QPSK, …

Media Processing Technologies• MPEG2/4 (or H.264)• Pre-/Post-Processing

High Performance CPU/DSP

Middlewares

DVD Players/Recorders

DVD (Digital Versatile/Video Disc/Disk) An Interesting Article from WP ’02.10.07

“DVD, 할리우드의 최대 수익원으로 부상” '02 년 할리우드 영화의 DVD 판매 및 대여수입은 26 억달러로 극장수입 17 억달러 , 비디오 판매

및 대여수입 16 억달러를 각각 추월하면서 최대 수익원으로 부상 DVD 수입 급증은 무엇보다 DVDP 보급 증가에 기인 VCR 은 9 천만 미국 가구가 보유해 포화 단계인 반면 DVD 는 1 년 전 천 7 백만에서 현재 3

천백만 가구로 급증

DVD 의 경우 VCR 과 달리 소비자들이 타이틀 대여보다 구매를 많이 하는 특성이 있어서 판매 확대가 용이

DVD 보유가구는 올해 평균 260 달러 정도의 16 개 DVD 타이틀을 구매하는 반면 , VCR 보유가구는 평균 5 개의 테이프를 구매

DVD 는 대여료 대비 판매가가 3-5 배에 그치고 , 반영구적인 화질 , 제작과정과 게임 등 다양한 컨텐츠가 있기 때문

디즈니 영화 " 몬스터 " 는 전체 극장수입이 2.6 억 달러였지만 , DVD 를 20 달러에 출시한 첫 주에 1.4 억달러 가치의 7M copies 판매

DVD 는 대량생산이 용이해 제조원가가 적기 때문에 판매 수익도 큼 29.98 달러에 팔린 " 해리포터 " DVD 에서 영화사 몫은 9.98 달러 11 월 1 일 출시될 소니의 " 스파이더 맨 " DVD 는 이미 WalMart 에만 19M copies 납품 등

새로운 판매기록을 세울 전망

Deck Mechanism

P/U

MotorDriver

SystemControl

RF (EQ, DigitalDetector)

Servo(Focus, Tracking,

Sled control)

EFM+ Demod,ECC Decoder

Video Decoder(MPEG)

Front-End Back-End

Audio Decoder(MPEG, AC3, DTS, MLP)

CPS

Video

Audio

SystemControl

DVD Player System

DVD Disc Structures

Double side / Single Layer

9.4GB

Double Side / Dual Layer

17GB

Single side / Dual Layer

8.5GB

Single side / Single Layer

4.7GB

Single sided DiscSingle sided Disc

Double sided DiscDouble sided Disc

Optical Disc Evolution Movement to Higher-Density & Higher-Speed

Movement to Small Form Factor A smaller disc can store more than 2 hours of Motion

Picture in DVD’s quality (50mm BD or 30mm UD)

CD DVD BD UD

(Ultra Density)

High-Density 650 MB 4.7 GB (7 CD) 25/50 GB (6 DVD) 150 GB (6 BD)

High-Speed 1.2 Mbps (1x) ~

57.6 Mbps (48x)

11 Mbps (1x) ~

177 Mbps (16x)

36 Mbps (1x) ~

360 Mbps (10x)

100 Mbps (1x) ~

600 Mbps (6x)

Applications Digital Audio Digital Video (SD)

Digital Video (HD)

QXGA Video

Technologies Infra Red laser

CIRS(Cross Interleave Reed-Solomon) code

EFM

Dual Layer Disc

Red laser

RSPC(Reed-Solomon Product Code)

EFM+

MPEG2/DTS/AC3

Blue laser

LDC(Long

Distance Code)

+ BIC(Burst

Indicator Code)

1.7PP(Parity

Preserve /

Prohibit RMTR)

Multi Layer

Holographic

Near Field

Recording

Worldwide DVDP & DVD Recorder Supply (IDC '02. Oct)

Unit: 1M

26.940.9 48.5 52.2 52.4 48.7

0.02

0.71

3.069

19.14

32.21

0

20

40

60

80

100

2001 2002 2003 2004 2005 2006

DVD Play-Only DVD Recorder

’02 ’03 ’04 ’05

Avant Work 50 170 450 900

IDC 71 306 900 1,914

Fujiwara 60 180 400 800

C/In-Stat 110 280 640 1,360

MEI 130 500 1,150 1,500

Unit: 1M

Rapid Market Maturity of Play-Only DVDP

(Market Fall off after ’05 is expected)

Rapid Price Drop of DVDP: 30% / Year

( $129(’02) $89(’03) $59(’04) )

Market-Shift from VCR to DVD Recorder

(Higher A/V Quality, Affordable Price)

Rapid Market Growth after ’03 is Expected

(Annually more than 200% of Growth)

Popularization of DVDP for Low Price

Increase of Needs for Recorders

DVDP Market Saturation

Recorder Price Down & Market Formation

DVD Recorder Market Trends

DVD-RAM 80%

DVD-RW 20%

• In Worldwide DVD Recorder Market, Japan holds 48%, EU holds 32% and US takes 13%

EUEU

JapanJapanDVD-RAM 50%

DVD+RW 50%

USUSDVD-RAM 56%

DVD+RW 41%

◆ Japan

- DVD-RAM + HDD product takes 50% in RAM market

◆ US

- RAM takes 56% in market, +RW increases after ’02.2Q

◆ EU

- Philips (DVD+RW) is a major supplier

3.8M

$299

$399$499

$699

2.8M

1.4M1.0M

Market Size & Format Competitions

RAM

DVD-Multi

+ RW- RW

± RW

Pioneer

RicohPhilipsYamahaMitsumi

SONYNECSanyo

Panasonic, ToshibaSAMSUNG, HLDS

Dell, HP

Apple

IBM

Sony, Toshiba, Fujitsu

Super Multi

Recordable Discs & Features

# of Writes Scan Type Addressing type Write type

DVD-RAM

(Panasonic)

100,000 times

Zoned CLV Single Wobble & PID Land/Groove

DVD-RW

(Pioneer)

1,000 times CLV Single Wobble & Land Pre-pit

Groove

DVD+RW

(Philips)

1,000 times CLV Wobble PM (ADIP) Groove

DVD Standardization Body DVD-Forum

Nov. ’97: Changed from ‘Consortium’, Opened publicly Members: 212 companies over Content Owners, CE

Manufacturers, IT Manufacturers. Standardized DVD Formats

Logical: DVD-Video, DVD-Audio, DVD-VR, DVD-AR, Streamer Physical: DVD-ROM, DVD-RAM(3x), DVD-R(4x), DVD-RW(2x)

Discussing proposals for DVD Formats Logical: Interactive DVD, HD-DVD9, MOST1), iDVD Streamer Physical: DVD-RAM(5x), DVD-R(8x), DVD-RW(4x), DVD-AOD

BDF (Blue-ray Disc Founders) Closed consortium to standardize BD-ROM/R/RE format Member(9 CE companies) + Advisory Group(MPAA, IT, Disc

Manufacturer) + Contributors

1) Media Oriented Systems Transport

iDVD(Interactive DVD) DVD-Video Contents + Interactive Contents on Disc JAVA Script, HTML for Interactive Contents Value Added Service thru Internet Access

Additional Subtitle Service Game E-Commerce

Legarcy DVD Player Function

Interactiv Contents Browsing

API bridge

DVD- Video contentsInteractive Contents

InternetConnection

Contents onServer

iDVD Disc

iDVD Player

Internet Server

TV

LocalStorage

Network Connectivity(Optional for player)

Samsung A/V Decoder for DVDS5H5002

S5H5002 Block Diagram

32/16

Ethernetconn.

Ethernetconn.

SDRSDRAM

SDRSDRAM NOR FlashNOR Flash

ATAPIHost/

ParallelSerial A/V IF

3322bbiitt

AAHHBBPPLLUUSS

MPEG StreamDemuxDecoder

Memory Controller (32bit 117MHz)

NTSC/PALEncoder

MixerOSD

5 DAC

I2C

UART

SPI

8bitADC

GPIO

SPDIF

I2S out

I2S in

IR

AHB toAPB

Bridge

Memorystick I/F

MPEG2 Video

Decoder

2D GraphicAccelerator

M1

M2M1

M2

IO DMA

3322bbiitt

AAHHBBPPLLUUSS

Controlregisters

of IPControlregisters

of IPControl

registersof IP

3322bbiitt

AAPPBB

ARM940T

BT 656in/out

Sub-pictureDecoder

I-FrameOnly Encoder

IPC/ Format

Converter

Calm16MAC2424(Audio)

Bus Architecture SDRAM Bandwidth Problem

Bandwidth-hungry masters contending over an external SDRAM Single 16-bit SDRAM @ 133MHz used for the cost issue Bandwidth Utilization Serialized bus transaction in single layer AHB

Utilization = data transfer cycles / total clock cycles Multi-layer bus is required.

Low SDRAM bandwidth utilization for random access Access turn around time for each bank : 12 cycles Maximum utilization : about 60% Bank interleaving is required.

SDRAM latencyArbitration Data Transfer

SDRAM latencyArbitration Data Transfer

SDRAM latencyArbitration Data Transfer

SDRAM latencyArbitration Data Transfer

SDRAM latencyArbitration Data Transfer

SDRAM latencyArbitration Data Transfer

Single Layer Conventional AHB

Multi-Layer AHB

Multi-Layer AHB with Bank Interleaving

Bus Architecture – AHB+ Backward Compatible with AHB Bus : IP Reuse

Burst Length Extension (1,2,3,5,6,7,8 beats supported) Hiding Arbitration Overhead

Bus protocol state machine for each master

Maximize SDRAM Bandwidth Utilization Bank interleaving is fully utilized Address Dependent Priority Arbiter is tightly coupled with the memory controller

SDRAM

Memory Controller

Master 1 Master 2 Master n

ProtocolFSM

ProtocolFSM

ProtocolFSM

…

Arbiter

Bus Arbitration Scheme Priority Scheduling with Ages

Preventing starvation of low priority masters For each master, latency amount is set by software If latency is more than the amount, priority is incremented. Important feature for CPU/DSP

Read/Write transaction requests have higher priority after read/write transactions, respectively. (in order to localize the same type of accesses)

Priority Rule Interface masters have higher priority. Masters with smaller buffer have higher priority

Usually complex masters need a large buffer. Masters of higher bandwidth have higher priority IO DMA > SD Input > VP > FIU > VD > GA

AudioDSP(CalmRISC16+CalmMAC24)

CalmRISC16 CalmMAC24

Data Memory

ProgramMemory

command

status

data 24X Y 2416

16

code

CalmMAC24 : Passive Coprocessor to CalmRISC16 Single MDS for CalmRISC16 and Coprocessor CalmMAC24

Programming Generic Coprocessor Instructions Mapped to a Specific

Coprocessor Instruction Set, in general

CalmADM Design Objectives

Small Area Low Bus Access Rate Efficient Stream Data Processing

Caches + Stream Buffers

CalmADM Architecture Processors: CalmRISC16, CalmMAC24 Memory Subsystems: Three Caches, Two Sequential Stream Buffers Interfaces: AHB+ Interface, Mail Box

Y-Bus

PD-BusC a lm R IS C 16

I-C ache8K B

D -C acheXC : 6K B

D -C acheYC : 6K B

S B F 0 : 16B

H ostP rocessor

M IU

M ailB ox32B

Calm ADM

A rb ito r &A H B -P lus

M aste r

C a lm M A C 24

S B F 1 : 16B

A H B -P lusS lave

O ff-C h ipS D R A M

On-Chip

D-Bus

X-Bus

A H B -P lus

CalmADM Memory Mapping Scheme

16bit3FFFFFh

64K byte I/O Area

000000h

4M byte Data Memory

CalmADM Logical Memory

Unused YE

Unused XE

YL

XL

YH

XH

Physical Memory

DBASE

200000h

32K Lword

X Data Memory

220000h

3F0000h

2M byte

Calm area

Unused Area

Off-chip Memory

4:3 data packing

4:3 data packing

packed data

packed data

256K byte

SBL0 area

240000h

280000h 256K byte

SBL1 area

2C0000h

XBASE

YBASE

S0BASE

S1BASE

CalmRISC16 Virtual Memory

4M byte

Data Memory

CalmMAC24 Virtual Memory

32K Lword

Y Data Memory

Data Cache Structure

X/Y-Caches 2-way set associative Buffered write-back policy

As D-Cache Calm Area Access

XC/YC are two sets of D-Cache E bytes are unused

X/Y Area Access Address translation for E bytes

Set 2

Set1

128lines

8 24-bit data

3Byte

E H L

X-Cache

Y-Cache

Why Stream Buffers? Without Stream Buffers

With Stream Buffers

Eliminate the overhead of cache replacement due to stream I/O

Eliminate cache thrashing due to stream I/O

Separated buffer spaces increase data space

Data Cache

On-Chip Off-Chip Memory

Temporary Data Area

(read/write)

data address space of DSP coreDSP Core

CPU Core

Input Stream Area(read-only)

Output Stream Area(write-only)

Data Cache

On-Chip Off-Chip Memory

Temporary Data Area

(read/write)

data address space of DSP coreDSP Core

CPU Core

Input Stream Area(read-only)

Output Stream Area(write-only)

Data Cache

On-Chip

Stream Buffer

Stream Buffer

Input Data Area

(read-only)

Output Data Area

(write-only)

Off-Chip Memory

Temporary Data Area

(read/write)

data address space of DSP core

Extended data address space

Extended data address space

DSP Core

CPU Core

Data Cache

On-Chip

Stream Buffer

Stream Buffer

Input Data Area

(read-only)

Output Data Area

(write-only)

Off-Chip Memory

Temporary Data Area

(read/write)

data address space of DSP core

Extended data address space

Extended data address space

DSP Core

CPU Core

A Sequential Stream Buffer 16 byte read/write buffer, 16-bit mode / 32-bit mode Functions for efficient sequential access

Auto-increment of OFFSET address Empty detection and auto-fill Full detection and auto-flush Boundary detection and interrupt generation

Off-chip Memory Data Bus

On-ChipSequentialBuffer Off-Chip

Memory0

Offset

Input/Output Stream Area

(sequentially accessed)+ 1

Off-chip Memory

Address Bus

Sequential Buffer Module

1

2

3 Base Address

CalmRISC16 +

CalmMAC24

End==

interrupt

Buffer Entry Selection

Off-chip Memory Data Bus

On-ChipSequentialBuffer Off-Chip

Memory0

Offset

Input/Output Stream Area

(sequentially accessed)+ 1

Off-chip Memory

Address Bus

Sequential Buffer Module

1

2

3 Base Address

CalmRISC16 +

CalmMAC24

End==

interrupt

Buffer Entry Selection

De-Interlacing(or IPC) Scan Rate Conversion in DVDP

ProgressiveSource

InterlacedSource

InterlacedDisplay

ProgressiveDisplay

De-Interlacing

(3:2 or 2:2 Pull down)

(NTSC/PAL)

(Film) FieldSplit

(Frame Repetition)

Source Display

De-Interlacing-Cont’d

To display an interlaced video signal on a progressive display

Method Bob

Scan line interpolation/duplication using one field The resulting vertical resolution is limited to the “field”

Weave merging of two consecutive fields The simplest method to implement double resolution Artifacts in regions of movement

3D-IPC(Motion Adaptive IPC) Field merging for still areas of picture and interpolation for areas of

movement Issue: cost function to detect a “movement”

MC-IPC(Motion Compensation IPC) Accurate motion information Blocky side effect

De-Interlacing-Cont’d 3D-IPC in S5H5002

Spatio-TemporalFiltering

DirectionalInterpolation

TemporalFiltering

CalculateF(Motion)

Field I

Field I+1

Field I-1

Globalmotion

3 fieldsSAD

function

ImageComplexity

Motion inform

Localmotion

WEAVE

3D-IPC

Other ExamplesVideo Post Processing

forImage Enhancement

DNIeTM

Detail Contrast Enhancement

Color Tone Enhancement