Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P...

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M4 – Parallelism Snooping based Cache Coherence Protocol

Transcript of Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P...

Page 1: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

M4 – Parallelism

Snooping based Cache Coherence Protocol

Page 2: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Outline

● Parallelism● Flynn’s classification● Vector Processing

– Subword Parallelism

● Symmetric Multiprocessors, Distributed Memory Machines– Shared Memory Multiprocessing, Message Passing

● Synchronization Primitives– Locks, LL-SC

● Cache coherence

Page 3: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Cache Coherence

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Shared Memory vs. Distributed Memory

PP

CC

Main MemoryMain Memory

PP

CC

PP

CC

PP

CC

PP

MM

InterconnectInterconnect

PP

MM

PP

MM

PP

MM

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Multiprocessor Cache Coherence

CPU ACPU A CPU BCPU B

MemoryMemory

Page 6: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

Page 7: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

Page 8: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

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Multiprocessor Cache Coherence

Page 10: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

Page 11: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

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Multiprocessor Cache Coherence

Page 13: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

Page 14: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

Page 15: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

CPU B reads X

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Multiprocessor Cache Coherence

CPU B reads X Return which value to CPU B?

Return which value to CPU B?

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Cache Coherence● Coherence

– Which value to return on a read

Page 18: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Cache Coherence● Coherence

– Which value to return on a read

● A memory system is coherent if:–

Page 19: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Cache Coherence● Coherence

– Which value to return on a read

● A memory system is coherent if:– Write Propagation

●

– Write Serialization●

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Cache Coherence● Coherence

– Which value to return on a read

● A memory system is coherent if:– Write Propagation

● A write is visible after a sufficient time lapse

– Write Serialization●

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Cache Coherence● Coherence

– Which value to return on a read

● A memory system is coherent if:– Write Propagation

● A write is visible after a sufficient time lapse

– Write Serialization● All writes to a location are seen by every processor in the

same order

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Cache Coherence● Directory based protocols

–

● Snooping protocols–

–

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Cache Coherence● Directory based protocols

– Sharing status maintained in a directory

● Snooping protocols–

–

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Cache Coherence● Directory based protocols

– Sharing status maintained in a directory

● Snooping protocols– Sharing status is stored in the cache controller

– Cache controller snoops broadcast medium

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Cache Coherence● Write Invalidate protocols

–

● Write Update protocols–

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Cache Coherence● Write Invalidate protocols

– Invalidates other processors' copies on a write

● Write Update protocols–

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Cache Coherence● Write Invalidate protocols

– Invalidates other processors' copies on a write

● Write Update protocols– Updates all data copies on a write

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Cache Coherence● Sharing Status

– Invalid (I)

– Shared (S) (or Clean)

– Modified (M) (or Dirty)

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

Page 31: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

Cache Miss

Cache Miss Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

Cache Miss

Cache Miss Cache Miss

Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

CPU A reads XCPU A reads X

SharedShared

Page 37: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

Cache Miss

Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

Cache Miss

Cache Miss

Cache Miss

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

Page 43: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared

CPU B reads XCPU B reads X

SharedShared

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

CPU A writes XCPU A writes X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

CPU A writes XCPU A writes X

Write Invalidate X

Page 47: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

CPU A writes XCPU A writes X

Write Invalidate X

Write Invalidate X Write Invalidate X

Page 48: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

CPU A writes XCPU A writes X

Write Invalidate X

Write Invalidate X Write Invalidate X

Page 49: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared InvalidInvalid

CPU A writes XCPU A writes X

Write Invalidate X

Write Invalidate X Write Invalidate X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared InvalidInvalid

CPU A writes XCPU A writes X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

CPU A writes XCPU A writes X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

CPU B reads XCPU B reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

CPU B reads XCPU B reads X

Cache Miss

Cache Miss

Page 55: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

CPU B reads XCPU B reads X

Write Back

Page 56: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

ModifiedModified InvalidInvalid

CPU B reads XCPU B reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared InvalidInvalid

CPU B reads XCPU B reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared InvalidInvalid

CPU B reads XCPU B reads X

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SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared InvalidInvalid

CPU B reads XCPU B reads X

Page 60: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP - Write Invalidate

CPU ACPU A CPU BCPU B

MemoryMemory

SharedShared SharedShared

CPU B reads XCPU B reads X

Page 61: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor
Page 62: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Slides Contents

● Rajeev Balasubramonian, CS6810, University of Utah.

●

Page 63: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Extra

Page 64: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Shared Memory vs. Message Passing● Shared Memory Machine: processors share

the same physical address space– Implicit Communication, Hardware controlled

cache coherence

● Message Passing Machine– Explicit communication – programmed

– No cache coherence (simpler hardware)

– Message passing libraries: MPI

PP

CC

Main MemoryMain Memory

PP

CC

PP

CC

PP

CC

PP

MM

InterconnectInterconnect

PP

MM

PP

MM

PP

MM

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Cache Coherence● Consistency

– When should a written value be available to read

– Memory Consistency Models

● Coherence– Which value to return on a read

● A memory system is coherent if:– Write Propagation

● A write is visible after a sufficient time lapse

– Write Serialization● All writes to a location are seen by every processor in the

same order

Page 66: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Multiprocessor Cache Coherence

● A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P.

● A read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses.

● Writes to the same location are serialized; that is, two writes to the same location by any two processors are seen in the same order by all processors.

Page 67: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

Write Invalidate Coherence Protocol

Writeback / WritethroughEnforcing write serialization

• Bus Arbitration

Tag Contention, Duplication

Page 68: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP Cache Coherence

● MSI Protocol● MESI Protocol

– Exclusive state: No invalidate messages on writes.

– Intel i7 uses MESIF

● MOESI Protocol– Owned state: Only valid copy in the system. Main

memory copy is stale.

– Owner supplies data on a miss.

Page 69: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor

SMP Example

ProcessorA

Caches

ProcessorB

Caches

ProcessorC

Caches

ProcessorD

Caches

Main Memory I/O System

A: Rd XB: Rd XC: Rd XA: Wr XA: Wr XC: Wr XB: Rd XA: Rd XA: Rd YB: Wr XB: Rd YB: Wr XB: Wr Y


Cache coherence problem and its solutions

Cache coherence problem and its solutions

Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs · 2020-06-13 · Cache Memory Agent – A2 Cache Figure 1: Cache coherence management One way to manage cache coherence

Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs · 2020-06-13 · Cache Memory Agent – A2 Cache Figure 1: Cache coherence management One way to manage cache coherence

Power Efficient Cache Coherence

Power Efficient Cache Coherence

walterschilling.org · Explain the problem of cache coherence Explain how cache coheïÆ777766 dealt with Explain noo ing based cache coherence Explain alse sharin . EDO, so-RAM,

walterschilling.org · Explain the problem of cache coherence Explain how cache coheïÆ777766 dealt with Explain noo ing based cache coherence Explain alse sharin . EDO, so-RAM,

Cache Coherence for GPU Architectures - Iowa State Universityclass.ece.iastate.edu/.../HPCA13GPUCachecoherence.pdf · Cache Coherence for GPU Architectures Inderpreet Singh1 Arrvindh

Cache Coherence for GPU Architectures - Iowa State Universityclass.ece.iastate.edu/.../HPCA13GPUCachecoherence.pdf · Cache Coherence for GPU Architectures Inderpreet Singh1 Arrvindh

Directory-Based Cache Coherence Marc De Melo. Outline Non-Uniform Cache Architecture (NUCA) Cache Coherence Implementation of directories in multicore.

Directory-Based Cache Coherence Marc De Melo. Outline Non-Uniform Cache Architecture (NUCA) Cache Coherence Implementation of directories in multicore.

Constructive Computer Architecture Cache Coherence Arvind

Constructive Computer Architecture Cache Coherence Arvind

Source Snooping Cache Coherence Protocols - Par Labparlab.eecs.berkeley.edu/.../parlab/files/20091029-goodman-ssccp.pdfSource Snooping Cache Coherence Protocols ... – Supports all

Source Snooping Cache Coherence Protocols - Par Labparlab.eecs.berkeley.edu/.../parlab/files/20091029-goodman-ssccp.pdfSource Snooping Cache Coherence Protocols ... – Supports all

Cache Coherence Techniques - Dipartimento di Informaticavannesch/SPA 2011-12/Silvia-cache-coherence-.pdf · Figure 1: The cache coherence problem 1 Cache Coherence In multiprocessor

Cache Coherence Techniques - Dipartimento di Informaticavannesch/SPA 2011-12/Silvia-cache-coherence-.pdf · Figure 1: The cache coherence problem 1 Cache Coherence In multiprocessor

Cache Coherence Protocols 1 Cache Coherence Protocols in Shared Memory Multiprocessors Mehmet Şenvar.

Cache Coherence Protocols 1 Cache Coherence Protocols in Shared Memory Multiprocessors Mehmet Şenvar.

Assessment of Cache Coherence Protocols

Assessment of Cache Coherence Protocols

Dynamic Verification of Cache Coherence Protocols

Dynamic Verification of Cache Coherence Protocols

Lecture 9: Cache Coherence

Lecture 9: Cache Coherence

Cache Coherence

Cache Coherence

Database backed coherence cache

Database backed coherence cache

Cache Coherence in Distributed Systems (Thesis)

Cache Coherence in Distributed Systems (Thesis)

Cache Coherence - Parasol Laboratory | Department of ...rwerger/Courses/654/cachecoherence1.pdf · Snoopy Cache Coherence Schemes • A distributed cache coherence scheme based on

Cache Coherence - Parasol Laboratory | Department of ...rwerger/Courses/654/cachecoherence1.pdf · Snoopy Cache Coherence Schemes • A distributed cache coherence scheme based on

CACHE COHERENCE TECHNIQUES FOR MULTICORE PROCESSORS

CACHE COHERENCE TECHNIQUES FOR MULTICORE PROCESSORS

Cache Coherence for GPU Architectures

Cache Coherence for GPU Architectures

Cache coherence - University of Pittsburghmelhem/courses/xx45p/coherence.pdf · 2 3 Approaches to cache coherence • Do not cache shared data • Do not cache writeable shared data

Cache coherence - University of Pittsburghmelhem/courses/xx45p/coherence.pdf · 2 3 Approaches to cache coherence • Do not cache shared data • Do not cache writeable shared data