Smart Devices of 2025

Challenges for Packaging of Future Device Technologies

Steve Riches/Kevin Cannon – Tribus-D Ltd

CW Workshop

27 March 2018

E:mail: info@tribus-d.uk

M: 07804 980 954

Tribus-D Overview, February 2018

Steve Riches

Kevin Cannon

Founded January 2016

Over 60 years combined industrial experience in:• Electronic packaging and interconnection• Automotive, industrial, aerospace and

consumer electronics• Si, SiC, GaN semiconductor assembly• Optics, Sensors, MEMS, ASICs, Power, Hybrids• Displays, LED lighting• High temperature electronic packaging• Energy harvesting• Wireless interconnect• Laser processing• Project management• Proposal generation

Assembly Technology Development

Assembly Technology Consultancy

3D InterconnectsImage: Optomec

Packaging and Interconnect:• 3D Interconnect• Die Attach• Sintering• Die Thinning• Flip Chip Bonding• Wire Bonding• Adhesives/soldering• Over-moulding• Thermal Management• Underfill

Tribus-D Ltd – OverviewSpecialists in Micro-Electronics Assembly

Advanced Electronic Packaging and Interconnect:• Distributed (Smart) Systems• Miniaturisation• Reduced parasitics• Elimination of interfaces• Flexible hybrid electronics (Si/passive devices)• Rapid prototyping

Scope of Presentation

• Advanced Packaging of Electronic Devices• More than Moore• Technology Trends• Commercial Challenges• Wide Band-gap Semiconductors• Heterogeneous Integration on Foils• Fan Out Wafer Level Packaging (FOWLP)• 5G/SIP Architectures• Additional Challenges of RF/µ-Wave/mm-Wave

• Packaging for Future Devices• Miniaturisation• Embedded Packaging Technologies• Plastic and Hybrid Electronics• Additive Manufacturing/3D Printing

• Conclusions

Advanced Packaging Assembly Methods

Cross-Section of Advanced Packaging Assembly MethodsImage: Yole Development

Technology Trends• Higher power• Higher frequencies• Thermal management• EMI shielding• Miniaturisation/form factor • More integration/embedding• Less bespoke products• Higher quantities• End of Life/Recycling• Material availability• Sustainability• Flexible/Hybrid electronics

Commercial Challenges for Industrialisation

• Materials and manufacturing costs• Economies of scale• Low volume vs high volume• Established supply chain• In-house manufacture vs sub-contract• Standard vs customised product• Investment required• Level of integration• Low power vs high power• Availability of bare die• Minimum order quantities• Yield• Obsolescence• Cost modelling• Patent issues System in Package Options

Source: O’Malley G, i-NEMI “Packaging Trends and Challenges” Microtech 17, IMAPS-UK, March 2017, Rutherford Appleton Laboratories

Potential Applications for Wide Band-Gap Semiconductors

• As power capacity and operating frequencies increase, packaging and interconnection becomes more important in determining performance and efficiency of power modules

• Need to reduce circuit parasitics (R, C, L) and thermal resistance

• Achieved by shortening connections and removal of interfaces

Smart System Integration on foils

EC-funded FP7 project Interflex (2010- 2013)

Multi-foil Hetereogeneous Integration

flexible PV panel

Printed Sensors (FhG EMFT)

Thinned STM8L

Microcontroller

(STMicroelectronics)Wiring layers, Printed via

holes, Passives and

Assembly (FhG EMFT,

Bosch)

Radio chip (bare die) and Antenna on foil

Thin voltage regulator

2xSTLQ50

(STMicroelectronics)

Top side

Bottom

side Thin film batteries (CEA Liten)

https://www.i-micronews.com/images/Reports/Packaging/Images_Reports/Advanced-RF-System-Cell-Phones-5G.jpg

https://www.i-micronews.com/images/Reports/Packaging/Images_Reports/rf-system-SiP-architecture-5G.jpg

Qualcomm VIVE – QCA9500

High Density WiGig/WiFi 802.11 Chipset for 60GHz Band

• RF IC and Integrated Antennae• Up to 4 transceivers controlling up to 32 antennae• Antennae embedded within package

• SiP with double sided moulded configuraton• Baseboard processor – re-distributed processor signal to pcb with copper pillars inside the moulding• Switch• Regulator• Crystal• Memory• 60 SMD components

Additional Challenges for RF/µ-wave/mm-wave Packaging:

• Distributed Effects• Circuit features/components have dimensions that are appreciable fraction of the wavelength• Electrical characteristics change as the frequency increases• Small features or discontinuities in signal traces can have a significant effect on circuit performance

Ref: Kuang K, Franklin K and Cahill S “RF and Microwave Microelectronics Packaging” Springer Publishing ISBN 978-1-4419—0983-1

Microwave Evaluation BoardImage: www.custommmic.com

Additional Challenges for RF/µ-wave/mm-wave Packaging:

• Design of metal pattern and dielectric thickness to maintain required line impedance

• Short interconnect lengths to minimise reflections• Material selection to minimise effects on electromagnetic fields

on ICs• Coupling between traces and package resonance• High power dissipation from active devices• Sensitivity of some devices to mechanical damage

Ref: Kuang K, Franklin K and Cahill S “RF and Microwave Microelectronics Packaging” Springer Publishing ISBN 978-1-4419—0983-1

• Transmission line and interconnection via signal transition effects• Coupling and radiation: adjacent metal traces, traces near

to ICs, traces between layers• Materials selection: line impedance and insertion loss,

thickness of dielectric and metal layers• Lumped elements: passives need to be integrated or

embedded into the packaging to perform at higher frequencies

Packaging Trends - Miniaturisation

Features

• Handling thinned silicon die• Levelling/parallelism• Package warpage• Alignment tolerances• CTE mismatch

Barriers

• Thinned die <50µm• Die Connections <30µm• 2.5D and 3D structures• Alignment – sub-micron• Thermal management

Ref: O’Malley G, i-NEMI “Packaging Trends and Challenges” Microtech 17, IMAPS-UK, March 2017, Rutherford Appleton LaboratoriesRef: Avrillier C, SET “Flip-chip bonding : how to meet the high accuracy requirement?” Advanced Packaging Workshop, IMAPS-UK, Feb 18

Alternative Assembly Methods for Flip Chip

Overview of Transient Liquid Phase (TLPS) Cu-Sn Solder Bonding ProcessProcess Description

Advantages

• Low cost materials compared to Ag or Au• High thermal stability• Remelt temperatures higher than process

temperatures

• Long processing times normally required to achieve Cu-Sn intermetallic joint

• Intermetallic materials have high rigidity, possibly causing stresses during thermal cycling

• Complicated processing involving pressure and removal of oxide prior to bonding (e.g. through formic acid)

• Difficult to achieve void free interfaces

Disadvantages

• Heating, melting and dissolution/diffusion of low melting point material (e.g. Sn) with Cu

• Sn can be applied as:• Foil• Separate particles• Sn coated Cu particles

• Intermetallic joint formed (e.g. Cu3Sn) has higher remelt temperature

Ref: Nishikawa H et al “Effect of Iso-Thermal Aging at 250oC on shear strength of joints using Sn coated Cu Particle Paste for High Temperature Application”, HITEN 2017 Conference pp202-206

Packaging Trends – Embedded Packaging Technologies

Features

• CTE mismatch between Si and substrate• Possibility of repair• Recyclability/sustainability• Thermal management• Yields

Barriers

• Design flexibility• Common building blocks – modular electronics• Reduced module thickness• Improved electrical performance• EMI shielding capability

Ref: Ivankovic A et al, Yole Developments “Status of advanced substrates 2018 – Embedded dies and interconnects, substrates like pcb trends” March 2018Ref: Tremlett P, Micro-semi “Why Embedded Die” IMAPS-UK/NMI Conference – Embedded Die Technology, September 2016

Technology Features• Integrated power module• Common building block• Modular and scalable• Thermal management

Potential Benefits• Miniaturisation• Improved electrical efficiency• Enhanced heat dissipation and EMI

shielding• High temperature operation• Recyclability and sustainability

What’s Next• Demonstration• End-User Feedback• Benchmarking• Collaboration• IP Landscape

Embedded Electronic Packaging Technologies for Compound Semiconductor Power Applications

Packaging Trends – Plastic and Hybrid Electronics

Features

• Plastic ICs for limited functionality (e.g. RFID) • Combination of Si and plastics for higher performance• Opportunity for introduction of new materials• High volume, low cost applications

• Integration of diverse materials• Low overall temperature processing

• Low temperature excursions• Localised heating techniques

• Reliability/lifetime

Barriers

Ref: Dou G and Holmes A, Imperial College “Interconnection Technologies for Integration of Active Devices with Printed Plastic Electronics” InnoLAE Conference, Cambridge, January 2018

Wearable healthcare Device Source: medGadget Silicon on Flex Demonstrator Source: Imperial College

Packaging Trends – Additive Manufacturing/3D Printing

Features

Ref: Berger U “Additive Manufacturing to Add Value to Products Produced with Conventional Manufacturing Methods” IMAPS-UK Microtech, March 2017

Challenges for Packaging of Future Device Technologies - Conclusions

• Increased power and frequency requirements for future electronic modules will need:• Enhanced thermal management• Reduced circuit parasitics• Improved EMI shielding

• For companies wishing to exploit devices using advanced packaging technologies, affordable access to state of the art packaging equipment is needed in the following areas:• Miniaturisation• Embedded Packaging Technologies• Plastic and Hybrid Electronics• Additive Manufacturing/3D printing

• Routes to industrialisation need to be defined between:• Lower volume, high added value• Higher volume, low cost applications• Different business models may be required