Small Signal Amplifier - BJT 1-23

7/28/2019 Small Signal Amplifier - BJT 1-23

1/23

Small Signal Amplifiers - BJT

Definitions

Small Signal Amplifiers

Dimensioning of capacitors


2/23

Small signal condition

When the input signal (vin and, iin) is small so that output signal (vout and,

iout)is confined in the active region of the output characteristics of the device,the device is operating in a condition of small signal.

More specifically, the condition of small signal are verified when the variations in

output are so small that the values of the parameters of the device can be

regarded as constant.

In these conditions, the amplifiers can be analyzed using the small-signal

models of the BJT. The small signal conditions occur, in general, for the firststages constituting an amplification system.

Linearity

In conditions of the small signal, the amplifier can be considered linear. The

output signal is proportional to the input signal. This property derives from

the fact that the components of the circuit are described by linear equations.If the system is linear applies the principle of superposition.

Amplitude and phase distortion

So that a waveform is not altered across the amplifier is necessary that each of

its sinusoidal component is equally modified in amplitude and phase.

Definitions (1)


3/23

The transfer function or network function

Complex function that describes the relationship between the output signal and the input

signal. It is defined in the Laplace domain (s) or in the frequency domain (s = jw)

Amplitude and phase responseReal functions obtained by specifying amplitude and phase of the transfer function with s = jw.

Describe the variation of modulus and phase when the frequency changes.

Gain and phase shift of an amplifier

In the case of an amplifiertransfer function is also called amplification (or gain) and can be

expressed in magnitude and phase. Relatively to the various electrical quantities considered for

entry and exit there are various definitions of gain

Definitions (2)

;Lvin

VA

V

Voltage

amplification

;Li

in

IA

I

Current

amplification

;LGin

IA

VTransconductance

amplification

;LR

in

VA

I

Transresistance

amplification

RL

Vs

RS

IL

+

Vin

-

Iin

+

VL

-


4/23

;outoutout

VZI

Output Impedance

It is the impedance viewed from the output port. This impedance can be interpreted as

the Thevenin impedance at the output port.

;ininin

VZI

Input impedance

It is the impedance viewed by the source of the input signal.

Definitions (3)

RLVs

RS

IL

+

Vin

-

Zin

Iin

+

VL

-

RSIout

+

Vout

-

Zout


5/23

BJT

VCC

R1

R2

RC

Rs

Vs

C1

RE

+

Vin

-

+

VL

-

C2

RL

BJT

VCC

R1

R2

Rs

Vs

C1

RE

+

Vin

-

+

VL

-

C2

R

L

BJT

VCC

R1

RC

Rs

Vs

C1

RE

+

Vin

-

+

VL

-

C2

RL

C3

R2

Common Collecttor Conf.Common Base Conf.. Common Emitter Conf.

Three configurations can be considered

Definitions (4)

CBC CEC CCC

Av

Ai

Rin

Rout

1

fe C L C L

Eie fe E

h R // R R // R

Rh h R

1P ie

fe E P R // h h R R

CR

inv

L

R

A R

1

1

1fe E L

ie fe E L

h R // R

h h R // R

1P ie fe E L PR // h h R // R R

in in

vL L

R R

A R R

1

ie P S E

fe

h R // R

h

R //

//fe

C L

ie

hR R

h

CR

//1

ieE

fe

hR

h

1

fein C

vL C L fe

hR R

A R R R h

1 2PR R // R

Electronics: a systems approach by N. Storey


6/23

hfeibib

hie

vout

R1//R2

+

-

vin

+

-

RERC//RL

hfeibib

hie

vout

R1//R2

+

-

vin +

-

RC

RE//RL

hfeibib

hie

vout+

-

vin

+

-

RE

RC//RL

Common Base C.

Common Emitter C.

Common Collecttor C.

Definitions (5)


7/23

Coupling capacitor

The amplifier is used to provide voltage and current levels adequate to drive the

load connected to the output. The use of a single BJT is sometimes not sufficient

to achieve this result.This limitation can be overcome by connecting in cascade several amplifiers,

so that the signal emitted by the source is increased by each amplifier constituting

the cascade. Each individual amplifier is called stage.

Capacitors are used to connect one stage to another, they are referred coupling

capacitors. The coupling capacitors have the function of providing insulation in DC so that

the bias of one stage does not affect that of the next stage.

These capacitors have to pass the AC signal from one stage to another with

minimum distortion.

Definitions (6)

+

VL

-

RL

IL

Zout

Vs

RS

+

Vin

-

Zin

Iin


8/23

Gain variation with frequency

Because of the introduced reactive elements and the parasitic reactive

elements the response of the amplifier is function of frequency.

By-pass capacitors

These capacitors are connected in parallel to a resistor, so AC signals on the

resistor are short circuited. In this way the AC and DC circuits are different.

1

fe C L

V

ie fe E

h R // RA

h h R

fe C L

V

ie

h R // RA

h

Definitions (7)

BJ

T

REC3

BJ

T

Re

R3

C3

BJT

R3

RE

C3

For example, in the case of CEC, a by-

pass capacitor on RE allows to obtain a

higher voltage gain.

For the capacitor by-pass the following configurations can be used :


9/23

Freq.

Freq.

Mid-band To simplify the study, it is useful to assume that there is a range of frequencies

(bandwidth) in which all the reactive effects are negligible.

Therefore in this range, gain (A0), input and output impedances are real quantities (Rin Rout).

Three different frequency ranges (low, medium and high frequencies) can be considered.

Three different frequency ranges correspond to three different dynamic circuits.

0l u

AA f A f

2

l u 0 dBdB dBA f A f A 3dB

Electronics: a systems approach by N. Storey (13.7)

Cut-off frequencies

The mid-band is delimited by two frequencies, thelower cut-off frequency fl (determined by coupling

and by-pass capacitors) and the upper cut-off

frequency fu (determined by the junction capacitance

and the parasitic effects).

The cutoff frequencies are defined by:

Definitions (8)


10/23

( );

0

L in LL Lj jL

v

in in in

in

V VVA e e

V V V

Mid-band

;

;

L

v

in

L

v

in

VA

V

VA

V

Common Emitter C.

Common Collector C.

RLVs

RS

IL

+

Vin

-

Zin

Iin

+

VL-

Zout

Definitions (9)


11/23

Observation

When the small signal conditions are verified the bias conditions are not

influenced by signals present, and the full analysis can be divided into two

sub-analysis: DC and AC. The AC analysis is often made by assuming the existence of the intermediate

band and analyzing the circuit in this band, where the reactive effects can be

neglected.

Therefore, it is important to know the cutoff frequencies that define the mid-band.

Syntesis of a small signal stageIn general, a synthesis process, without the computer aid is carried out taking

into account the behavior of the circuit in DC and in AC and estimating the effect of

the capacitors on the cut-off frequencies. At last, the synthesis, of a stage which

works at small signal, can be realized in the following steps:

1. Synthesis of the bias network.

2. Change of the bias network to meet the design specifications.

3. Choice of the capacitors to obtain the request lower cutoff frequency.

Definitions (10)


12/23

Small signal amplifiers


13/23

common collector stage

To design an amplifier, that by means of a suitable RL value, ensure a specific

current gain and voltage amplification equal to one.

The circuit solution is the:

L

Iin

IA

I

1. Synthesize the bias network (R1, R2, RE) .2. Select the RL value which ensures the desired current gain.

3. Choose the appropriate values for C1 and C2 which ensure the lower cutoff

frequency given in the project specifications.

Synthesis steps

BJT

R2

R1

RL

C1

C2

Vs

RS

VCC

Iin

IL

RE

+V

in

-

+V

L

-


14/23

Bias network for the CCC3 resistors

3 relations

BJT

VCC

R

1

R2VE

VB

RE

Rbase

2

2

2

2

10

21// 2

( )

(

10

11 R

1

1

0 0

2

1

)

1 R10

CQ CQ

BQ BQ

FE FE

BEQbaseFE E

B

CC CE E CQ B

CC B B Q

Q

E E

Q

Q

FE E

RV R R I V V

R

I II I I

h

V V R I I

h

VRR hI

R

I

R hI2

Synthesis of bias network for the CCC

Synthesis steps: 1


15/23

=FE FE min FE maxh h h

CC CEQ

E

C

V VR

I

2

1

10FE ER h R

1 2

CC BEQ E

BEQ E

V V VR R

V V

3) RE is obtained by:

4) R2 is obtained by:

5) R1 is obtained by:

Synthesis steps of bias network:

Synthesis steps: 1

1) Choose the supply voltage VCC and the transistor working point: IC, VCE.

2) From the datasheet VBEon and hFE values can be obtained. If only hFEmin and hFEmax

values are provided, hFE can be estimated using:


16/23

RL is obtained by the circuit analysis.

Synthesis steps: 2

1 1 1 1P E LfeinI V

L L L I P E Lfe

R // hie h R // RRA A

R R R A R h R // R

1 1E L

fe

L I P E L

R Rh

R A R R R

1

1L

fe

E

I

fe

E

P

R

R

R

h

A

h

R

1L

fe P

I fe

Rh R

A h

L

P

I

RR

A

If hfeRE>>RP or hfeRE> 10RP

If hfeRE> 10RP and hfe>10AI


17/23

To perform the AI and Rin measurements :

;RT Lin LT L

V VI I

R R

Mount the circuit introducing a test resistor RT

Measure VRT (using two probes)

Calculate Iin and IL

Calculate AI

Calculate Rin

1 2TR R // R

LI

in

IAI

inin

in

VR

I

BJT

R2

R1

RL

C1

C2

Vs

RS

VCC

Iin

IL

RE

RT +

Vin

-

+ VRT

-

+

VL

-


18/23

common emitter stage

To design a stage which ensures, in the passband, the desired voltage

amplification.

If the load can be selected a possible solution is the:

LV

in

VA

V

BJT

VCC

R1

R2

RC

Rs

Vs

C1

RE C3

+

Vin

-

+

VL

-

C2

RL

1. Synthesize the bias network (R1, R2, RC, RE) .2. Select the RL value which ensures the voltage gain desired.

3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which

ensure the lower cutoff frequency given in the project specifications

Synthesis steps


19/23

Synthesis of bias network for the CEC (and CBC)

4 resistors 4 relations

BJT

VCC

R1

R2

Rc

VE

RE

VB

Rbase

ICQ

2

2

2

2

10

1

2 1// 2 ( )1 2

0 10

11 R

1 10

)

0

(

1R

10

CC

E

CQ C

CC C C CEQ E CQ BQ

CC BQ

Q

BQ BQ

FE F

B

E

BEQba

E

se

FE E

BQ

Q E

FE E

VV

I II I I

h h

VRR h

V R I

RV R R I V

V

VR

I I

R

I

R

I

R h

I2

Synthesis steps: 1


20/23

=FE FE min FE maxh h h

10

CCE

E

CQ CQ

VV

R I I

CC CEQ E

C

CQ

V V VR

I

1 2

CC BEQ E

BEQ E

V V VR R

V V

3) RE is achived by:

4) RC is obtained by:

5) R2 is calculated by:

6) R1 is calculated by:

1) Choose the supply voltage VCC and the transistor working point: IC, VCE.

2) From the datasheet VBEon and hFE values can be obtained. If only hFEmin and hFEmax

values are provided, hFE can be estimated using:

Synthesis steps of bias network:

2 1 R10

FE ER h

Synthesis steps: 2


21/23

hie

R1//R

2

ib ib hfe

Vs

RS

ii

RL

1 1fe C L feV

ie L ie V C

h R // R hA

h R h A R

BJT

VCC

R1

R2

RC

Rs

Vs

C1

RE C3

+

Vin

-

+

VL

-

C2

RL

RL is obtained by circuit analysis.

Synthesis steps: 2


22/23

common emitter stage with

emitter degeneration

To design a stage to ensure, in the passband, a voltage amplification

If the load is fixed a possible solution is the:

LV

in

VA

V

1. Synthesize the bias network (R1, R2, RC, RE).Same approach of the CEC.

2. Select the R3 value.

3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which

ensure the lower cutoff frequency given in the project specifications.

Synthesis steps

BJT

VCC

R1

R2

RC

R3

Rs

Vs

C1

RE

C3+

Vin

-

+

V L

-

C2

RL

The emitter resistor is replaced with

RE//Series (C3-R3) to obtain different

impedance values in DC and AC.


23/23

hie

R1//R2

ib ib hfe

RE//R3Vs

RS

ii

RL

BJT

VCC

R1

R2

RC

R3

Rs

Vs

C1

RE

C3+

Vin

-

+

VL

-

C2

RL

3 33

3

1

1

1 1

fe C L VC LV

E C L Eie fe E

V

C L E

h R // R AR // RAR // R R // R R // Rh h R // R

A

R R // R R

Synthesis steps: 2

Small Signal Amplifier - BJT 1-23

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