Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto … · 2015. 9. 7. · grated Wake on...

LAN8742A/LAN8742AiSmall Footprint RMII 10/100 Ethernet Transceiver with HP

Auto-MDIX and flexPWR® Technology

Highlights• Single-Chip Ethernet Physical Layer Transceiver

(PHY)• Cable diagnostic support• Wake on LAN (WoL) support• Comprehensive flexPWR technology

- Flexible power management architecture- LVCMOS Variable I/O voltage range: +1.8 V to

+3.3 V- Integrated 1.2 V regulator with disable feature

• HP Auto-MDIX support• Miniature 24-pin VQFN, RoHS-compliant pack-

age (4 x 4 x 0.9 mm height)

Target Applications• Set-Top Boxes• Networked Printers and Servers• Test Instrumentation• LAN on Motherboard• Embedded Telecom Applications• Video Record/Playback Systems• Cable Modems/Routers• DSL Modems/Routers• Digital Video Recorders• IP and Video Phones• Wireless Access Points• Digital Televisions• Digital Media Adapters/Servers• Gaming Consoles• POE Applications

(Refer to Microchip Application Note 17.18)

Key Benefits• High-performance 10/100 Ethernet transceiver

- Compliant with IEEE802.3/802.3u (Fast Ethernet)- Compliant with ISO 802-3/IEEE 802.3

(10BASE-T)- Loop-back modes- Auto-negotiation- Automatic polarity detection and correction- Link status change wake-up detection- Vendor specific register functions- Supports the reduced pin count RMII interface

• Power and I/Os- Various low power modes- Integrated power-on reset circuit- Two status LED outputs- May be used with a single 3.3 V supply

• Additional Features- Ability to use a low cost 25 MHz crystal for

reduced BOM• Packaging

- 24-pin VQFN (4 x 4 mm), RoHS-compliant pack-age with RMII

• Environmental- Commercial temperature range (0°C to +70°C)- Industrial temperature range (-40°C to +85°C)

2013-2015 Microchip Technology Inc. DS00001989A-page 1

LAN8742A/LAN8742Ai

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected]. We welcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site: http://www.microchip.com• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.

DS00001989A-page 2 2013-2015 Microchip Technology Inc.

mailto:[email protected]://www.microchip.comhttp://www.microchip.com


LAN8742A/LAN8742AiTable of Contents1.0 Introduction ..................................................................................................................................................................................... 42.0 Pin Description and Configuration .................................................................................................................................................. 63.0 Functional Description .................................................................................................................................................................. 164.0 Register Descriptions .................................................................................................................................................................... 575.0 Operational Characteristics ......................................................................................................................................................... 1036.0 Package Outline .......................................................................................................................................................................... 116Appendix A: Revision History ............................................................................................................................................................ 119The Microchip Web Site .................................................................................................................................................................... 121Customer Change Notification Service ............................................................................................................................................. 121Customer Support ............................................................................................................................................................................. 121Product Identification System ........................................................................................................................................................... 122

LAN8742A/LAN8742Ai

1.0 INTRODUCTION

1.1 General Terms and ConventionsThe following is a list of the general terms used throughout this document:

1.2 General DescriptionThe LAN8742A/LAN8742Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/Ovoltage that is compliant with the IEEE 802.3 and 802.3u standards.

The LAN8742A/LAN8742Ai supports communication with an Ethernet MAC via a standard RMII interface. It contains afull-duplex 10-BASE-T/100BASE-TX transceiver and supports 10 Mbps (10BASE-T) and 100 Mbps (100BASE-TX)operation. The LAN8742A/LAN8742Ai implements auto-negotiation to automatically determine the best possible speedand duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over LAN cables. Inte-grated Wake on LAN (WoL) support provides a mechanism to trigger an interrupt upon reception of a perfect DA, broad-cast, magic packet, or wakeup frame.

The LAN8742A/LAN8742Ai supports both IEEE 802.3-2005 compliant and vendor-specific register functions. However,no register access is required for operation. The initial configuration may be selected via the configuration pins asdescribed in Section 3.7, "Configuration Straps". Register-selectable configuration options may be used to further definethe functionality of the transceiver.

The LAN8742A/LAN8742Ai can be programmed to support wake-on-LAN at the physical layer, allowing detection ofconfigurable Wake-up Frame and Magic packets. This feature allows filtering of packets at the PHY layer, without requir-ing MAC intervention. Additionally, the LAN8742A/LAN8742Ai supports cable diagnostics which allow the device toidentify opens/shorts and their location on the cable via vendor-specific registers.

Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6 V. The device can be configured to operateon a single 3.3 V supply utilizing an integrated 3.3 V to 1.2 V linear regulator. The linear regulator may be optionallydisabled, allowing usage of a high efficiency external regulator for lower system power dissipation.

The LAN8742A/LAN8742Ai is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperaturerange versions. A typical system application is shown in Figure 1-1. Figure 1-2 provides an internal block diagram of thedevice.

BYTE 8 bitsFIFO First In First Out buffer; often used for elasticity bufferMAC Media Access ControllerRMII™ Reduced Media Independent Interface N/A Not ApplicableX Indicates that a logic state is “don’t care” or undefined.RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero

for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses.

SMI Serial Management Interface

FIGURE 1-1: SYSTEM BLOCK DIAGRAM

LAN8742A/LAN8742Ai

10/100 Ethernet

MAC

RMII

Mode LED

Transformer

Crystal or Clock

Oscillator

MDI RJ45


LAN8742A/LAN8742Ai

FIGURE 1-2: ARCHITECTURAL OVERVIEW

RM

II Lo

gic

Interrupt Generator

LEDs

PLL

Receiver

DSP System:Clock

Data Recovery Equalizer

Squeltch & Filters

Analog-to-Digital

10M RX Logic

100M RX Logic

100M PLL

10M PLL

Transmitter10M

Transmitter

100M Transmitter

10M TX Logic

100M TX Logic

Central Bias

PHY Address Latches

LAN8742A/LAN8742Ai

RBIAS

LED1

nINT/REFCLKO

XTAL2

XTAL1/CLKIN

LED2

Management Control

Mode Control

Reset Control

MDIX Control

HP Auto-MDIX

RXP/RXN

TXP/TXN

TXD[0:1]

TXEN

RXD[0:1]

RXER

CRS_DV

MDC

MDIO

Auto-NegotiationnRST

MODE[0:2]

SMI

PHYAD0

WoL


LAN8742A/LAN8742Ai

2.0 PIN DESCRIPTION AND CONFIGURATIONFIGURE 2-1: 24-VQFN PIN ASSIGNMENTS (TOP VIEW)

Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low.For example, nRST indicates that the reset signal is active low.

Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer typesis provided in Section 2.2.

VSS

NOTE: Exposed pad (VSS) on bottom of package must be connected to ground

LAN8742A/LAN8742Ai24 PIN VQFN

(TOP VIEW)

MDIO

1

2

3

4

5

6

7 8 9 10 11 12

18

17

16

15

14

13

24 23 22 21 20 19VDDCR

XTAL1/CLKIN

XTAL2

LED1/nINT/nPME/REGOFF

LED2/nINT/nPME/nINTSEL

VDD2A TXD1

TXD0

TXEN

nRST

nINT/REFCLKO

MDCVD

D1A

TXN

TXP

RXN

RXP

RBIA

S

CRS_

DV/M

ODE2

RXER

/PHY

AD0

VDDI

O

RXD0

/MOD

E0

RXD1

/MOD

E1


LAN8742A/LAN8742Ai

TABLE 2-1: RMII SIGNALS

Num Pins Name Symbol Buffer Type Description

1 Transmit Data 0

TXD0 VIS The MAC transmits data to the transceiver using this signal.

1 Transmit Data 1

TXD1 VIS The MAC transmits data to the transceiver using this signal.

1 Transmit Enable

TXEN VIS(PD)

Indicates that valid transmission data is present on TXD[1:0].

1 Receive Data 0

RXD0 VO8 Bit 0 of the 2 data bits that are sent by the trans-ceiver on the receive path.

PHY Operat-ing Mode 0

Configuration Strap

MODE0 VIS(PU)

Combined with MODE1 and MODE2, this configu-ration strap sets the default PHY mode.

See Note 1 for more information on configuration straps.

Note: Refer to Section 3.7.2, "MODE[2:0]:Mode Configuration" for additionaldetails.

1 Receive Data 1

RXD1 VO8 Bit 1 of the 2 data bits that are sent by the trans-ceiver on the receive path.


Configuration Strap

MODE1 VIS(PU)



Note: Refer to Section 3.7.2, "MODE[2:0]:Mode Configuration" for additionaldetails.

1 Receive Error RXER VO8 This signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver.

PHY Address 0Configuration

Strap

PHYAD0 VIS(PD)

This configuration strap sets the transceiver’s SMI address.


Note: Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration" for additional information.


LAN8742A/LAN8742Ai

Note 1: Configuration strap values are latched on power-on reset and system reset. Configuration straps are iden-tified by an underlined symbol name. Signals that function as configuration straps must be augmented withan external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps" for additionalinformation.

1 Carrier Sense / Receive Data

Valid

CRS_DV VO8 This signal is asserted to indicate the receive medium is non-idle. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte (10101011) is received.

Note: Per the RMII standard, transmitted data is not looped back onto the receive data pins in 10BASE-T half-duplex mode.


Configuration Strap

MODE2 VIS(PU)



Note: Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration" for additional details.

TABLE 2-1: RMII SIGNALS (CONTINUED)



LAN8742A/LAN8742Ai

TABLE 2-2: LED PINS


1 LED 1 LED1 O12 This pin can be used to indicate link activity, link speed, nINT, or nPME as configured via the LED1 Function Select field of the Wakeup Control and Status Register (WUCSR).

Note: Refer to Section 3.8.1, "LEDs" and Sec-tion 3.8.4, "Wake on LAN (WoL)" for additional LED information.

Interrupt Out-put

nINT O12 Active low interrupt output.

Note: By default, the nINT signal is output on the nINT/REFCLKO pin. The nINT sig-nal can be optionally configured to out-put on the LED1 or LED2 pins. Refer to Section 3.6, "Interrupt Management" for additional details on device interrupts.

Power Man-agement Event

Output

nPME O12 Active low Power Management Event (PME) out-put.

Note: The nPME signal can be optionally con-figured to output on the LED1 or LED2 pins. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional nPME and WoL information.

Regulator Off Configuration

Strap

REGOFF IS(PD)

This configuration strap is used to disable the inter-nal 1.2 V regulator. When the regulator is disabled, external 1.2 V must be supplied to VDDCR.

• When REGOFF is pulled high to VDD2A with an external resistor, the internal regulator is disabled.

• When REGOFF is floating or pulled low, the internal regulator is enabled (default).


Note: Refer to Section 3.7.3, "REGOFF: Inter-nal +1.2 V Regulator Configuration" for additional details.


LAN8742A/LAN8742Ai

Note 1: Configuration strap values are latched on power-on reset and system reset. Configuration straps are iden-tified by an underlined symbol name. Signals that function as configuration straps must be augmented withan external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps" for additionalinformation.

1 LED 2 LED2 O12 This pin can be used to indicate link activity, link speed, nINT, or nPME as configured via the LED2 Function Select field of the Wakeup Control and Status Register (WUCSR).

Note: Refer to Section 3.8.1, "LEDs" and Sec-tion 3.8.4, "Wake on LAN (WoL)" for additional LED information.

Interrupt Out-put

nINT O12 Active low interrupt output.

Note: By default, the nINT signal is output on the nINT/REFCLKO pin. The nINT sig-nal can be optionally configured to out-put on the LED1 or LED2 pins. Refer to Section 3.6, "Interrupt Management" for additional details on device interrupts.

Power Man-agement Event

Output

nPME O12 Active low Power Management Event (PME) out-put.

Note: The nPME signal can be optionally con-figured to output on the LED1 or LED2 pins. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional nPME and WoL information.

nINT/REFCLKO

Function Select Configuration

Strap

nINTSEL IS(PU)

This configuration strap selects the mode of the nINT/REFCLKO pin.

• When nINTSEL is floated or pulled to VDD2A, nINT is selected for operation on the nINT/REFCLKO pin (default).

• When nINTSEL is pulled low to VSS, REF-CLKO is selected for operation on the nINT/REFCLKO pin.


Note: Refer to See Section 3.8.1.6, "nINTSEL and LED2 Polarity Selection" for addi-tional information.

TABLE 2-2: LED PINS (CONTINUED)



LAN8742A/LAN8742Ai

TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS


1 SMI Data Input/Output

MDIO VIS/VO8(PU)

Serial Management Interface data input/output

1 SMI Clock MDC VIS Serial Management Interface clock

TABLE 2-4: ETHERNET PINS


1 Ethernet TX/RX Posi-tive Channel

1

TXP AIO Transmit/Receive Positive Channel 1

1 Ethernet TX/RX Nega-tive Channel

1

TXN AIO Transmit/Receive Negative Channel 1

1 Ethernet TX/RX Posi-tive Channel

2

RXP AIO Transmit/Receive Positive Channel 2

1 Ethernet TX/RX Nega-tive Channel

2

RXN AIO Transmit/Receive Negative Channel 2

TABLE 2-5: MISCELLANEOUS PINS


1 External Crystal Input

XTAL1 ICLK External crystal input

External Clock Input

CLKIN ICLK Single-ended clock oscillator input.

Note: When using a single ended clockoscillator, XTAL2 should be left uncon-nected.

1 External Crystal Out-

put

XTAL2 OCLK External crystal output

1 External Reset

nRST VIS(PU)

System reset. This signal is active low.


LAN8742A/LAN8742Ai

1 Interrupt Out-put

nINT VOD8(PU)

Active low interrupt output. Place an external resistor pull-up to VDDIO.

Note: The nINT signal can be optionally con-figured to output on the LED1 or LED2 pins. Refer to Section 3.6, "Interrupt Management" for additional details on device interrupts.

Note: Refer to Section 3.8.1.6, "nINTSEL and LED2 Polarity Selection" for details on how the nINTSEL configura-tion strap is used to determine the function of this pin.

Reference Clock Output

REFCLKO VO8 This optional 50 MHz clock output is derived from the 25 MHz crystal oscillator. REFCLKO is select-able via the nINTSEL configuration strap.

Note: Refer to Section 3.7.4.2, "REF_CLK Out Mode" for additional details on device interrupts.

Note: Refer to Section 3.8.1.6, "nINTSEL and LED2 Polarity Selection" for details on how the nINTSEL configura-tion strap is used to determine the function of this pin.

TABLE 2-6: ANALOG REFERENCE PINS


1 External 1% Bias Resistor

Input

RBIAS AI This pin requires connection of a 12.1 kΩ (1%) resistor to ground.

Refer to the LAN8742A/LAN8742Ai reference schematic for connection information.

Note: The nominal voltage is 1.2 V and theresistor will dissipate approximately1 mW of power.

TABLE 2-5: MISCELLANEOUS PINS (CONTINUED)



LAN8742A/LAN8742Ai

TABLE 2-7: POWER PINS


1 +1.8 V to +3.3 V Variable I/O

Power

VDDIO P +1.8 V to +3.3 V variable I/O power.


1 +1.2 V Digital Core Power

Supply

VDDCR P Supplied by the on-chip regulator unless config-ured for regulator off mode via the REGOFF con-figuration strap.


Note: 1 µF and 470 pF decoupling capaci-tors in parallel to ground should beused on this pin.

1 +3.3 V Channel 1 Analog Port

Power

VDD1A P +3.3 V Analog Port Power to Channel 1.


1 +3.3 V Channel 2 Analog Port

Power

VDD2A P +3.3 V Analog Port Power to Channel 2 and the internal regulator.


1 Ground VSS P Common ground. This exposed pad must be con-nected to the ground plane with a via array.


LAN8742A/LAN8742Ai

2.1 Pin Assignments

TABLE 2-8: 24-VQFN PACKAGE PIN ASSIGNMENTS

Pin Num Pin Name Pin Num Pin Name

1 VDD2A 13 MDC2 LED2/nINT/nPME/nINTSEL 14 nINT/REFCLKO3 LED1/nINT/nPME/REGOFF 15 nRST4 XTAL2 16 TXEN5 XTAL1/CLKIN 17 TXD06 VDDCR 18 TXD17 RXD1/MODE1 19 VDD1A8 RXD0/MODE0 20 TXN9 VDDIO 21 TXP10 RXER/PHYAD0 22 RXN11 CRS_DV/MODE2 23 RXP12 MDIO 24 RBIAS


LAN8742A/LAN8742Ai

2.2 Buffer Types

TABLE 2-9: BUFFER TYPES

Buffer Type Description

IS Schmitt-triggered inputO12 Output with 12 mA sink and 12 mA sourceVIS Variable voltage Schmitt-triggered inputVO8 Variable voltage output with 8 mA sink and 8 mA source

VOD8 Variable voltage open-drain output with 8 mA sinkPU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups

are always enabled.

Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely oninternal resistors to drive signals external to the device. When connected to a loadthat must be pulled high, an external resistor must be added.

PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled.

Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not relyon internal resistors to drive signals external to the device. When connected to aload that must be pulled low, an external resistor must be added.

AI Analog inputAIO Analog bi-directionalICLK Crystal oscillator input pinOCLK Crystal oscillator output pin

P Power pin

Note: The digital signals are not 5 V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*" for additionalbuffer information.

Note: Sink and source capabilities are dependent on the VDDIO voltage. Refer to Section 5.1, "Absolute Maxi-mum Ratings*" for additional information.


LAN8742A/LAN8742Ai

3.0 FUNCTIONAL DESCRIPTIONThis chapter provides functional descriptions of the various device features. These features have been categorized intothe following sections:

• Transceiver• Auto-Negotiation• HP Auto-MDIX Support• MAC Interface• Serial Management Interface (SMI)• Interrupt Management• Configuration Straps• Miscellaneous Functions• Application Diagrams

3.1 Transceiver

3.1.1 100BASE-TX TRANSMITThe 100BASE-TX transmit data path is shown in Figure 3-1. Each major block is explained in the following subsections.

3.1.1.1 100BASE-TX Transmit Data Across the RMII InterfaceThe MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data islatched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50 MHz data.

3.1.1.2 4B/5B EncodingThe transmit data passes from the RMII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to5-bit symbols (known as “code-groups”) according to Table 3-1. Each 4-bit data-nibble is mapped to 16 of the 32 pos-sible code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. Theremaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is/I/, a transmit error code-group is /H/, etc.

FIGURE 3-1: 100BASE-TX TRANSMIT DATA PATH

MAC

Tx Driver

MLT-3 Converter

NRZI Converter

4B/5B Encoder

CAT-5RJ45

25 MHz by5 bits

NRZI

MLT-3MLT-3

MLT-3

Scrambler and PISORMII

25 MHzby 4 bits

Ext Ref_CLK

PLL

RMII 50 MHz by 2 bits

MLT-3Magnetics

125 Mbps Serial


LAN8742A/LAN8742Ai

TABLE 3-1: 4B/5B CODE TABLE

Code Group Sym Receiver Interpretation Transmitter Interpretation

11110 0 0 0000 DATA 0 0000 DATA01001 1 1 0001 1 000110100 2 2 0010 2 001010101 3 3 0011 3 001101010 4 4 0100 4 010001011 5 5 0101 5 010101110 6 6 0110 6 011001111 7 7 0111 7 011110010 8 8 1000 8 100010011 9 9 1001 9 100110110 A A 1010 A 101010111 B B 1011 B 101111010 C C 1100 C 110011011 D D 1101 D 110111100 E E 1110 E 111011101 F F 1111 F 111111111 I IDLE Sent after /T/R until TXEN11000 J First nibble of SSD, translated to “0101”

following IDLE, else RXER Sent for rising TXEN

10001 K Second nibble of SSD, translated to “0101” following J, else RXER

Sent for rising TXEN

01101 T First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RXER

Sent for falling TXEN

00111 R Second nibble of ESD, causes deasser-tion of CRS if following /T/, else assertion of RXER

Sent for falling TXEN

00100 H Transmit Error Symbol Sent for rising TXER00110 V INVALID, RXER if during RXDV INVALID11001 V INVALID, RXER if during RXDV INVALID00000 V INVALID, RXER if during RXDV INVALID00001 V INVALID, RXER if during RXDV INVALID00010 V INVALID, RXER if during RXDV INVALID00011 V INVALID, RXER if during RXDV INVALID00101 V INVALID, RXER if during RXDV INVALID01000 V INVALID, RXER if during RXDV INVALID01100 V INVALID, RXER if during RXDV INVALID10000 V INVALID, RXER if during RXDV INVALID


LAN8742A/LAN8742Ai

3.1.1.3 ScramblingRepeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-bandpeaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entirechannel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from beingradiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiverapplications, such as repeaters or switches, each transceiver will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

3.1.1.4 NRZI and MLT-3 EncodingThe scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125 MHz NRZIdata stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents acode bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.1.1.5 100M Transmit DriverThe MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP andTXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals passthrough the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100 Ωimpedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.1.1.6 100M Phase Lock Loop (PLL)The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the100BASE-TX transmitter.

3.1.2 100BASE-TX RECEIVEThe 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.

FIGURE 3-2: 100BASE-TX RECEIVE DATA PATH

MAC

A/D Converter

MLT-3 Converter

NRZI Converter

4B/5B Decoder

Magnetics CAT-5RJ45

PLL

RMII 50 MHz by 2 bits25 MHz by

5 bits

NRZI

MLT-3MLT-3 MLT-3

6 bit Data

Descrambler and SIPO

125 Mbps Serial

DSP: Timing recovery, Equalizer and BLW Correction

MLT-3

RMII25 MHzby 4 bits

Ext Ref_CLK


LAN8742A/LAN8742Ai

3.1.2.1 100M Receive InputThe MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADCsamples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levelssuch that the full dynamic range of the ADC can be used.

3.1.2.2 Equalizer, Baseline Wander Correction and Clock and Data RecoveryThe 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizercan restore the signal for any good-quality CAT-5 cable between 1 m and 100 m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and canreceive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing unit of the DSP,selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used toextract the serial data from the received signal.

3.1.2.3 NRZI and MLT-3 DecodingThe DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to anNRZI data stream.

3.1.2.4 DescramblingThe descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In ParallelOut (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Oncesynchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbolswithin a window of 4000 bytes (40 µs). This window ensures that a maximum packet size of 1514 bytes, allowed by theIEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,receive operation is aborted and the descrambler re-starts the synchronization process.

3.1.2.5 AlignmentThe de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start offrame.

3.1.2.6 5B/4B DecodingThe 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-sented on the RXD[1:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC pre-amble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data isavailable on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End ofStream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assertthe carrier sense and receive data valid signals.

Note: These symbols are not translated into data.


LAN8742A/LAN8742Ai

3.1.2.7 Receive Data Valid SignalThe Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on theRXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXDis aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failureor SIGDET becomes false.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MIImode).

3.1.2.8 Receiver ErrorsDuring a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrarydata is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is beingdecoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that theValid Data signal is not yet asserted when the bad SSD error occurs.

3.1.2.9 100M Receive Data Across the RMII InterfaceThe 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50 MHz.The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK).

3.1.3 10BASE-T TRANSMITData to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from theMII at a rate of 2.5 MHz and converts them to a 10 Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

• MII (digital)• TX 10M (digital)• 10M Transmitter (analog)• 10M PLL (analog)

3.1.3.1 10M Transmit Data Across the MII/RMII InterfaceThe MAC controller drives the transmit data onto the TXD bus. TXD[1:0] shall transition synchronously with respect toREF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be “00” toindicate idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved forout-of-band signaling (to be defined). Values other than “00” on TXD[1:0] while TXEN is deasserted shall be ignored bythe device.TXD[1:0] shall provide valid data for each REF_CLK period while TXEN is asserted.

In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the trans-mitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted duringthis time. The transceiver also supports the SQE (Heartbeat) signal.

FIGURE 3-3: RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS

5 D5 data data data dataRXD

RX_DV

RX_CLK

5 D5 data data data dataCLEAR-TEXT 5J K

5 5 5

T R Idle


LAN8742A/LAN8742Ai

3.1.3.2 Manchester EncodingThe 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10 Mbps serial NRZI data stream. The10M PLL locks onto the external clock or internal oscillator and produces a 20 MHz clock. This is used to Manchesterencode the NRZ data stream. When no data is being transmitted (TXEN is low), the 10M TX block outputs Normal LinkPulses (NLPs) to maintain communications with the remote link partner.

3.1.3.3 10M Transmit DriversThe Manchester-encoded data is sent to the analog transmitter where it is shaped and filtered before being driven outas a differential signal across the TXP and TXN outputs.

3.1.4 10BASE-T RECEIVEThe 10BASE-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers thereceive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to4-bit data nibbles which are passed to the controller via MII at a rate of 2.5 MHz.

This 10M receiver uses the following blocks:

• Filter and SQUELCH (analog)• 10M PLL (analog)• RX 10M (digital)• MII (digital)

3.1.4.1 10M Receive Input and SquelchThe Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio magnetics. It isfirst filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set ofamplitude and timing comparators that normally reject differential voltage levels below 300 mV and detect and recognizedifferential voltages above 585 mV.

3.1.4.2 Manchester DecodingThe output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded data. The polarityof the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and viceversa), the condition is identified and corrected. The reversed condition is indicated by the XPOL bit of the Special Con-trol/Status Indications Register. The 10M PLL is locked onto the received Manchester signal, from which the 20 MHzcock is generated. Using this clock, the Manchester encoded data is extracted and converted to a 10 MHz NRZI datastream. It is then converted from serial to 4-bit wide parallel data.

The 10M RX block also detects valid 10BASE-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link.

3.1.4.3 10M Receive Data Across the RMII InterfaceThe 2-bit data nibbles are sent to the RMII block. These data nibbles are valid on the rising edge of the RMII REF_CLK.

3.1.4.4 Jabber DetectionJabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length,usually due to a fault condition, which results in holding the TXEN input for a long period. Special logic is used to detectthe jabber state and abort the transmission to the line within 45 ms. Once TXEN is deasserted, the logic resets the jabbercondition.

As shown in Section 4.2.2, "Basic Status Register", the Jabber Detect bit indicates that a jabber condition was detected.


LAN8742A/LAN8742Ai

3.2 Auto-NegotiationThe purpose of the auto-negotiation function is to automatically configure the transceiver to the optimum link parametersbased on the capabilities of its link partner. Auto-negotiation is a mechanism for exchanging configuration informationbetween two link-partners and automatically selecting the highest performance mode of operation supported by bothsides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification.

Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via theSerial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits ofthe PHY Special Control/Status Register, as well as in the Auto Negotiation Link Partner Ability Register. The auto-nego-tiation protocol is a purely physical layer activity and proceeds independently of the MAC controller.

The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement Register. The defaultadvertised by the transceiver is determined by user-defined on-chip signal options.

The following blocks are activated during an auto-negotiation session:

• Auto-negotiation (digital)• 100M ADC (analog)• 100M PLL (analog)• 100M equalizer/BLW/clock recovery (DSP)• 10M SQUELCH (analog)• 10M PLL (analog)• 10M Transmitter (analog)

When enabled, auto-negotiation is started by the occurrence of one of the following events:

• Hardware reset• Software reset• Power-down reset• Link status down• Setting the Restart Auto-Negotiate bit of the Basic Control Register

On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of Fast Link Pulses(FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can passuncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numberedpulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent,contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.

The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). Itadvertises its technology ability according to the bits set in the Auto Negotiation Advertisement Register.

There are 4 possible matches of the technology abilities. In the order of priority these are:

• 100M Full Duplex (Highest Priority) • 100M Half Duplex• 10M Full Duplex • 10M Half Duplex (Lowest Priority)

If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is capable of 10M and100M, then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half andfull duplex modes, then auto-negotiation selects full duplex as the highest performance operation.

Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any dif-ference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiationwill also re-start if not all of the required FLP bursts are received.

The capabilities advertised during auto-negotiation by the transceiver are initially determined by the logic levels latchedon the MODE[2:0] configuration straps after reset completes. These configuration straps can also be used to disableauto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration" for additional information.


LAN8742A/LAN8742Ai

Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of the capabilitiesadvertised by the transceiver. Writing the Auto Negotiation Advertisement Register does not automatically re-start auto-negotiation. The Restart Auto-Negotiate bit of the Basic Control Register must be set before the new abilities will beadvertised. Auto-negotiation can also be disabled via software by clearing the Auto-Negotiation Enable bit of the BasicControl Register.

3.2.1 PARALLEL DETECTIONIf the LAN8742A/LAN8742Ai is connected to a device lacking the ability to auto-negotiate (i.e., no FLPs are detected),it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In thiscase the link is presumed to be half duplex per the IEEE standard. This ability is known as “Parallel Detection.” Thisfeature ensures interoperability with legacy link partners. If a link is formed via parallel detection, then the Link PartnerAuto-Negotiation Able bit of the Auto Negotiation Expansion Register is cleared to indicate that the Link Partner is notcapable of auto-negotiation. The controller has access to this information via the management interface. If a fault occursduring parallel detection, the Parallel Detection Fault bit of Link Partner Auto-Negotiation Able is set.

Auto Negotiation Link Partner Ability Register is used to store the link partner ability information, which is coded in thereceived FLPs. If the link partner is not auto-negotiation capable, then the Auto Negotiation Link Partner Ability Registeris updated after completion of parallel detection to reflect the speed capability of the link partner.

3.2.2 RESTARTING AUTO-NEGOTIATIONAuto-negotiation can be restarted at any time by setting the Restart Auto-Negotiate bit of the Basic Control Register.Auto-negotiation will also restart if the link is broken at any time. A broken link is caused by signal loss. This may occurbecause of a cable break, or because of an interruption in the signal transmitted by the link partner. Auto-negotiationresumes in an attempt to determine the new link configuration.

If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the Basic Control Reg-ister, the LAN8742A/LAN8742Ai will respond by stopping all transmission/receiving operations. Once the break_link_-timer is completed in the auto-negotiation state-machine (approximately 1250 ms), auto-negotiation will re-start. In thiscase, the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negoti-ation.

3.2.3 DISABLING AUTO-NEGOTIATIONAuto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control Register to zero. Thedevice will then force its speed of operation to reflect the information in the Basic Control Register (Speed Select bit andDuplex Mode bit). These bits should be ignored when auto-negotiation is enabled.

3.2.4 HALF VS. FULL DUPLEXHalf duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle net-work traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. Ifdata is received while the transceiver is transmitting, a collision results.

In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS respondsonly to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.


LAN8742A/LAN8742Ai

3.3 HP Auto-MDIX SupportHP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-TX) media UTP interconnect cable withoutconsideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable, or a cross-over patchcable, as shown in Figure 3-4, the device’s Auto-MDIX transceiver is capable of configuring the TXP/TXN and RXP/RXNpins for correct transceiver operation.

The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairsare interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics andtermination of an Auto-MDIX design.

The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status Indications Register.

Note: When operating in 10BASE-T or 100BASE-TX manual modes, the Auto-MDIX crossover time can beextended via the Extend Manual 10/100 Auto-MDIX Crossover Time bit of the EDPD NLP/Crossover Tim-eRegister. Refer to Section 4.2.12, "EDPD NLP/Crossover TimeRegister" for additional information.

FIGURE 3-4: DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION

1

2

3

4

5

6

7

8

TXP

TXN

RXP

Not Used

Not Used

RXN

Not Used

Not Used

1

2

3

4

5

6

7

8

TXP

TXN

RXP

Not Used

Not Used

RXN

Not Used

Not Used

Direct Connect Cable

RJ-45 8-pin straight-through for 10BASE-T/100BASE-TX

signaling

1

2

3

4

5

6

7

8

TXP

TXN

RXP

Not Used

Not Used

RXN

Not Used

Not Used

1

2

3

4

5

6

7

8

TXP

TXN

RXP

Not Used

Not Used

RXN

Not Used

Not Used

Cross-Over Cable

RJ-45 8-pin cross-over for 10BASE-T/100BASE-TX

signaling


LAN8742A/LAN8742Ai

3.4 MAC Interface

3.4.1 RMII The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernettransceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devicesincorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as theport counts increase. RMII reduces this pin count while retaining a management interface (MDIO/MDC) that is identicalto MII.

The RMII interface has the following characteristics:

• It is capable of supporting 10 Mbps and 100 Mbps data rates• A single clock reference is used for both transmit and receive• It provides independent 2-bit (di-bit) wide transmit and receive data paths• It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes

The RMII includes the following interface signals (1 optional):

• Transmit data - TXD[1:0]• Transmit strobe - TXEN• Receive data - RXD[1:0]• Receive error - RXER (Optional) • Carrier sense - CRS_DV• Reference Clock - (RMII references usually define this signal as REF_CLK)

3.4.1.1 CRS_DV - Carrier Sense/Receive Data ValidThe CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously ondetection of carrier due to the criteria relevant to the operating mode. In 10BASE-T mode when squelch is passed, orin 100BASE-TX mode when 2 non-contiguous zeroes in 10 bits are detected, the carrier is said to be detected.

Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the firstdi-bit of a nibble onto RXD[1:0] (i.e., CRS_DV is deasserted only on nibble boundaries). If the device has additional bitsto be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device shall assert CRS_DV on cyclesof REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of REF_CLK which pres-ent the first di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25 MHz in 100 Mbps modeand 2.5 MHz in 10 Mbps mode when CRS ends before RXDV (i.e., the FIFO still has bits to transfer when the carrierevent ends). Therefore, the MAC can accurately recover RXDV and CRS.

During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] isconsidered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative toREF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place.

3.4.1.2 Reference Clock (REF_CLK)The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device useselasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.

Note: The RMII interface can be disabled (outputs driven low) via the Interface Disable bit of the Wakeup Controland Status Register (WUCSR).


LAN8742A/LAN8742Ai

3.5 Serial Management Interface (SMI)The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0through 6 as required by clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to 31 allowed by thespecification. Device registers are detailed in Chapter 4, "Register Descriptions".

At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock provided by theStation Management Controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data(commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges ofthe MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutiverising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easilydriven by the I/O port of a microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shownin Figure 3-5 and Figure 3-6. The timing relationships of the MDIO signals are further described in Section 5.6.5, "SMITiming".

FIGURE 3-5: MDIO TIMING AND FRAME STRUCTURE - READ CYCLE

FIGURE 3-6: MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE

MDC

MDIO

Read Cycle

...32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D1...D15 D14 D0

Preamble Start ofFrameOP

Code PHY Address Register AddressTurn

AroundData

Data From PhyData To Phy

MDC

MDIO ...32 1's 0 1 10 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

Write Cycle

D15 D14 D1 D0

...

DataPreamble Start ofFrameOP

Code PHY Address Register AddressTurn

Around

Data To Phy


LAN8742A/LAN8742Ai

3.6 Interrupt ManagementThe device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. Thisinterrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain eventsare detected as setup by the Interrupt Mask Register.

The nINT signal can be selected to output on three different pins:

• nINT/REFCLKO (See Section 3.7.4, "nINTSEL: nINT/REFCLKO Configuration" for configuration information)

• LED1(See Section 3.8.1, "LEDs" for configuration information)

• LED2(See Section 3.8.1, "LEDs" for configuration information)

The device’s interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Bothsystems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-assert the nINT interrupt output. These modes are detailed in the following subsections.

Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternativeinterrupt mode requires setup after a power-up or hard reset.

Note: In addition to the main interrupts described in this section, an nPME pin is provided exclusively for WoLspecific interrupts. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional information on nPME.


LAN8742A/LAN8742Ai

3.6.1 PRIMARY INTERRUPT SYSTEMThe Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). ThePrimary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the cor-responding mask bit in the Interrupt Mask Register (see Table 3-2). Then when the event to assert nINT is true, the nINToutput will be asserted. When the corresponding event to deassert nINT is true, then the nINT will be de-asserted.

Note 1: If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assertfor 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To preventan unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of theENERGYON interrupt service routine.

TABLE 3-2: INTERRUPT MANAGEMENT TABLE

Mask Interrupt Source Flag Interrupt Source Event to Assert nINTEvent to

De-Assert nINT

30.8 29.8 WoL 3.32784.7:4 nPME Rising 3.32784.7:4

or’ed together

3.32784.7:4 or’ed together low or reading register 29

30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 (see Note 1)

Falling 17.1 orReading register 29

30.6 29.6 Auto-Negotiation Complete

1.5 Auto-Negotiate Complete

Rising 1.5 Falling 1.5 orReading register 29

30.5 29.5 Remote Fault Detected

1.4 Remote Fault Rising 1.4 Falling 1.4, or Reading register 1 or Reading register 29

30.4 29.4 Link Down 1.2 Link Status Falling 1.2 Reading register 1 orReading register 29

30.3 29.3 Auto-Negotiation LP Acknowledge

5.14 Acknowledge Rising 5.14 Falling 5.14 orReading register 29

30.2 29.2 Parallel Detection Fault

6.4 Parallel Detec-tion Fault

Rising 6.4 Falling 6.4 or Reading register 6, orReading register 29, or Re-Auto Negotiate or

Link down30.1 29.1 Auto-Negotiation

Page Received6.1 Page Received Rising 6.1 Falling 6.1 or

Reading register 6, orReading register 29, orRe-Auto Negotiate, or

Link down.

Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If nosignal is present, then both ENERGYON and INT7 will clear within a few milliseconds.


LAN8742A/LAN8742Ai

3.6.2 ALTERNATE INTERRUPT SYSTEMThe Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to “1”. In thismode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3-3). To Clear an interrupt,either clear the corresponding bit in the Interrupt Mask Register to deassert the nINT output, or clear the interruptsource, and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will causethe state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. Ifthe Condition to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the Conditionto deassert is false, then the Interrupt Source Flag remains set, and the nINT remains asserted.

For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable isplugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nINT will be asserted low. To de-assert the nINT interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing thecable and then writing a ‘1’ to the INT7 bit in the Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the InterruptMask Register).TABLE 3-3: ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE

Mask Interrupt Source Flag Interrupt Source Event to Assert nINTCondition to

DeAssertBit to Clear

nINT

30.8 29.8 WoL 3.32784.7:4 nPME Rising 3.32784.7:4

or’ed

3.32784.7:4 all low

29.8

30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.730.6 29.6 Auto-Negotiation

Complete1.5 Auto-Negotiate

CompleteRising 1.5 1.5 low 29.6

30.5 29.5 Remote Fault Detected

1.4 Remote Fault Rising 1.4 1.4 low 29.5

30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.430.3 29.3 Auto-Negotiation

LP Acknowledge5.14 Acknowledge Rising 5.14 5.14 low 29.3

30.2 29.2 Parallel Detection Fault

6.4 Parallel Detec-tion Fault

Rising 6.4 6.4 low 29.2

30.1 29.1 Auto-Negotiation Page Received

6.1 Page Received Rising 6.1 6.1 low 29.1

Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If nosignal is present, then both ENERGYON and INT7 will clear within a few milliseconds.


LAN8742A/LAN8742Ai

3.7 Configuration StrapsConfiguration straps allow various features of the device to be automatically configured to user defined values. Config-uration straps are latched upon Power-On Reset (POR) and pin reset (nRST). Configuration straps include internalresistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connectedto a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that itreaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of anexternal resistor.

3.7.1 PHYAD[0]: PHY ADDRESS CONFIGURATIONThe PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into an internal registerat the end of a hardware reset (default = 0b). In a multi-PHY application (such as a repeater), the controller is able tomanage each PHY via the unique address. Each PHY checks each management data frame for a matching address inthe relevant bits. When a match is recognized, the PHY responds to that particular frame. The PHY address is also usedto seed the scrambler. In a multi-PHY application, this ensures that the scramblers are out of synchronization and dis-perses the electromagnetic radiation across the frequency spectrum.

The device’s SMI address may be configured using hardware configuration to either the value 0 or 1. The user can con-figure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can bewritten (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register.The PHYAD0 hardware configuration strap is multiplexed with the RXER pin.

3.7.2 MODE[2:0]: MODE CONFIGURATIONThe MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block isthen configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,the configuration of the 10/100 digital block is controlled by the register bit values and the MODE[2:0] configurationstraps have no affect.

The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-4. The usermay configure the transceiver mode by writing the SMI registers.

Note: The system designer must guarantee that configuration strap pins meet the timing requirements specifiedin Section 5.6.3, "Power-On nRST & Configuration Strap Timing". If configuration strap pins are not at thecorrect voltage level prior to being latched, the device may capture incorrect strap values.

Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except for REGOFFand nINTSEL which should be tied to VDD2A.

TABLE 3-4: MODE[2:0] BUS

MODE[2:0] Mode Definitions

Default Register Bit Values

Register 0 Register 4

[13,12,10,8] [8,7,6,5]

000 10BASE-T Half Duplex. Auto-negotiation disabled. 0000 N/A001 10BASE-T Full Duplex. Auto-negotiation disabled. 0001 N/A010 100BASE-TX Half Duplex. Auto-negotiation disabled.

CRS is active during Transmit & Receive.1000 N/A

011 100BASE-TX Full Duplex. Auto-negotiation disabled.CRS is active during Receive.

1001 N/A

100 100BASE-TX Half Duplex is advertised. Auto-negoti-ation enabled.CRS is active during Transmit & Receive.

1100 0100

101 Repeater mode. Auto-negotiation enabled. 100BASE-TX Half Duplex is advertised. CRS is active during Receive.

1100 0100


LAN8742A/LAN8742Ai

The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3-5.

3.7.3 REGOFF: INTERNAL +1.2 V REGULATOR CONFIGURATIONThe incorporation of flexPWR technology provides the ability to disable the internal +1.2 V regulator. When the regulatoris disabled, an external +1.2 V must be supplied to the VDDCR pin. Disabling the internal +1.2 V regulator makes itpossible to reduce total system power, since an external switching regulator with greater efficiency (versus the internallinear regulator) can be used to provide +1.2 V to the transceiver circuitry.

3.7.3.1 Disabling the Internal +1.2 V RegulatorTo disable the +1.2 V internal regulator, a pull-up strapping resistor should be connected from the REGOFF configura-tion strap to VDD2A. At power-on, after both VDDIO and VDD2A are within specification, the transceiver will sampleREGOFF to determine whether the internal regulator should turn on. If the pin is sampled at a voltage greater than VIH,then the internal regulator is disabled and the system must supply +1.2 V to the VDDCR pin. The VDDIO voltage mustbe at least 80% of the operating voltage level (1.44 V when operating at 1.8 V, 2.0 V when operating at 2.5 V, 2.64 Vwhen operating at 3.3 V) before voltage is applied to VDDCR. As described in Section 3.7.3.2, when REGOFF is leftfloating or connected to VSS, the internal regulator is enabled and the system is not required to supply +1.2 V to theVDDCR pin.

3.7.3.2 Enabling the Internal +1.2 V RegulatorThe +1.2 V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the regulator off modeusing the REGOFF configuration strap as described in Section 3.7.3.1. By default, the internal +1.2 V regulator isenabled when REGOFF is floating (due to the internal pull-down resistor). During power-on, if REGOFF is sampledbelow VIL, then the internal +1.2 V regulator will turn on and operate with power from the VDD2A pin.

110 Power-Down mode. In this mode the transceiver will wake-up in Power-Down mode. The transceiver can-not be used when the MODE[2:0] bits are set to this mode. To exit this mode, the MODE bits in Register 18.7:5 (see Section 4.2.14, "Special Modes Register") must be configured to some other value and a soft reset must be issued.

N/A N/A

111 All capable. Auto-negotiation enabled. X10X 1111

TABLE 3-5: PIN NAMES FOR MODE BITS

MODE Bit Pin Name

MODE[0] RXD0/MODE0MODE[1] RXD1/MODE1MODE[2] CRS_DV/MODE2

Note: Because the REGOFF configuration strap shares functionality with the LED1 pin, proper considerationmust also be given to the LED polarity. Refer to Section 3.8.1, "LEDs" for additional information on the rela-tion between REGOFF and the LED1 polarity.

TABLE 3-4: MODE[2:0] BUS (CONTINUED)

MODE[2:0] Mode Definitions

Default Register Bit Values

Register 0 Register 4

[13,12,10,8] [8,7,6,5]


LAN8742A/LAN8742Ai

3.7.4 nINTSEL: nINT/REFCLKO CONFIGURATIONThe nINTSEL configuration strap is used to select between one of two available modes: REF_CLK In Mode (nINT) andREF_CLK Out Mode. The configured mode determines the function of the nINT/REFCLKO pin. The nINTSEL configu-ration strap is latched at POR and on the rising edge of the nRST. By default, nINTSEL is configured for nINT mode viathe internal pull-up resistor.

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.However, on the receive data path, the receiver recovers the clock from the incoming data stream. The device useselasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.

In REF_CLK In Mode, the 50 MHz REF_CLK is driven on the XTAL1/CLKIN pin. This is the traditional system configu-ration when using RMII, and is described in Section 3.7.4.1. When configured for REF_CLK Out Mode, the device gen-erates the 50 MHz RMII REF_CLK and the nINT interrupt is not available. REF_CLK Out Mode allows a low-cost25 MHz crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and isdescribed in Section 3.7.4.2.

TABLE 3-6: nINTSEL CONFIGURATION

Strap Value Mode REF_CLK Description

nINTSEL = 0 REF_CLK Out Mode nINT/REFCLKO is the source of REF_CLK.

nINTSEL = 1 REF_CLK In Mode nINT/REFCLKO is an active low interrupt output. The REF_CLK is sourced externally and must be driven on the XTAL1/CLKIN pin.

Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper considerationmust also be given to the LED polarity. Refer to Section 3.8.1.6, "nINTSEL and LED2 Polarity Selection"for additional information on the relation between nINTSEL and the LED2 polarity.


LAN8742A/LAN8742Ai

3.7.4.1 REF_CLK In ModeIn REF_CLK In Mode, the 50 MHz REF_CLK is driven on the XTAL1/CLKIN pin. A 50 MHz source for REF_CLK mustbe available external to the device when using this mode. The clock is driven to both the MAC and PHY as shown inFigure 3-7.

FIGURE 3-7: EXTERNAL 50 MHZ CLOCK SOURCES THE REF_CLK

LAN8742A/LAN8742Ai10/100 PHY

24-VQFNRMII

TXP

TXN

Mag RJ45

RXP

RXN

XTAL1/CLKIN

XTAL2

TXD[1:0]

2

RXD[1:0]

CRS_DV2

RMII

LED[2:1]

2

Interface

MDIOMDCnINT

nRST

TXEN

MAC

Accepts external 50MHz clock

50MHz Reference

Clock

All RMII signals are synchronous to the supplied clock

REF_CLKRXER


LAN8742A/LAN8742Ai

3.7.4.2 REF_CLK Out ModeTo reduce BOM cost, the device includes a feature to generate the RMII REF_CLK signal from a low-cost, 25 MHz fun-damental crystal. This type of crystal is inexpensive in comparison to 3rd overtone crystals that would normally berequired for 50 MHz. The MAC must be capable of operating with an external clock to take advantage of this feature asshown in Figure 3-8.

In order to optimize package size and cost, the REFCLKO pin is multiplexed with the nINT pin. In REF_CLK Out mode,the nINT functionality is disabled to accommodate usage of REFCLKO as a 50 MHz clock to the MAC.

Note: The REF_CLK Out Mode is not part of the RMII Specification. To ensure proper system operation, a timinganalysis of the MAC and LAN8742A/LAN8742Ai must be performed.

Note: In REF_CLK Out Mode, REFCLKO will not output when the device is in Energy Detect Power-Down Modeor General Power-Down Mode.

FIGURE 3-8: SOURCING REF_CLK FROM A 25 MHZ CRYSTAL

LAN8742A/LAN8742Ai10/100 PHY24-VQFN

RMII

TXP

TXN

Mag RJ45

RXP

RXN

25 MHz

XTAL1/CLKIN

XTAL2

LED[2:1]

2

Interface

nRST

TXD[1:0]

2

RXD[1:0]

CRS_DV2

RMII MDIOMDC

TXEN

REFCLKO

MAC

Capable of accepting 50 MHz

clock

Note: nINT not available in this configuration

RXERREF_CLK


LAN8742A/LAN8742Ai

In some system architectures, a 25 MHz clock source is available. The device can be used to generate the REF_CLKto the MAC as shown in Figure 3-9. It is important to note that in this specific example, only a 25 MHz clock can be used(clock cannot be 50 MHz). Similar to the 25 MHz crystal mode, the nINT function is disabled.

FIGURE 3-9: SOURCING REF_CLK FROM EXTERNAL 25 MHZ SOURCE

LAN8742A/LAN8742Ai10/100 PHY

24-VQFNRMII

TXP

TXN

Mag RJ45

RXP

RXN

XTAL1/CLKIN

XTAL2

TXD[1:0]

2

RXD[1:0]

CRS_DV2

RMII

LED[2:1]

2

Interface

MDIOMDC

nRST

TXEN

REFCLKO

MAC

Capable of accepting 50 MHz

clock

RXER

25 MHzClock

REF_CLK

Note: nINT is not available on the REFCLKO/nINT pin in this configuration. nINT can be made optionally available via the LED1 or LED2 pin.


LAN8742A/LAN8742Ai

3.8 Miscellaneous Functions

3.8.1 LEDSTwo LED signals are provided as a convenient means to indicate the transceiver's mode of operation or be used asnINT or nPME signals. The LED1 and LED2 pin functions are configurable via the LED1 Function Select and LED2Function Select bits of the Wakeup Control and Status Register (WUCSR), respectively. When used as an LED indicator,the LED signals are either active high or active low as described in Section 3.8.1.5, "REGOFF and LED1 Polarity Selec-tion" and Section 3.8.1.6, "nINTSEL and LED2 Polarity Selection". For additional information on nINT, refer to Section3.6, "Interrupt Management". For additional information on nPME, refer to Section 3.8.4, "Wake on LAN (WoL)".

When configured in the default Link/Activity mode, the LED1 output is driven active whenever the device detects a validlink, and blinks when CRS is active (high) indicating activity.

When configured in the default Link Speed mode, the LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive when the operating speed is 10 Mbps or during line isolation.

3.8.1.1 LED1/nINT/nPME Usage with Internal Regulator Disabled (REGOFF High)When the LED1/nINT/nPME/REGOFF pin is high during reset, the internal regulator is disabled. After the deassertionof reset, this pin will first function as LED1 (Link Activity). Upon configuration, it can function as nINT or nPME. Figure3-10 illustrates the steps required to program the LED1 pin as nINT or nPME with the internal regulator disabled.

In this configuration, it is possible for an LED to be connected to this pin while it function as nINT or nPME during theWoL state. Since the polarity to turn on the LED is active low, the Link Activity LED will not be lit while waiting for a WoLevent.

Note: When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO.

Note: Refer to Section 3.7.3, "REGOFF: Internal +1.2 V Regulator Configuration" for additional information onthe REGOFF configuration strap.

FIGURE 3-10: LED1/nINT/nPME/REGOFF WITH INTERNAL REGULATOR DISABLED

nRST

LED1/nINT/

WUCSR[14:13]

Link Activity nINT/nPME

00b 01b/10b 00b

Link Activity

nPME/REGOFF


LAN8742A/LAN8742Ai

3.8.1.2 LED1/nINT/nPME Usage with Internal Regulator Enabled (REGOFF Low)When the LED1/nINT/nPME/REGOFF pin is low during reset, the internal regulator is enabled. After the deassertion ofreset, this pin will first function as LED1 (Link Activity). Upon configuration, it can function as nINT or nPME. Figure 3-11 illustrates the steps required to program the LED1 pin as nINT or nPME with the internal regulator enabled.

In this configuration, it is recommended not to connect an LED to this pin. Because this pin is active high, the LED willbe lit while waiting for a WoL event.

3.8.1.3 LED2/nINT/nPME Usage with nINTSEL EnabledWhen the LED2/nINT/nPME/nINTSEL pin is high during reset, the nINT/REFCLKO pin is configured to function as nINT.After the deassertion of reset, this pin will first function as LED2 (Link Speed). Upon configuration, it can function asnPME. It is also possible to configure LED2 as nINT although this would duplicate the function of the nINT/REFCLKOpin. Figure 3-12 illustrates the steps required to program the LED2 pin as nINT or nPME with nINTSEL enabled.

In this configuration, it is possible for an LED be connected to this pin while it functions as nINT or nPME during a WoLstate. Since the polarity to light the LED is active low, the Link Speed LED will not be lit while waiting for a WoL event.

To provide further flexibility, LED2 can be reconfigured as Link Activity by writing 11b to the LED2 Function Select fieldof the Wakeup Control and Status Register (WUCSR). This allows LED2 to function as Link Activity when LED1 cannotbe configured as Link Activity. Link Speed can be easily implemented on the microcontroller using GPIO.


FIGURE 3-11: LED1/nINT/nPME/REGOFF WITH INTERNAL REGULATOR ENABLED

Note: Refer to Section 3.7.4, "nINTSEL: nINT/REFCLKO Configuration" for additional information on the nINT-SEL configuration strap.

FIGURE 3-12: LED2/nINT/nPME WITH nINTSEL ENABLED

nRST

LED1/nINT/

WUCSR[14:13]

Link Activity nINT/nPME

00b 01b/10b

nPME/REGOFF

nRST

LED2/nINT/

WUCSR[12:11]

Link Speed/ nINT/nPME

00b/11b 01b/10b 00b/11b

Link Speed/Link Activity

00b

Link Activity

nPME/nINTSEL


LAN8742A/LAN8742Ai

3.8.1.4 LED2/nINT/nPME Usage with nINTSEL DisabledWhen the LED2/nINT/nPME/nINTSEL pin is low during reset, the nINT/REFCLKO pin is configured to function as REF-CLKO. After the deassertion of reset, this pin will first function as LED2. Upon configuration, it can function as nINT ornPME. Figure 3-13 illustrates the steps required to program the LED2 pin as nINT or nPME with nINTSEL disabled.

In this configuration, it is not recommended to connect an LED to this pin. Because this pin is active high, the LED willbe lit while waiting for a WoL event.

3.8.1.5 REGOFF and LED1 Polarity SelectionThe REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically change polarity basedon the presence of an external pull-up resistor. If the LED1 pin is pulled high to VDD2A by an external pull-up resistorto select a logical high for REGOFF, then the LED1 output will be active low. If the LED1 pin is pulled low by the internalpull-down resistor to select a logical low for REGOFF, the LED1 output will then be an active high output. Figure 3-14details the LED1 polarity for each REGOFF configuration.

FIGURE 3-13: LED2/nINT/nPME WITH nINTSEL DISABLED

FIGURE 3-14: LED1/REGOFF POLARITY CONFIGURATION


nRST

LED2/nINT/

WUCSR[12:11]

Link Speed nINT/nPME

00b 01b/10b

nPME/nINTSEL

LED1/REGOFF

~270

REGOFF = 0 (Regulator ON)LED output = Active High

~270

VDD2A

REGOFF = 1 (Regulator OFF)LED output = Active Low

LED1/REGOFF

10K


LAN8742A/LAN8742Ai

3.8.1.6 nINTSEL and LED2 Polarity SelectionThe nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically change polarity basedon the presence of an external pull-down resistor. If the LED2 pin is pulled high to VDD2A to select a logical high fornINTSEL, then the LED2 output will be active low. If the LED2 pin is pulled low by an external pull-down resistor to selecta logical low for nINTSEL, the LED2 output will then be an active high output. Figure 3-15 details the LED2 polarity foreach nINTSEL configuration.

3.8.2 VARIABLE VOLTAGE I/OThe device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinkingtechnologies. These pins can operate from a low I/O voltage of +1.8 V up to +3.3 V. The applied I/O voltage must main-tain its value with a tolerance of ±10%. Varying the voltage up or down after the transceiver has completed power-onreset can cause errors in the transceiver operation. Refer to Chapter 5, "Operational Characteristics" for additional infor-mation.

3.8.3 POWER-DOWN MODESThere are two device power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. Thesemodes are described in the following subsections.

3.8.3.1 General Power-DownThis power-down mode is controlled via the Power Down bit of the Basic Control Register. In this mode, the entire trans-ceiver (except the management interface) is powered-down and remains in this mode as long as the Power Down bit is“1”. When the Power Down bit is cleared, the transceiver powers up and is automatically reset.

FIGURE 3-15: LED2/nINTSEL POLARITY CONFIGURATION

Note: Refer to Section 3.7.4, "nINTSEL: nINT/REFCLKO Configuration" for additional information on the nINT-SEL configuration strap.

Note: Input signals must not be driven high before power is applied to the device.

Note: In REF_CLK Out Mode, REFCLKO will not output when the device is in General Power-Down Mode.

~270

nINTSEL = 0LED output = Active High

10K

~270

VDD2A

nINTSEL = 1LED output = Active Low

LED2/nINTSEL

LED2/nINTSEL


LAN8742A/LAN8742Ai

3.8.3.2 Energy Detect Power-Down (EDPD)This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,when no energy is present on the line the transceiver is powered down (except for the management interface, theSQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energyfrom 100BASE-TX, 10BASE-T, or Auto-negotiation signals.

In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is powered-downand nothing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and thetransceiver powers-up. The device automatically resets into the state prior to power-down and asserts the nINT interruptif the ENERGYON interrupt is enabled in the Interrupt Mask Register. The first and possibly the second packet to acti-vate ENERGYON may be lost.

When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled.

When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPsin EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover TimeRegister. When enabled, the TX NLP timeinterval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP/Crossover TimeRegister.When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPDRX Single NLP Wake Enable bit of the EDPD NLP/Crossover TimeRegister will enable the device to wake on receptionof a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared, the maximum interval for detecting receptionof two NLPs to wake from EDPD is configurable via the EDPD RX NLP Max Interval Detect Select field of the EDPDNLP/Crossover TimeRegister.

3.8.4 WAKE ON LAN (WOL)The device supports PHY layer WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames. TheWoL detection can be configured to assert the nINT interrupt pin or nPME pin, providing a mechanism for a system insleep mode to return to an operational state when a WoL event occurs. This feature is particularly useful in addressingunnecessary waking of the main SoC in designs where the Ethernet MAC is integrated into the SoC.

Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individuallyenabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable(MPEN), and Wakeup Frame Enable (WUEN) bits of the Wakeup Control and Status Register (WUCSR), respectively.Two methods are provided for indicating a WoL event to an external device: nINT and nPME.

The nINT pin may be used to indicate WoL interrupt events by setting bit 8 (WoL) of the Interrupt Mask Register. Onceenabled, any received packet that matches the condition(s) configured in the Wakeup Control and Status Register(WUCSR) will assert nINT until the interrupt is cleared. When using nINT to indicate a WoL interrupt, the pin may beshared with other non-WoL interrupt events, as configured via the Interrupt Mask Register. While waiting for a WoLevent to occur, it is possible that other interrupts may be triggered. To prevent such conditions, all other interrupts shallbe masked by system software, or the alternative nPME pin may be used. Refer to Section 3.6, "Interrupt Management"for additional nINT information.

Alternatively, the nPME pin may be used to independently indicate WoL interrupt events. The nPME signal can be con-figured to output on any of the following pins:

• LED1/nINT/nPME/nREGOFF• LED2/nINT/nPME/nINTSEL

The LED1/nINT/nPME/nREGOFF or LED2/nINT/nPME/nINTSEL pin can be configured to function as nPME by config-uring the LED1 Function Select or LED2 Function Select bits of the Wakeup Control and Status Register (WUCSR) to10b, respectively.Once the nPME pin is enabled, any received packet that matches the condition(s) configured in theWakeup Control and Status Register (WUCSR) will assert nPME until WUCSR bits 7:4 are cleared by the system soft-ware. However, in some applications it may be desirable for nPME to self clear. When the nPME Self Clear bit of theWakeup Control and Status Register (WUCSR) is set, the nPME pin will clear after the time configured in the Miscella-neous Configuration Register (MCFGR).

Upon a WoL event, further resolution on the source of the event can be obtained by examining the Perfect DA FrameReceived (PFDA_FR), Broadcast Frame Received (BCAST_FR), Magic Packet Received (MPR), and Remote WakeupFrame Received (WUFR) status bits in the Wakeup Control and Status Register (WUCSR).

Note: In REF_CLK Out Mode, REFCLKO will not output when the device is in Energy Detect Power-Down Mode.


LAN8742A/LAN8742Ai

The Wakeup Control and Status Register (WUCSR) also provides a WoL Configured bit, which may be set by softwareafter all WoL registers are configured. Because all WoL related registers are not affected by software resets, softwarecan poll the WoL Configured bit to ensure all WoL registers are fully configured. This allows the software to skip repro-gramming of the WoL registers after reboot due to a WoL event.

The following subsections detail each type of WoL event. For additional information on the main system interrupts, referto Section 3.6, "Interrupt Management".

3.8.4.1 Perfect DA (Destination Address) DetectionWhen enabled, the Perfect DA detection mode allows the triggering of the nINT or nPME pin when a frame with thedestination address matching the address stored in the MAC Receive Address A Register (RX_ADDRA), MAC ReceiveAddress B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC) is received. The frame mustalso pass the FCS and packet length check.

As an example, the Host system must perform the following steps to enable the device to assert nINT on detection of aPerfect DA WoL event:

1. Set the desired MAC addres

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto … · 2015. 9. 7. · grated Wake on...

Documents

Transcript of Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto … · 2015. 9. 7. · grated Wake on...