Sleepy Keeper : a New Approach to Low-Leakage...

©© Vincent J. Mooney III, 2006Vincent J. Mooney III, 2006

Sleepy Keeper : a NewApproach to Low-Leakage Power VLSI Design

Se Hun Kim and Vincent J. Mooney III

Center for Research on Embedded Systems and TechnologySchool of Electrical and Computer Engineering

Georgia Institute of Technology, Atlanta, Georgia, U.S.A

October 2006


Outline

IntroductionRelated workSleepy KeeperExperimental MethodologyExperimental ResultsConclusion


Background

Technology Trend High density Transistor size scaling downHigh performance Vth scaling down

Increase of leakage powerIncrease of portable device (e.g., Cell phone, PDA)

Power Consumption = Dynamic + StaticStatic Power Consumption (Leakage Power) became a significant issue


Leakage Power

Gate-oxide leakageGate tunneling due to thin oxide

Subthreshold leakage Scaling down of Vth

Short-channel effectOur research focus

n+ n+

DrainSource

Gate

P-substrate

NFETSubthresholdLeakage current

Gate-oxideLeakage current


Outline

IntroductionPrevious workSleepy KeeperExperimental Methodology.Experimental ResultsConclusion


Previous Work

SleepZigZagStackSleepy-StackLeakage Feedback


Approaches : Sleep

Source gatingState destructive

Floating outputAdditional routingDual Vth applicable

S’

PullupNetwork

A

PulldownNetwork

B

S W/L=4

W/L=2

Low Vth High Vth


Approaches : Zigzag

Favored input vectorReduced wake-up overhead than sleep approach

State destructiveDual Vth

applicable

S’

PullupNetwork

A

PulldownNetwork

B

S’

PullupNetwork

A

PulldownNetwork

B

PullupNetwork

A

PulldownNetwork

B

S


Approaches : Stack

Duplicated transistorsInduce reverse bias in cutoffState-SavingDelay penaltygreater gate capacitance

greater resistance

PullupNetwork

A

PulldownNetwork

BW/L=2W/L=1

W/L=1

W/L=4W/L=2

W/L=2


Approaches : Sleepy-Stack

Combination of Sleep and StackSource gating, Stack effect

State-savingUltra-low leakageArea penalty

PullupNetwork

A

PulldownNetwork

BW/L=2

W/L=1

W/L=1

W/L=4 W/L=2

W/L=2

W/L=1

W/L=2


Approaches : Leakage Feedback

Based on Sleep approachState-savingLeakage in inverterArea penalty

S’

PullupNetwork

A

PulldownNetwork

B

S

Out


Outline

IntroductionPrevious workSleepy KeeperExperimental MethodologyExperimental ResultsConclusion


Motivation of Sleepy Keeper

Ultra low leakage with dual Vth

State-savingLess area penalty and faster than sleepy stack approach


Sleepy Keeper Structure

Add sleep transistorsAdd two transistors driven by outputNMOS to Pull-up Network, PMOS to Pull-down Network

W/L=1.5

W/L=3

Conventional CMOS inverter Sleepy keeper inverter

Keeper transistors


Sleepy Keeper Operation

Active mode Sleep mode

During active mode, sleep transistors are on reducing delay

During sleep mode, sleep transistors are offsaving state

Can apply dual Vth

Low Vth

High Vth


Sleepy Keeper Operation

AssumptionsSmall delay between active mode and sleep mode

Keeper transistorskeeper transistors are not for switching

lower voltage can be applied to maintain state


Outline



Experimental Methodology

Seven techniques are comparedbase case, forced stack, sleep, zigzag,sleepy stack, leakage feedback, and sleepy keeper

Dual-Vth applied for sleep, zigzag, sleepy stack, leakage feedback, and sleepy keeper

Dual-Vth applied (0.2V and 0.4V)


Experimental Methodology

Worst-case propagation delay, static power and dynamic power for each approach measuredArea estimated by scaling down 0.18um layout

Layouts Schematics

HSPICE simulation

Power, Delay estimation

Areaestimation

TSMC 0.18umBPTM** 0.18, 0.13,

0.10, 0.07 um

NCSU CDK*TSMC 0.18um

**Berkeley Predictive Technology Model (BPTM)[Online]. Available http://www.eas.asu.edu/~ptm.

*NC State University Cadence Design Kit[Online]. Available http://www.cadence.ncsu.edu.


Experimental MethodologyPower, delay estimation

Area estimationScaled by ratio of squares & 10% overhead for nonlinear scaling layersEx) 100um^2 in TSMC 0.18um

For 0.10um => 100 * (0.10^2/0.18^2) * 1.1

SchematicTemplate

for experiment automation

Netlist Input vectors HSPICE


Test circuit (4-bit adder chain)

1-bit adderCout = AB + Cin(A+B)Sum = ABCin+(A+B+Cin)Cout’

4-bit adder chain

A B

Cin Cout’ Cout’

Cin

A B

Sum’

Cin Cout

Sum

BA

A1 B1

Cin Cout

Sum1

A2 B2

Cin Cout

Sum2

A3 B3

Cin Cout

Sum3

A0 B0

Cin Cout

Sum0


1-bit adder schematic


Outline



3.00E-10

5.00E-10

7.00E-10

9.00E-10

1.10E-09

1.30E-09

1.50E-09

1.70E-09

Base cas

e

Stack

Sleep

ZigZagSleep

y Stack

Sleepy K

eeper

Sleep*

ZigZag*

Sleepy Stack

*Sleepy

Kee

per*

4-bit adder results – Propagation Delay

8.30E-10Sleepy Keeper*

1.24E-09Sleepy Stack*

7.43E-10ZigZag*

7.52E-10Sleep*

5.90E-10Sleepy Keeper

8.64E-10Sleepy Stack

5.25E-10ZigZag

5.38E-10Sleep

1.16E-09Stack

3.76E-10Base case

0.07µ

Compared mainly to sleepy stack (best prior leakage control technique

while state saving)

Sleepy keeper results 46% less delay than sleepy stack (49% less when dual Vth)

Reason : Less number of transistors than sleepy stack


1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

Base c

ase

Stack

Sleep

ZigZag

Sleepy Stac

kSleep

y Kee

per

Sleep*

ZigZag*

Sleepy Stac

k*Sleep

y Kee

per*

4-bit adder results – Static Power

Compared to stack, sleepy keeper reduce leakage power 175X

Sleepy keeper results 20% more static power than sleepy stack (11%

more when dual Vth)



2.19E-11ZigZag*

3.65E-11Sleep*



9.09E-09ZigZag

1.36E-08Sleep

6.83E-09Stack

8.90E-08Base case

0.07µ


4-bit adder results – Dynamic Power

Compared to sleepy stack, sleepy keeper results 31% more dynamic

power (41% more when dual Vth)

Conjecture : more short circuit current



8.46E-06ZigZag*

9.03E-06Sleep*



8.37E-06ZigZag

8.77E-06Sleep

7.41E-06Stack

8.63E-06Base case

0.07µ

1.00E-06

1.00E-05

1.00E-04

1.00E-03

Base c

ase

Stack

Sleep

ZigZag

Sleepy Stac

kSleep

y Kee

per

Sleep*

ZigZag*

Sleepy Stac

k*Sleep

y Kee

per*


10

100

1000

10000

Base c

ase

Stack

Sleep

ZigZag

Sleepy Stac

kSleep

y Kee

per

Sleep*

ZigZag*

Sleepy Stac

k*Sleep

y Kee

per*

4-bit adder results – Area

93% larger than base case, 49% smaller than sleepy stack

Reason : Sleep transistors, additional 2 transistors, and unusual placement of keeper transistor

177.11Sleepy Keeper

263.52Sleepy Stack

110.48ZigZag

123.76Sleep

123.76Stack

91.84Base case

0.07µ


Conclusion

Ultra low static power with dual Vth

State savingLess area, less delay than sleepy stackDynamic power increased

Sleepy Keeper : a New Approach to Low-Leakage...

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