SLAAC SLD Update Steve Crago USC/ISI September 14, 1999 DARPA.

SLAAC SLD Update

Steve Crago

USC/ISI

September 14, 1999

DARPADARPA

Steve CragoUSC INFORMATION SCIENCES INSTITUTE

Second-Level Detection

Detection

Indexer(SLD)

Focus ofAttention

ESARImage

LPMMSE CRM

Identification

Belief Management(Fusion Executive)

MPM

Joint STARSAdvance Workstation

(JAWS)ATR Results Display

PGA

Second-Level Detection

SAR Image

T72

Annotated SAR Image

T72*Not Joint STARS imagery

Goal200x performance

improvement over old custom hardware


Interface

Input Chips (regions of interest, 8-bit pixels) Bright and Surround Templates (expected SAR

reflection and absorption, 1-bit pixels) Output

Hypothetical target matches


Chip

*Not Joint STARS imagery

64 p

ixel

s

48 pixels

Template

Search Space32 pixels

15 pixels

Chip

SLD Search Space


Computation

SM(i, j) = B(u,v)M(i+u, j+v),

8-bit additions

TH(i,j) = SM(i,j)/BC - Bias

BS(i, j) =B(u,v)[M(i+u, j+v)<TH(i,j)]

8-bit comparisons1-bit additions

SS(i, j) =S(u,v)[M(i+u, j+v)<TH(i,j)]

8-bit comparisons1-bit additions

P1ShapeSum

P2Threshold

P3Bright Sum

P4Surround Sum

Q(i, j) = [BS(i, j) + SS(i, j)]*100

50 50

P5Hit

Quality

Calculate average intensity of chip pixels at positions expected to reflect signal

For each position in the search space:

Count number of pixels that exceed average intensity under “on” bright template pixels

Counter number of pixels that are less than average intensity under “on” surround template pixels

Check hit conditions, calculate hit quality, and return 2 highest hit quality scores


ACS Implementation

Compute independent search space pixels in parallel (15 - 200 computational elements per FPGA)

Template Memory

Packed 8-bit pixels

Packed bits

Host

Highest Quality Hits(Chip, Template IDs,location)Chip Pixels

Adaptive Computing Element


I/O Requirements

Each eight-bit chip pixel used for 550 operations per match task

Each FIFO element contains 8 chip pixels Each FIFO elements contains enough operands for

3600 operations

I/O will not be a bottleneck any time soon!


Memory Requirements

Template pixels are only 1 bit (each memory access provides 18 operands)

Computation uses one template bit per cycle Pixels are broadcast to all compute elements that

are working on a single match task Multiple ports for parallel match tasks reduce logic

complexity

Memory bandwidth will not be a bottleneck any time soon, but ports are helpful!


Virtex Features

Chip pixel alignment pipeline BlockSelectRAM+ can replace logic cells Could buy some speed

Template-specific reconfiguration Potential speedup due to sparseness of templates Clear win not yet clear


Performance Projections

Platform Template-Matches/Second(one board)

One 4062 1,300

Wildforce (4062-based) 5,200

SLAAC-2 (40150-based) 15,600

SLAAC-2V (XCV100-based) 104,000


Schedule

Single-chip implementation working Full Wildforce implementation: 9/99 SLAAC-2 implementation: 9/99? Virtex implementation: ???

Remap to use additional logic should be easy Utilization of BlockSelectRAM+ will take a little more

time, but straightforward

SLAAC SLD Update Steve Crago USC/ISI September 14, 1999 DARPA.

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