SISTEMI EMBEDDED - unipi.it
11
SISTEMI EMBEDDED Course Presentation – Spring 2018 Federico Baronti Dip. Ing. Informazione Via G. Caruso, 16 – Stanza B-1-09 050 2217581 – [email protected] http://www.iet.unipi.it/f.baronti/ Office hours: Friday 15-18. Please, contact me in advance before showing up.
Transcript of SISTEMI EMBEDDED - unipi.it
SISTEMI EMBEDDED
Course Presentation ndash Spring 2018
Federico BarontiDip Ing Informazione
Via G Caruso 16 ndash Stanza B-1-09
050 2217581 ndash federicobarontiunipiit
httpwwwietunipiitfbaronti
Office hoursFriday 15-18 Please contact me in advance before showing up
2M ElettronicaLu Ma Me Gi Ve Sa
830930
9301030 NanoelettronicaC33
NanoelettronicaC22
10301130 NanoelettronicaC33
NanoelettronicaC22
11301230 NanoelettronicaC33
Sistemi embeddedB24
Sistemi di elaborazioneSI 7
12301330 Sistemi embeddedB24
Sistemi di elaborazioneSI 7
13301430 Sistemi di elaborazioneADI1
Sistemi di elaborazioneSI 7
14301530 Sistemi di elaborazioneADI1
NanoelettronicaC41
15301630 Sistemi embeddedADI3 ex B26
NanoelettronicaC41
Sistemi embeddedADI3 ex B26
16301730 Sistemi embeddedADI3 ex B26
NanoelettronicaC41
Sistemi embeddedADI3 ex B26
17301830 Sistemi embeddedADI3 ex B26
Sistemi embeddedADI3 ex B26
wwwlantivcom
Class Schedule
F Baronti - Sistemi Embedded - University of Pisa 2
Optional Lab
Course Objectives
Learn expertise and methodologies to design and program an embedded system
Wersquoll use as a reference a System on Programmable Chip (SoPC) platform based on an Intel (formerly Altera) FPGA
F Baronti - Sistemi Embedded - University of Pisa 3
Course Organization
F Baronti - Sistemi Embedded - University of Pisa 4
GroupProject
ComputerOrganisation
EmbeddedC
Programming
ToolsCompiler
LinkerJTAG debugger
Nios II procamp System
Interconnect Fabric
Performance Metrics
Constraints
Course Requirements
bull Digital Electronicsbull Digital Logic Designndash HDL Coding
bull Software Programmingndash Basic knowledge of C or C++ Language
F Baronti - Sistemi Embedded - University of Pisa 5
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
2M ElettronicaLu Ma Me Gi Ve Sa
830930
9301030 NanoelettronicaC33
NanoelettronicaC22
10301130 NanoelettronicaC33
NanoelettronicaC22
11301230 NanoelettronicaC33
Sistemi embeddedB24
Sistemi di elaborazioneSI 7
12301330 Sistemi embeddedB24
Sistemi di elaborazioneSI 7
13301430 Sistemi di elaborazioneADI1
Sistemi di elaborazioneSI 7
14301530 Sistemi di elaborazioneADI1
NanoelettronicaC41
15301630 Sistemi embeddedADI3 ex B26
NanoelettronicaC41
Sistemi embeddedADI3 ex B26
16301730 Sistemi embeddedADI3 ex B26
NanoelettronicaC41
Sistemi embeddedADI3 ex B26
17301830 Sistemi embeddedADI3 ex B26
Sistemi embeddedADI3 ex B26
wwwlantivcom
Class Schedule
F Baronti - Sistemi Embedded - University of Pisa 2
Optional Lab
Course Objectives
Learn expertise and methodologies to design and program an embedded system
Wersquoll use as a reference a System on Programmable Chip (SoPC) platform based on an Intel (formerly Altera) FPGA
F Baronti - Sistemi Embedded - University of Pisa 3
Course Organization
F Baronti - Sistemi Embedded - University of Pisa 4
GroupProject
ComputerOrganisation
EmbeddedC
Programming
ToolsCompiler
LinkerJTAG debugger
Nios II procamp System
Interconnect Fabric
Performance Metrics
Constraints
Course Requirements
bull Digital Electronicsbull Digital Logic Designndash HDL Coding
bull Software Programmingndash Basic knowledge of C or C++ Language
F Baronti - Sistemi Embedded - University of Pisa 5
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Objectives
Learn expertise and methodologies to design and program an embedded system
Wersquoll use as a reference a System on Programmable Chip (SoPC) platform based on an Intel (formerly Altera) FPGA
F Baronti - Sistemi Embedded - University of Pisa 3
Course Organization
F Baronti - Sistemi Embedded - University of Pisa 4
GroupProject
ComputerOrganisation
EmbeddedC
Programming
ToolsCompiler
LinkerJTAG debugger
Nios II procamp System
Interconnect Fabric
Performance Metrics
Constraints
Course Requirements
bull Digital Electronicsbull Digital Logic Designndash HDL Coding
bull Software Programmingndash Basic knowledge of C or C++ Language
F Baronti - Sistemi Embedded - University of Pisa 5
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Organization
F Baronti - Sistemi Embedded - University of Pisa 4
GroupProject
ComputerOrganisation
EmbeddedC
Programming
ToolsCompiler
LinkerJTAG debugger
Nios II procamp System
Interconnect Fabric
Performance Metrics
Constraints
Course Requirements
bull Digital Electronicsbull Digital Logic Designndash HDL Coding
bull Software Programmingndash Basic knowledge of C or C++ Language
F Baronti - Sistemi Embedded - University of Pisa 5
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Requirements
bull Digital Electronicsbull Digital Logic Designndash HDL Coding
bull Software Programmingndash Basic knowledge of C or C++ Language
F Baronti - Sistemi Embedded - University of Pisa 5
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Group Project
bull Design an SoPC on an Intel Max 10 FPGA hosted on the Terasic DE10-Lite boardndash Computer implementationbull May require the design of one or more custom
peripheralsndash Software programming
bull Project assignment during the 5th weekbull See Projects of previous years to gather an
idea
F Baronti - Sistemi Embedded - University of Pisa 6
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Material (1)
bull Available at the course web page httphttpwwwietunipiitfbarontididatticaSE2018Sistemi Embeddedhtml
bull Slides used during lecturesbull Project templatesexamplesbull Text bookndash C Hamacher Z Vranesic S Zaky N Manjikian
Computer Organization and Embedded Systemsrdquo McGraw-Hill International Edition
bull Documentation from Intel FPGA (Altera)
F Baronti - Sistemi Embedded - University of Pisa 7
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Material (2)
bull Quartus Prime Lite Edition (161 update 2)with Max 10 Device Support
bull University Program Installer (161)
bull Nios II Documentation
F Baronti - Sistemi Embedded - University of Pisa 8
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
DE10-Lite
User Manual
4
wwwterasiccom January 24 2017
The DE10-Lite package includes
x The DE10-Lite board x Type A Male to Type B Male USB Cable
11 22 DDEE1100--LLiittee SSyysstteemm CCDD
The DE10-Lite System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets
User can download this System CD from the web (httpDE10-Liteterasiccomcd)
11 33 LLaayyoouutt aanndd CCoommppoonneennttss
This section presents the features and design characteristics of the board
A photograph of the board is shown in Figure 1-2 and Figure 1-3 It depicts the layout of the board and indicates the location of the connectors and key components
Figure 1-2 Development Board (top view)
Course Material (3)bull 14x DE10-Lite Development amp Education boardndash Intel Max 10 10M50DAF484C7G (50k LE 1638 Kb in M9K blocks)
F Baronti - Sistemi Embedded - University of Pisa 9
NEW
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Course Material (4)bull 2x Touch display (LT24) 6x 8M Pixel Camera
(D8M-GPIO) Multi-touch LCD Module Second Edition (MTL2) Servo Motor Kit (SVK)
F Baronti - Sistemi Embedded - University of Pisa 10
MLT2 User Manual 27 wwwterasiccom
April 12 2016
Figure 5-2 displays the five-finger painting of the canvas area
Figure 5-2 Five-finger Painting
5522 SSyysstteemm DDeessccrriippttiioonn
For LCD display processing the reference design is developed based on Alterarsquos Video and Image Processing Suite (VIP) The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input
For multi-touch processing a Terasic Memory-Mapped IP is used to retrieve the user input including multi-touch gestures and single-touch coordinates For IP--usage details please refer to the Chapter Three in this document Note the IP is encrypted so the license should be installed before compiling the Quartus II project
Figure 5-3 shows the system generic block diagram of demonstration reference design
NEWMTL2
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
Exam Evaluation
bull Project Evaluation (~40 ) the same marking
for all the group members
ndash Presentation and Demo (~30 ) - Due on last class
ndash Project report (~70 ) ndash Due a ldquoweekrdquo before the
selected exam date
bull Oral Test (~60 )
ndash Project discussion (~50 )
ndash Assessment of understanding and mastering the
course contents (~50 )
F Baronti - Sistemi Embedded - University of Pisa 11
