Sinusoidal Pulse Width Modulation Design Based DDS

Gao Shuangxi, Cao Shufu College of Information & Technology,

Hebei University of Economics & Business, Hebei Shijiazhuang, China.

Email: gaosx@126.com Email:caoshufu@heuet.edu.cn

Zhang Ying Department of Electronic and Communication Engineering

North China Electric Power University Hebei Baoding，China china.zy.love@163.com

Abstract—FPGA chip using Cyclone series designed and implemented a new type of sinusoidal pulse width modulation (SPWM) generator. The generator used direct digital synthesis (DDS) technology with DSP Builder (FPGA chip supported the corresponding algorithm sub-circuits) discreteness as the hardware middle layer, produced triangle and sine modulated carrier wave which can be controlled in frequency, phase, amplitude. After comparator comparison, the output state was automatic overturn at the time of the waveform intersection, brought SPWM w aveform to achieve the control of corresponding switching devices on-off. This method avoided compiling complex hardware program, at the same time ensured the scalability of the system, improved the development efficiency and met the requirements of embedded system, but also has on-site programmability. The simulation results show that the SPWM waveform can neatly achieve the adjustment about frequency, phase, amplitude, and have high frequency resolution.

Keywords- DDS; SPWM; DSP Builder

I. INTRODUCTION In recent years, with the development of microprocessor

and its peripheral circuits, some of the problems existing in digital control technology have been greatly improved, and gradually replace the analog control technology to achieve the traditional control functions. PWM technology is a very important part of the power electronic technologies. It has huge function to enhance the performance of power electronic devices and promote the development of power electronic technologies.

Sinusoidal pulse width modulation SPWM (Sinusoidal Pulse Width Modulation) changes pulse modulation mode based on PWM, the pulse width time duty ratio arranges according to the sine rule, so that the output waveform can be exported sine wave through proper filtering. Traditional SPWM mainly be composed by the analog circuits, respectively bring triangular wave and sine wave by discrete devices, and then synthesize to get the SPWM waveform by comparator, thus SPWM obtains a higher accuracy. The disadvantage is lack control flexibility, does not easy to compose closed-loop control system with the microcomputer system[1]. With the continuous development of digital communications technologies and the integrated circuits, direct

digital synthesis (DDS) and programmable logic gate array (FPGA) have been widely used. DDS as a new type of frequency synthesizer technology has many characteristics such as high frequency resolution, fast frequency conversion speed, and the output phase-continuous when the frequency changes, and easy to implement a variety of modulation functions and so on [2]. This paper presents a design project of realization SPWM waveform based on DSP Builder, which greatly improve the quality of SPWM output waveform. It has high flexibility and controllability.

II. DDS BASIC PRINCIPLE DDS is a digital frequency synthesizer[3]. It is a digital

technology synthesis method, by controlling the phase change rate direct produce frequency that has a variety of different frequency and amplitude signals. DDS has a higher frequency resolution, can fast realize frequency switching and maintain a continuous phase when frequency changes. It is easy to realize numerically controlled modulation of frequency, phase and amplitude.

DDS system is mainly composed by the phase accumulator, sine ROM look-up table, D/A converters and so on[4]. DDS block diagram is shown in Fig. 1.

Figure 1. DDS block diagram

In the figure, the phase accumulator accumulates phase increment M which is determined by the frequency control word one time when each clock cycle comes. If the count is

Tuning word

Clock f0

Phase accumulator

ROM

DAC

LPF

f out

978-1-4244-5874-5/10/$26.00 ©2010 IEEE

greater than 2N, then automatic overflow and only keep the N-bit digital of the back in the accumulator. Sine look-up table ROM is used to implement the conversion from the phase value output by phase accumulator to the sine amplitude value, make the digital of the sine amplitude value convert into analog in the ADC, finally pass the filter and export a very pure sine wave output signal.

After given DDS clock frequency, the output signal frequency depends on the frequency control word, the frequency resolution depends on the accumulator bits, the phase resolution depends on the ROM address line digit, the amplitude quantization noise depends on the ROM data-bit word length and D/A converter digit.

III. SPWM MODULATION PRINCIPLE SPWM waveform is a series of constant amplitude and

different width rectangular pulse waveform equivalent to sine wave[5]. Its principle is: the sine wave is divided into n equal portions, and then the sine-curve of each equal portions and the horizontal axis close in areas, which are replaced by a rectangular pulse having equivalent areas. In which the amplitude of rectangular pulse is constant, the midpoint of each pulse overlaps the midpoint of each equal portion. In this way, the waveform consisting of n constant amplitude and different width rectangular pulse is equivalent sine wave, which calls SPWM waveform.

A. SPWM BasicPrinciple of theModulation In SPWM, sine wave is often as a modulated signal, the

isosceles triangle wave is often as the carrier, generates modulated wave through the modulation. As shown in Fig. 2.

Figure 2. Bipolar SPWM waveform

On the assumption that equivalent sine wave is UmSinωt, SPWM pulse sequences wave amplitude is Us/2, the pulse width is different width, but has the same center distance π/n, n is the number of pulses of the half cycle sine wave, so that if the ith rectangular pulse width is δi, its phase angle of the focal points is θi, then the equivalent principle according to the area theory has:

( ) ( )∫+

−=

n

nmsii

i

ttdUU2

2sin2

πθ

πθωωδ

= ( ) ⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ +−−

nU inim 2

coscos 2πθθ π

= im nU θπ sin

2sin2 （1）

When n is larger nn 22

sin ππ ≈ , there has:

i

s

mi nU

U θπδ sin2= （2）

That is, the width of the ith is approximately proportional to the sine wave value.

B. SPWM Modulation Based on DDS In SPWM, sample to a pure single-frequency signal

)2sin()(sin)( 0tftts πθ ==

the sampling cycle is Tc, then discrete waveform sequence can be gotten:

)2sin()( 0 cnTfnu π= )2,1,0( =n （3） The corresponding of discrete phase sequence is:

nnTfn c •Δ== θπθ 02)( )2,1,0( =n （4）

In formula: cc ffTf 00 22 ππθ ==Δ is the phase increment between two successive sampling. According to sampling theorem the following conclusions can be gotten.

cff21

0 < （5）

The discrete sequence can be gotten:

• From (3) can be unique recovered the original analog signal;

• The slope of the phase function decides the frequency of the signals, but the phase increment θΔ decides the slope of the phase function.

Therefore, if controlling the phase increment, then the frequency of the synthesis signal can be controlled. Now the phase π2 of the whole cycle is divided into M equal parts, for K-times of the δ ，then the frequency of the signal can be obtained:

ff cc M

KT

K ==π

δ20

（6）

The corresponding analog signal is:

)2sin()( tMKtu f c

π= （7）

In the formula, K and M are positive integers, according to the requirement of the sampling theorem, the maximum value of K should be less than the half of the M.

In summary, at the circumstances of the sampling frequency is certain, by controlling the phase increment between the two samples (not greater than π) control the

obtained frequency of discrete sequence, the analog signal of the frequency can be only recovered after keeping and filtering.

IV. SPWM IMPLEMENTATION BASED ON DDS

A. Verification system design In order to verify the SPWM generator that is proposed in

the paper, design a small control system based on power electronics.

The system uses EP1C12Q240C8 series of Cyclone offered by Altera company. The chip offers 173 I/O interfaces, has 12060 LES, 52 RAM Block of 4 KB, the total available 239616Bit RAM, in addition chip also has two phase-locked loop, this can ensure the system clock signals stability when the system high-speed operation. Memory module use 256K × 32Bit SRAM and 2M × 8Bit FLASH ROM, in which SRAM is mainly to store the executable code and variables using in the program when develop SOPC, while the FLASH is used to solidify the debugged SOPC code, etc. The system overall structure is shown in Fig. 3.

Figure 3. Thepower electronic control system basic structure

As the last figure shown, the main circuit of input power uses the inverter circuit, switching device uses IGBT with a 2.5-5v threshold voltage, due to a very small input capacitance, fast switching speed and high frequency. The output circuit is low-pass filter.

Driver circuit realizes isolation and protection, protection measures of IGBT include voltage and dv/dt suppression, over-current protection, over temperature protection. The feedback circuit make system form the closed-loop structure, so that improve the control accuracy.

B. User-defined SPWM module design SPWM modules use the DSP Builder interface tool which

is between Quartus � and Matlab/ Simulink to design. Using direct digital frequency synthesis (DDS) technology, produce stability frequency triangular carrier and modulated sine wave, which are compared by high-speed analog comparator. Its output state automatically turns at the time of the waveform intersection point, consequently control the corresponding switches device on-off, completely avoid real-time computing.

First of all, call DSPBuilder and the other graphical blocks in Simulink libraries using graphical mode in Simulink environment of Matlab, constitute a system-level or algorithm-level design block diagram, that is, Simulink design model,

then complete VHDL conversion, integration and adaptation using the DSP Builder, finally integrate the generated VHDL, SPWM module shown in Fig.4.

Figure 4. SPWM model in the DSP builder Lane

In Fig.4, AW is amplitude control word, FW is frequency control word, TF is triangular wave frequency, CLK is reference clock, PR is phase register, ROM is sine look-up table, AV is absolute value, AG is amplitude gain, C is comparator, and TC is triangular carrier.

Under the control of the reference clock, frequency control word accumulate by the accumulator, in order to obtain the corresponding phase data, the phase modulator receive the phase output of the phase accumulator, mainly is used for signal phase modulation, the output data as sample address to addressable sine ROM lookup table, accomplish the counterchange of phase to amplitude, output different amplitude encoding, progress the amplitude gain through the amplitude control word, generate adjustable frequency-domain amplitude digital sine wave and triangular wave, moreover to produce the needed SPWM wave.

C. parameter selection In order to facilitate system validation selectes as follows:

• The word length D of ROM data bit and D/A converter is 10.

• The word length of phase accumulator N is 10.

• The system reference clock fc which generate by phase-locked loop is 50MHz.

• The storage format of addressable memory is 1024 × 10Bit. The phase control is 10240 ≤≤ P .

• The phase step is. 10242N

By the DDS theory the output frequency resolution can be gotten as follows:

kHzf

ff Nc 9.48

2min0 ===Δ,

And the maximum frequency is:

MHz

ff c 25

2max0 ==.

PWM module CPU

Power circuit Lower-pass filter

Drive circuit Feedback circuit

Display module

FW

CLK

TF

AW

PR

PR

ROM

AV

AG

AG

C

SPWM

TC

V. SIMULATION VERIFICATION At first select chip models based on top-level design, lock

the chip pin, then do analysis to result using of timing simulation.

A. Behavioral simulation In the simulink of Matlab, respectively set the triangular

amplitude value is 300. Frequency word is 100 million. Phase word is 0. Sine wave amplitude is 220, Frequency word is 9 million. Phase word is 0. The modulation depth m is 4. Simulation is processed. This simulation results are shown in Fig. 5. The results showed that the frequency can be controlled by the frequency control words, their amplitude can also be controlled by the amplitude control words.

Figure 5. SPWM simulation waveform m = 4

B. RTL functional simulation Link for ModelSim is a co-simulation interface expansion

module. It seamlessly links up the Matlab, FPGA and the ASIC hardware design flows. It provides a fast two-way connection connecting Matlab and Modelsim. Progress the direct co-simulation between these two simulation models, and more efficiently verify the register transfer level (RTL) model in Matlab Modelsim

In the ModelSim simulation environment, simulation is processed to VHDL that was inborn by Signalcompiler. Since the simulation is not related to hardware time sequence, it belongs to functional simulation. This simulation results are shown in Fig. 6.

Figure 6. ModelSim simulation results

VI. CONCLUSION Paper uses FPGA series of Cyclone offered by Altera

company as the master chip. using VHDL hardware description language design PWM generator, UART and liquid crystal display and so on module in the FPGA hardware development. Also use Nios soft core offered by Altera's. Using C language processes program to soft-core CPU. This Not only ensures the scalability of the system, but also improves the development efficiency. Realize SPWM with FPGA has more flexible than the special chip, as long as change the data in the ROM and the control parameters, frequency and phase tuning can be achieved. System has many virtues such as design simple, reliable, easy tuning and so on. The whole design idea is flexible, and intuitive graphical interface is simple and objective, development cycle is short. The simulation results show that the design principles are correct and effective.

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[3] Chen Xiaozheng, “Design and Realization of Virtual Frequency Scanner Based on DDS Technology”, Communication & Audio and Video, No. 1 2006, pp. 40~46

[4] LiYong1, Ai Zhujun1 and Liu Qiaoyun etc. “A design for DDS based on FPGA”, Cryo.& Supercond, Vo.l 35 No. 6, 2007, pp.539~542

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