SINGLE HIP UAL PROSLIC WITH INTEGRATED SERIAL … · Rev. 1.2 5 1. Electrical Specifications Table...

Rev. 1.2 2/13 Copyright © 2013 by Silicon Laboratories Si32266/7/8/9

Si32266/7/8/9

SINGLE-CHIP DUAL PROSLIC® WITH INTEGRATED SERIAL INTERFACE ( ISI)Features

Applications

Description

The Si32266/7/8/9 Dual ProSLIC® devices, in a single package, implement two completeforeign exchange station (FXS) telephony interfaces. The Si32266/7/8/9 devices operatefrom a 3.3 V supply and use Silicon Labs' proprietary three-wire digital Integrated SerialInterface (ISI). Built-in dc-dc converter controllers can be used to automatically generate theoptimal battery voltage required for each line-state, optimizing efficiency and minimizingheat generation. The Si32266/7 devices are designed to operate with a tracking batterysupply for each channel for lowest power consumption. The Si32268/9 devices use sharedbattery supplies for lowest cost, with an internal dc-dc controller that operates in TrackingShared Supply (TSS) mode to deliver power consumption lower than typical fixed voltageshared rail designs. Self-testing and metallic loop testing (MLT) (e.g., GR-909) is facilitatedby the built-in DSP, monitor ADC, and test load. The devices are available with linefeedvoltage ratings of –110 V (Si32266/8) or –140 V (Si32267/9) to support high voltage ringing,and both devices support wideband audio for better-than-PSTN voice quality. All Si32266/7/8/9 devices are available in a 6 x 8 mm 50-pin QFN package.

Functional Block Diagram

Two complete FXS channels in 6 x 8 mm 3-wire ISI combines PCM, SPI, and interrupt Performs all BORSCHT functions Ideal for short- or long-loop applications Ultra low power consumption Internal balanced or unbalanced ringing Patented low power ringing Adaptive ringing Simplified configuration and diagnostics

Supported by ProSLIC APIGR-909 loop diagnosticsAudio diagnostics with loopbackIntegrated test load

Wideband voice support On-hook transmission Loop or ground start operation Smooth polarity reversal Pulse metering

Software-programmable parameters:Ringing frequency, amplitude,

cadence, and waveshapeTwo-wire ac impedanceTranshybrid balanceDC current loop feed (10–45 mA)Loop closure and ring trip thresholdsGround key detect threshold

Integrated dc-dc controllers with directconnection to MOSFET

Two high voltage supply optionsFull tracking (Si32266/7)Tracking shared supplies

(Si32268/9) DTMF generator/decoder A-Law/µ-Law companding, linear PCM 3.3 V operation Pb-free/RoHS-compliant packaging

VoIP gateways and routers xDSL IADs Optical Network Terminals/Units (ONT/U) Analog Terminal Adapters (ATA)

Cable eMTA Wireless Fixed Terminals (WFT) Wireless Local Loop (WLL) WiMAX CPE

P C M /

In terface

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e

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A D C

D A C

C O D E C S LICLinefeedC ontro l

L inefeedM onitor

D C -D C C ontro ller

L ine D iagnostics

P LLP S C LK

M IS O

M O S I

Inte

gra

ted

Ser

ial

Inte

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ab

le

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A D C

D A C

C O D E C

D C -D C C ontro llers

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P LL

S i32266/7/8 /9

D A CR IN G

TIP

Lin

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ed

C hannel A

C O D E C S LIC

D A CR IN G

TIP

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C hannel B

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A D C

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L ine feedC ontro l

L ine feedM onitor

Patents pending

Ordering Information

See page 42.

Pin Assignments

Si32266/7

Si32268/9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TIPa

N/C

GPIO2A / SRINGCa

GPIO1a / STIPCa

SRINGDCa

SRINGACa

STIPACa

STIPDCa

CAPPa

CAPMa

SVBATa

SVDC

RSTB

PSCLK

MIS

O

MO

SI

SD

CH

a

SD

CLa

DC

DR

Va

DC

FF

a

DC

FF

b

DC

DR

Vb

SD

CLb

SD

CH

b

VDDREG

SVBATb

CAPMb

CAPPb

IREF

STIPDCb

STIPACb

SRINGACb

SRINGDCb

GPIO1b / STIPCb

GPIO2b / SRINGCb

VDDA

N/C

TIPb

VB

AT

b

N/CRIN

Gb

N/C

N/C

N/C

N/C

N/C

VR

EF

_BT

VB

AT

a

RIN

Ga

EPAD 2

15 16 17 18 19

20 21 22 23 24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

4041

42

4344

4546

57

5849 47

48

50

VD

DD

EPAD 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

RINGa

N/C

TIPa

GPIO2a / SRINGCa

GPIO1a / STIPCa

SRINGDCa

STIPACa

STIPDCa

CAPPa

CAPMa

SVBATa

SVDC

RS

TB

PS

CL

K

MIS

O

MO

SI

DC

FF

a

DC

FF

b

DC

DR

Vb

SD

CLb

SD

CH

b

VD

DR

EG

SVBATb

CAPMb

CAPPb

IREF

STIPDCb

STIPACb

SRINGACb

SRINGDCb

GPIO1b / STIPCb

GPIO2b / SRINGCb

VDDA

N/C

TIPb

VB

AT

b

N/C

RIN

Gb

N/C

N/C

N/C

N/C

BA

SE

a

VB

AT

a

BA

SE

b

EPAD 2

15 16 17 18 19 20 21 22 23 24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40414243444546575849 47

48

50

VD

DD

N/C

SRINGACa

N/C

BA

T_

PO

EPAD 1

Si32266/7/8/9

2 Rev. 1.2

Si32266/7/8/9

Rev. 1.2 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1. Si32266/7 Flyback Tracking DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.2. Si32268 TSS DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285. FXS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295.6. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305.7. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305.8. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315.9. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.10. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.11. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.12. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.13. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.14. Pulse Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335.17. In-Circuit and Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6. Integrated Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1. Si32266/7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367.2. Si32268/9 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4410. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

10.1. 50-Pin QFN/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4510.2. 50-Pin QFN/NBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

11. PCB Land Pattern: LGA and NBA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4711.1. Land Pattern and Solder Mask Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4711.2. Thermal Via Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4811.3. Stencil Aperture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5012.1. 50-Pin LGA Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5012.2. 50-Pin LGA Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5012.3. 50-Pin NBA Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Si32266/7/8/9

4 Rev. 1.2

12.4. 50-Pin NBA Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Si32266/7/8/9

Rev. 1.2 5

1. Electrical Specifications

Table 1. Recommended Operating Conditions1

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TAF-grade 0 25 70 °C

G-grade –40 25 85 °C

Silicon Junction Temperature, QFN-50

TJHV Linefeed Die — — 1452 °C

Supply Voltage, Si3226x VDDD, VDDA 3.13 3.3 3.47 V

Battery Voltage, Si32266/83 VBAT –110 — –15 V

Battery Voltage, Si32267/93 VBAT –140 — –15 V

Notes:1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at

nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.2. Except during ringing.3. Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.

Table 2. AC Characteristics(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)

Parameter Test Condition Min Typ Max Unit

TX/RX Performance

Overload Compression 2-Wire – PCM Figure 4 — —

Single Frequency Distortion(0 dBm0 input)

0 Hz to 4 kHz — — –40 dBm05

0 Hz to 12 kHz — — –28 dBm05

Signal-to-(Noise + Distortion) Ratio1 200 Hz to 3.4 kHzD/A or A/D 8-bit

Active off-hook, and OHT, any ZT

Figure 3 — —

Audio Tone Generator Signal-to-Distortion Ratio1

0 dBm0, Active off-hook, and OHT, any ZT

46 — — dB

Intermodulation Distortion — — –41 dB

Gain Accuracy1 2-Wire to PCM or PCM to 2-Wire1014 Hz, any gain setting

–0.2 — 0.2 dB

Attenuation Distortion vs. Frequency 0 dBm05 See Figure 5 and 6

Group Delay vs. Frequency See Figure 7 and 8

Notes:1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking

performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.

3. VDDD, VDDA = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register coefficients.

4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.5. 0 dBm0 is equal to 0 dBm into 600 .

Si32266/7/8/9

6 Rev. 1.2

Gain Tracking2 1014 Hz sine wave, reference level –10 dBm

Signal level:

3 dB to –37 dB — — 0.25 dB

–37 dB to –50 dB — — 0.5 dB

–50 dB to –60 dB — — 1.0 dB

Round-Trip Group Delay 1014 Hz, Within same time-slot — 450 500 µs

2-Wire Return Loss3 200 Hz to 3.4 kHz 26 30 — dB

Transhybrid Balance3 300 Hz to 3.4 kHz 26 30 — dB

Noise Performance

Idle Channel Noise4 C-Message weighted — 8 12 dBrnC

Psophometric weighted — –82 –78 dBmP

PSRR from VDDD, VDDA @ 3.3 V RX and TX, 200 Hz to 3.4 kHz — 55 — dB

Longitudinal Performance

Longitudinal to Metallic/PCM Balance (forward or reverse)

200 Hz to 1 kHz 58 60 — dB

1 kHz to 3.4 kHz 53 58 — dB

Metallic/PCM to Longitudinal Balance

200 Hz to 3.4 kHz 40 — — dB

Longitudinal Impedance 200 Hz to 3.4 kHz at TIP or RING — 50 —

Longitudinal Current Capability Active off-hook 60 Hz Reg 73 = 0x0B

— 25 — mA

Table 2. AC Characteristics (Continued)(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)

Parameter Test Condition Min Typ Max Unit

Notes:1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking

performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.

3. VDDD, VDDA = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register coefficients.

4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.5. 0 dBm0 is equal to 0 dBm into 600 .

Si32266/7/8/9

Rev. 1.2 7

Table 3. Power Supply Characteristics(VDD = 3.3 V, TA = 0 to 70 ºC)


Supply currents: Reset

IDD VT and VR = Hi-Z , RST = 0 — 3.5 — mA

IVBAT — 0 — mA

Supply currents:High Impedance, Open

IDD VT and VR = Hi-Z — 23 — mA

IVBAT — 0.6 — mA

Supply currents:Forward/Reverse, On-hook

IDDVTR = –48 V, Automatic Power Save

Mode enabled — 10 — mA


Supply currents:Forward/Reverse, On-hook

IDDVTR = –48 V, Automatic Power Save

Mode disabled — 35 — mA


Supply currents:Tip/Ring Open, On-hook

IDDVT or VR = –48 V,VR or VT = Hi-Z,

Automatic Power Save Mode enabled

— 10 — mA


Supply currents:Tip/Ring Open, On-hook

IDD

VT or VR = –48 V,VR or VT = Hi-Z,

Automatic Power Save Mode disabled

— 35 — mA


Supply currents:Forward/Reverse OHT, On-hook

IDDVTR =48 V — 53 — mA

IVBAT — 3 — mA

Supply currents:Forward/Reverse Active, Off-hook

IDDILOOP = 26 mA RLOAD = 200 Ω — 54 — mA

IVBAT — 2.2 +

ILOOP — mA

Supply currents:Ringing

IDDVTR =55VRMS + 0 VDC, balanced, FXO disabled

sinusoidal, f = 20 Hz, RLOAD = 5 REN = 1400 Ω

— 40 — mA

IVBAT — 38 — mA

Notes:1. All specifications are for a single channel of Si3226x, and based on measurements with all channels in the same

operating state.2. ILOOP is the dc current in the subscriber loop during the off-hook state.

Si32266/7/8/9

8 Rev. 1.2

Table 4. Linefeed Characteristics(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)


Maximum Loop Resistance RLOOP

RDC,MAX = 430 ILOOP = 18 mA, VBAT = –52 V,

RPROT = 0 — — 2000

DC Feed Current

Differential — — 45 mA

Common Mode — — 30 mA

Differential + Common Mode — — 45 mA

DC Loop Current Accuracy ILIM = 18 mA — — 10 %

DC Open Circuit Voltage Accuracy

Active Mode; VOC = 48 V, VTIP – VRING

— — 4 V

DC Differential OutputResistance

RDO ILOOP < ILIM 160 — 640

DC On-Hook VoltageAccuracy—Ground Start

VOHTOIRING<ILIM; VRING wrt ground,

VRING = –51 V— — 4 V

DC OutputResistance—Ground Start

RROTO IRING<ILIM; RING to ground 160 — 640

DC Output Resistance—Ground Start

RTOTO TIP to ground 400 — — k

Loop Closure DetectThreshold Accuracy

ITHR = 13 mA — — 10 %

Ground Key DetectThreshold Accuracy

ITHR = 13 mA — — 10 %

Ring TripThreshold Accuracy

AC detection,VRING = 70 Vpk, no offset,

ITH = 80 mA— — 4 mA

DC detection,20 V dc offset, ITH = 13 mA

— — 1 mA

DC Detection,48 V DC offset, Rloop = 1500 — — 3 mA

Ringing Amplitude* VRINGING

Si32266/8 Open circuit, VBAT = –110 V

— –108 — VPK

Si32267/9 Open circuit, VBAT = –140 V

— –136 — VPK

Sinusoidal Ringing Total Harmonic Distortion

RTHD

Si32266/8: 60 VRMS, 15 VOFFSET, 0–5 REN

— 1 — %Si32267/9: 55 VRMS, 48 VOFFSET, 0–5 REN

Ringing Frequency Accuracy f = 16 Hz to 60 Hz — — 1 %

Ringing Cadence Accuracy Accuracy of ON/OFF times — — 50 ms

*Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance.

Si32266/7/8/9

Rev. 1.2 9

Loop Voltage Sense Accuracy

VTIP – VRING = 48 V — 2 4 %

Loop CurrentSense Accuracy

ILOOP = 18 mA — 7 10 %

Power AlarmThreshold Accuracy

Power Threshold = 1.0 WVBAT = –56 V, ILDDD = 40 mA,

RLOAD = 600 — 15 — %

Test Load Impedance RTESTHVIC_STATE_SPARE[23] = 1;

VT/R 50 V— 2.2 — k

Test Load Voltage VTL HVIC_STATE_SPARE[23] = 1 ±5 ±50 V

Table 5. Digital I/O Characteristics(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)


High Level Input Voltage VIH 2.0 — VDD V

Low Level Input Voltage VIL 0 — 0.8 V

High Level Output Voltage

VOH

MOSI, GPIO1/STIPC, GPIO2/SRINGC:

IO = –4 mAVDD – 0.6 — — V

Low Level Output Voltage

VOL

MOSI, GPIO1/STIPC, GPIO2/SRINGC:IO = 4 mA

— — 0.4 V

RST Internal Pullup Current

33 42 80 µA

Input Leakage Current IL — — 10 µA

Table 4. Linefeed Characteristics (Continued)(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)


*Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance.

Si32266/7/8/9

10 Rev. 1.2

Figure 1. Reset Timing Diagram

Table 6. Charge Pump Characteristics(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C)


Output Voltage (DCDRVa/b, DCFFa/b)

VCP 2 x VDD – 1 — 2xVDD V

Output Current ICP — — 3* mA

*Note: Peak drive current capability is >60 mA.

Table 7. Switching Characteristics—General Inputs*

(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C, CL = 20 pF)

Parameter Symbol Min Typ Max Unit

Rise Time, RST tr — — 5 ns

RST Pulse Width trl 396/PSCLK

— — µs

*Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels areVIH = VDD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

PSCLK

RSTB

395 396 393 392 5 4 3 2 1 1 2 3 4 50 392 393 394 395Counting of PSCLKRising Edges

Note: The count of PCLK rising edges during reset will be skewed by 1-2 clocks based on the internal sampling of reset.

Si32266/7/8/9

Rev. 1.2 11

Figure 2. ISI Timing Diagram

Table 8. Switching Characteristics—ISI(VDDA = 3.13 to 3.47 V, TA = 0 to 70 °C, CL = 20 pF)

Parameter Symbol Min Typ Max Unit

Setup Time, MOSI to PSCLK Fall tsu 7.5 — — ns

Hold Time, MOSI to PSCLK Fall th 5 — — ns

Delay Time, PSCLK Rise to MISO td — — 16 ns

PSCLK Period tp — 40.69 — ns

PSCLK Duty Cycle 40 50 60 %

PSCLK

tp

td

tsu th

Si32266/7/8/9

12 Rev. 1.2

Figure 3. Transmit and Receive Path SNDR

Figure 4. Overload Compression Performance

Acceptable Region

1 2 3 4 5 6 7 8 9

1

2

3

4

5

6

7

8

9

0

2.6

AcceptableRegion

Fundamental Input Power (dBm0)

FundamentalOutput Power

(dBm0)

Si32266/7/8/9

Rev. 1.2 13

Figure 5. Receive Path Frequency Response

0 052 005 057 0001 0521 0051 0571 0002 0522 0052 0572 0003 0523 0053 0573 0004 0524 0054 0574 005 054−

04−

53−

03−

52−

02−

51−

01−

5−

0

5noitrotsiD noitaunettA XR

Gai

n (d

B)

)zH( ycneuqerF

0 052 005 057 0001 0521 0051 0571 0002 0522 0052 0572 0003 0523 0053 0573 0004 0524 0054 0574 005 0

2.1−

1−

8.0−

6.0−

4.0−

2.0−

0

2.0

4.0liateD dnaB−ssaP XR

Gai

n (d

B)

)zH( ycneuqerF

Si32266/7/8/9

14 Rev. 1.2

Figure 6. Transmit Path Frequency Response

0 052 005 057 0001 0521 0051 0571 0002 0522 0052 0572 0003 0523 0053 0573 0004 0524 0054 0574 005 054−

04−

53−

03−

52−

02−

51−

01−

5−

0

5noitrotsiD noitaunettA XT

Loss

(dB

)

)zH( ycneuqerF

0 052 005 057 0001 0521 0051 0571 0002 0522 0052 0572 0003 0523 0053 0573 0004 0524 0054 0574 005 0

2.1−

1−

8.0−

6.0−

4.0−

2.0−

0

2.0

4.0liateD dnaB−ssaP XT

Loss

(dB

)

)zH( ycneuqerF

Si32266/7/8/9

Rev. 1.2 15

Figure 7. Transmit Group Delay Distortion

Figure 8. Receive Group Delay Distortion

200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 34000

100

200

300

400

500

600

700

800

900

1000

1100TX Group Delay Distortion

)su( noitrotsiD

Frequency (Hz)

200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 34000

100

200

300

400

500

600

700

800

900

1000

1100RX Group Delay Distortion

)su( noitrotsiD

Frequency (Hz)

Typical Response

Si32266/7/8/9

16 Rev. 1.2

Table 9. Thermal Conditions

Parameter Symbol Test Condition Value Unit

Thermal Resistance, Typical*

QFN-50JA 48 °C/W

Maximum Junction Temperature, QFN-50 (Linefeed Die)

TJHV Continuous 145 °C

Maximum Junction Temperature QFN-50 (Low Voltage Die)

TJLV 125 °C

*Note: The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal/bottom copper plane

Table 10. Absolute Maximum Ratings1

Parameter Symbol Test Condition Value Unit

Storage Temperature Range TSTG –55 to 150 °C

Continuous Power Dissipation2,3

QFN-50PD TA = 85 °C 1.25 W

Supply Voltage VDDD, VDDA –0.5 to 4.0 V

Digital Input Voltage VIND –0.3 to 3.6 V

Battery Supply Voltage4, Si32266/8 VBAT +0.4 to –115 V

Battery Supply Voltage4, Si32267/9 VBAT +0.4 to –142 V

TIP or RING Voltage, Si32266/85 VTIP, VRING +0.4 to –130 V

TIP or RING Voltage, Si32267/95 VTIP, VRING +0.4 to –142 V

TIP, RING Current ITIP, IRING ±100 mA

Notes:1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet.2. Operation of the Si3226x low voltage die above 125 °C junction temperature may degrade device reliability.3. Si3226x linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction

temperature exceeds the thermal shutdown threshold.4. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.5. Specification requires circuit for surge event as shown in typical application circuit. See “AN381: Si3226x ProSLIC

Designer’s Guide.”

Si32266/7/8/9

Rev. 1.2 17

2. Typical Application Circuits

2.1. Si32266/7 Flyback Tracking DC-DC Converter

ISI Bus

DC/DC Converter A

page

6

200V

150V

±1%

±10%

±10%

±0.5%

200V

150V

150V

±10%

150V

±1%

±10%

150V

150V

200V

DC/DC Converter A

200V

DC/DC Converter B

DC/DC Converter B

page

4pa

ge 5

page

7

200V

±10%

200V

±10%

ST

IPC

aS

RIN

GC

a

VD

DA

DC

DR

Va

SD

CH

a

SV

BA

Ta

ST

IPC

a

SR

ING

Ca

RIN

Ga

VD

DD

TIP

a

ST

IPC

b

TIP

b

SR

ING

Cb

RIN

Gb

SD

CL

aS

DC

Ha

SV

BA

Ta

SD

CL

bS

DC

Hb

SV

BA

Tb

ST

IPC

bS

RIN

GC

b

VDDDVDDA

SV

BA

Tb

DC

DR

Vb

SD

CH

b

SL

IC-R

ING

a

SL

IC-R

ING

b

SL

IC-T

IPa

SL

IC-T

IPb

SD

CL

aS

DC

Lb

DC

DR

Va

DC

DR

Vb

VD

C

VB

AT

a

VB

AT

a

VD

C+

3V

3

VB

AT

b

VB

AT

b

VB

AT

a

VD

C

VB

AT

b

VD

C

MO

SI

PS

CL

K

/SL

IC_

RE

SE

T

MIS

O

C2

02

0.0

1uF C2

02

0.0

1uF

R1550 R1550

R20

168

1KR

201

681K

R1

09

11

0K

R1

09

11

0K

D155

BAS21HT1

NID155

BAS21HT1

NI

C2

04 0

.01

uF

C2

04 0

.01

uFP

RO

T2

Pro

tect

ion

TIP

RIN

GT

IP_ext

VBATEGND

RIN

G_ext

C2

06

0.1

uFC

20

60

.1uF

Si3

2267

U1

Si3

2267

U1

TIP

A1

NC

2

GP

IO2A

/SR

ING

CA

3G

PIO

1A

/ST

IPC

A4

SR

ING

DC

A5

SR

ING

AC

A6

ST

IPA

CA

7

ST

IPD

CA

8

CA

PP

A9

CA

PM

A10

SV

BA

TA

11

SVDC12

RS

TB

13

PS

CLK

/PC

LK

14

MIS

O15

MO

SI

16

SD

CH

A17

SD

CLA

18

DC

DR

VA

19

AU

XO

I/D

CF

FA

20

AU

XD

RV

/DC

FF

B21

DC

DR

VB

22

SD

CLB

23

SD

CH

B24

VDDD25

VDDREG26

SV

BA

TB

27

CA

PM

B28

CA

PP

B29

IRE

F30

ST

IPD

CB

31

ST

IPA

CB

32

SR

ING

AC

B33

SR

ING

DC

B34

GP

IO1B

/ST

IPC

B35

GP

IO2B

/SR

ING

CB

36

VDDA37

NC

42

TIP

B39

NC

44

RIN

GB

41

NC

38

VBATB43

NC

50

VR

EF

_B

T45

NC

40

VBATA47

NC

48

RIN

GA

49

NC

46

GNDEPAD2

HWEPAD1

R20

31K

R20

31K

J1RJ-

11

SL

ICa

J1RJ-

11

SL

ICa

11

22

33

44

55

66

R10

41K

R10

41K

R20

0

1.65

M

R20

0

1.65

M

C2

05

0.1

uFC

20

50

.1uF

R10

31K

R10

31K

R10

168

1KR

101

681K

+C

13

01

20

uF+

C1

30

12

0uF

DC

DC

1

DC

DC

VB

AT

VDC

DC

DR

V

SD

CH

GND

SD

CL

C1

10

uFN

I

C1

10

uFN

I

R10

268

1KR

102

681K

DC

DC

2

DC

DC

VB

AT

VDC

DC

DR

V

SD

CH

GND

SD

CL

C1

01

0.0

1uF

C1

01

0.0

1uF

C1

03

0.0

1uF

C1

03

0.0

1uF

C1

02

0.0

1uF C1

02

0.0

1uF

R10

61.

47M

R10

61.

47M

C7

0.1

uFC7

0.1

uF

C1

04

0.0

1uF

C1

04

0.0

1uF

J2RJ-

11

SL

ICb

J2RJ-

11

SL

ICb

11

22

33

44

55

66

R10

71.

47M

R10

71.

47M

R20

10K

NI

R20

10K

NI

C4

0.1

uFC

40

.1uF

EP

AD

EP

AD

C1

00

0.1

uFC

10

00

.1uF

R6

20

R6

20

PR

OT

1P

rote

ctio

n TIP

RIN

GT

IP_ext

VBATEGND

RIN

G_ext

R10

0

1.65

M

R10

0

1.65

M

R6

11

0.0

R6

11

0.0

C6

10

uFC6

10

uF

D2

BA

V2

3A

NI

D2

BA

V2

3A

NI

R6

00

R6

00

C2

00

0.1

uFC

20

00

.1uF

D255

BAS21HT1

NID255

BAS21HT1

NI

R1

08

11

0K

R1

08

11

0K

C2

0.1

uF

C2

0.1

uF

C1

05

0.1

uFC

10

50

.1uF

R20

61.

47M

R20

61.

47M

R1560 R1560

R2

09

11

0K

R2

09

11

0K

R20

71.

47M

R20

71.

47M

R2

49.9

K

R2

49.9

K

R1

72

67

KR

17

26

7K

C2

03 0

.01

uF

C2

03 0

.01

uF

R20

41K

R20

41K

R2

08

11

0K

R2

08

11

0K

R20

268

1KR

202

681K

C2

01

0.0

1uF

C2

01

0.0

1uF

C1

06

0.1

uFC

10

60

.1uF

Fig

ure

9.S

i326

6/7F

lyb

ack

Trac

kin

g D

C-D

C C

on

vert

er T

op

Lev

el S

chem

atic

Si32266/7/8/9

18 Rev. 1.2

Figure 10. Si32266/7 Flyback Tracking DC DC1

Figure 11. Si32266/7 Flyback Tracking DC DC2

This design is optimized for VDC=4.5V-27V

Route as a differential pair

200V 200V200V 200V

-12V >= VBAT >= -138VIBAT <= 100mA

Ipeak <=4.0AmpsIndustrial Temp Only -40C-85C

PBAT <= 8.5W

Efficiency up to 85% depending on mode of operation.

Optional

Optional

Optional 20V-27V operation limits VBAT < 125V

VBAT

VDC

DCDRV

SDCH

GND

SDCL

VDC

VDC

C1240.1uFC1240.1uF

R122

15

R122

15

C120

10uF NI

C120

10uF NI

Q120

FQT7N10L

Q120

FQT7N10L

R12715NI

R12715NI

R1210.1R1210.1

C121

0.1uF

C121

0.1uF

R123

15

R123

15

R124

0

R124

0

D120

ES1F

D120

ES1F

D122

BAS16X NI

D122

BAS16X NI

C1250.1uF

NI

C1250.1uF

NI

C1220.1uFC1220.1uF

C126470pFNI

C126470pFNI

R125

0

R125

0

C1230.1uFC1230.1uF

T120

8uH

T120

8uH4 5

1 8

D121 75V

NI

D121 75V

NI

R12668KR12668K

This design is optimized for VDC=4.5V-27V

Route as a differential pair

200V 200V200V 200V

-12V >= VBAT >= -138VIBAT <= 100mA

Ipeak <=4.0AmpsIndustrial Temp Only -40C-85C

PBAT <= 8.5W


Optional

Optional

Optional 20V-27V operation limits VBAT < 125V

VBAT

VDC

DCDRV

SDCH

GND

SDCL

VDC

VDC

C2240.1uFC2240.1uF

R222

15

R222

15

C220

10uF NI

C220

10uF NI

Q220

FQT7N10L

Q220

FQT7N10L

R22715NI

R22715NI

R2210.1R2210.1

C221

0.1uF

C221

0.1uF

R223

15

R223

15

R224

0

R224

0

D220

ES1F

D220

ES1F

D222

BAS16X NI

D222

BAS16X NI

C2250.1uF

NI

C2250.1uF

NI

C2220.1uFC2220.1uF

C226470pFNI

C226470pFNI

R225

0

R225

0

C2230.1uFC2230.1uF

T220

8uH

T220

8uH4 5

1 8

D221 75V

NI

D221 75V

NI

R22668KR22668K

Si32266/7/8/9

Rev. 1.2 19

Figure 12. Si32266/7 Flyback Protection 1

Figure 13. Si32266/7 Flyback Protection 2

±10%

RING

TIP

RING_ext

TIP_ext

EGND

VBAT

VBAT

VBAT

U151

TISP61089BDR

U151

TISP61089BDR

K11

-VR

EF

2

NC3

K24

K25

A6

A7

K18

C108

0.01uF200VC108

0.01uF200V

R151

10

R151

10

R150

10

R150

10

RF151

B0500T

RF151

B0500T

12

C150

0.1uF

C150

0.1uF

RF150

B0500T

RF150

B0500T

12

±10%

RING

TIP

RING_ext

TIP_ext

EGND

VBAT

VBAT

VBAT

U251

TISP61089BDR

U251

TISP61089BDR

K11

-VR

EF

2

NC3

K24

K25

A6

A7

K18

C208

0.01uF200VC208

0.01uF200V

R251

10

R251

10

R250

10

R250

10

RF251

B0500T

RF251

B0500T

12

C250

0.1uF

C250

0.1uF

RF250

B0500T

RF250

B0500T

12

Si32266/7/8/9

20 Rev. 1.2

2.2. Si32268 TSS DC-DC Converter

100V

150V

±1%

±10%

±10%

±0.5%

100V

200V

200V

±10%

150V

±1%

±10%

200V

200V

100V

100V

100V

±10%

100V

±10%

page

4

AUX

Conv

erte

r Mo

de

Char

ge P

umps

ON B

OARD

VBA

T GE

NERA

TOR

150V

150V

150V

ST

IPC

aS

RIN

GC

a

VD

DA

ST

IPC

a

SR

ING

Ca

RIN

Ga

VD

DD

TIP

a

ST

IPC

b

TIP

b

SR

ING

Cb

RIN

Gb

SV

BA

Ta

SV

BA

Tb

ST

IPC

bS

RIN

GC

b

VDDDVDDA

SL

IC-R

ING

a

SL

IC-R

ING

b

SL

IC-T

IPa

SL

IC-T

IPb

BA

SE

a

BA

SE

b

AU

XD

RV

SVDC

AU

XD

RV

AU

XS

DC

HA

UX

SD

CL

AU

XS

DC

HA

UX

SD

CL

SV

DC

BA

TP

O

VD

C

3V

3

3V

3

VB

AT

bV

BA

Ta

VB

AT

aV

BA

Tb

VB

AT

a

VB

AT

b

VB

LO

VB

LO

VB

RIN

G

VB

RIN

G

VB

AT

a VB

AT

b

MO

SI

SC

LK

MIS

O

/RE

SE

T/IN

T

C1

04

0.0

1uF

C1

04

0.0

1uF

C2

0.1

uF

C2

0.1

uF

D255

BAS21HT1

NID255

BAS21HT1

NI

DC

DC

VDC

GA

TE

DR

V

SD

CH

GND

VB

LO

SD

CL

VB

RIN

G

R10

01.

65M

R10

01.

65M

C2

01

0.0

1uF

C2

01

0.0

1uF

R1

08

11

0K

R1

08

11

0K

R1110 R1110

C1

02

0.0

1uF C1

02

0.0

1uF

PR

OT

2P

rote

ctio

n

TIP

RIN

GT

IP_ext

EGND

RIN

G_ext

VB

AT

R20

268

1KR

202

681K

PR

OT

1P

rote

ctio

n TIP

RIN

GT

IP_ext

EGND

RIN

G_ext

VB

AT

R19

10K

R19

10K

EP

AD

EP

AD

C1

03

0.0

1uF

C1

03

0.0

1uF

J1RJ-

11

SL

ICa

J1RJ-

11

SL

ICa

11

22

33

44

55

66

C1

05

0.1

uFC

10

50

.1uF

R1

7

1.1

5M

R1

7

1.1

5M

R2

49.9

K

R2

49.9

K

C1

01

0.0

1uF

C1

01

0.0

1uF

R1

09

11

0K

R1

09

11

0K

C2

05

0.1

uFC

20

50

.1uF

R20

71.

47M

R20

71.

47M

C7

0.1

uFC7

0.1

uF

R20

168

1KR

201

681K

R2

08

11

0K

R2

08

11

0K

R20

31K

R20

31K

R6

20

R6

20

C4

0.1

uFC

40

.1uF

C1

00

0.1

uFC

10

00

.1uF

R6

30

R6

30

Po

we

r O

fflo

ad

BA

SE

b

BA

SE

a

BA

TP

O

VB

AT

b

VB

AT

a

VBLO

C6

10

uFC6

10

uF

R20

41K

R20

41K

R20

61.

47M

R20

61.

47M

R2

09

11

0K

R2

09

11

0K

C2

04 0

.01

uF

C2

04 0

.01

uF

R10

268

1KR

102

681K

Si3

2268

U1

Si3

2268

U1

TIP

A3

NC

2

GP

IO2A

/SR

ING

CA

5G

PIO

1A

/ST

IPC

A6

SR

ING

DC

A7

SR

ING

AC

A8

ST

IPA

CA

9

ST

IPD

CA

10

CA

PP

A11

CA

PM

A12

SV

BA

TA

13

SVDC14

RS

TB

15

NC

41

PS

CLK

/PC

LK

16

DA

TA

o17

DA

TA

i18

NC

45

NC

48

NC

43

AU

XO

I/D

CF

FA

19

AU

XD

RV

/DC

FF

B20

DC

DR

VB

21

SD

CLB

22

SD

CH

B23

VDDD24

VDDREG25

SV

BA

TB

26

CA

PM

B27

CA

PP

B28

IRE

F29

ST

IPD

CB

30

ST

IPA

CB

31

SR

ING

AC

B32

SR

ING

DC

B33

GP

IO1B

/ST

IPC

B34

GP

IO2B

/SR

ING

CB

35

VDDA36

NC

37

TIP

B38

NC

39

RIN

GB

40

NC

4

VBATB42

BA

SE

B44

BA

T_P

O46

BA

SE

A47

VBATA49

RIN

GA

1

GNDEPAD2

HWEPAD1

NC

50

C2

00

0.1

uFC

20

00

.1uF

R20

10K

NI

R20

10K

NI

R10

71.

47M

R10

71.

47M

C1

10

uFN

I

C1

10

uFN

I

D155

BAS21HT1

NID155

BAS21HT1

NI

R2110 R2110

R20

01.

65M

R20

01.

65M

R10

168

1KR

101

681K

R10

31K

R10

31K

C1

06

0.1

uFC

10

60

.1uF

J2RJ-

11

SL

ICb

J2RJ-

11

SL

ICb

11

22

33

44

55

66

R6

00

R6

00

R10

61.

47M

R10

61.

47M

C2

03 0

.01

uF

C2

03 0

.01

uF

R10

41K

R10

41K

C2

06

0.1

uFC

20

60

.1uF

C2

02

0.0

1uF C2

02

0.0

1uF

Fig

ure

14.S

i322

68 T

SS

DC

-DC

Co

nve

rter

—To

p L

evel

Sch

emat

ic

Si32266/7/8/9

Rev. 1.2 21

Figure 15. Si32268 TSS DC-DC Converter

Figure 16. Si32268 TSS Power Offload

N=3

N=2

N=1

-50V >= VBRING >= -103VIBAT <= 200mAPBATPeak <= 12W

VBLO = VBRING/(N3/N1)IBAT <= 80mAPBAT <= 3W

This design is optimized for VDC=10.8V to 20V

Ipeak <=4.0AmpsIndustrial Temp: -40C -> +85C


VDC

SDCH

GNDVBLO

SDCL

VBRING

GATEDRV

VDC

VDC

C1300.1uFC1300.1uF

R123

0

R123

0

D120ES1D

D120ES1D

+C131

220uF

+C131

220uF

Q120

FQT7N10L

Q120

FQT7N10L

R125

10

R125

10

D121

ES1D

D121

ES1D

C120

10uF NI

C120

10uF NI

T120

8uH

T120

8uH

4

5

1

8

7

6

C1230.1uFC1230.1uF

C1280.1uFC1280.1uF

C121

0.1uF

C121

0.1uF

R122

10

R122

10

R12715R12715

R143

0

R143

0

R12668KR12668K

+C1243.3uF

+C1243.3uF

C1220.1uFC1220.1uF

+C12510uF

+C12510uF

R144

0

R144

0

C132470pFC132470pF

R1210.1R1210.1

BASEbBASEa

BATPO

VBATbVBATa

VBLO

R11024.9R11024.9

D100BAS21HT1D100BAS21HT1

R21024.9R21024.9

Q100CZT5551

Q100CZT5551

Q200CZT5551

Q200CZT5551

D200BAS21HT1D200BAS21HT1

Si32266/7/8/9

22 Rev. 1.2

Figure 17. Si32268 TSS Protection 1

Figure 18. Si32268 TSS Protection 2

±10%

TIP

RING

TIP_ext

RING_ext

EGND

VBAT

VBAT

VBAT

C108

0.01uF

C108

0.01uF

tRT152

PTC

tRT152

PTC

R151

10

R151

10

C1090.1uFC1090.1uF

tRT153

PTC

tRT153

PTC

U150

TISP61089BDR

U150

TISP61089BDR

K11

G2

NC3

K24

K25A6A7K18

R150

10

R150

10

±10%

TIP

RING

TIP_ext

RING_ext

EGND

VBAT

VBAT

VBAT

C208

0.01uF

C208

0.01uF

tRT252

PTC

tRT252

PTC

R251

10

R251

10

C2090.1uFC2090.1uF

tRT253

PTC

tRT253

PTC

U250

TISP61089BDR

U250

TISP61089BDR

K11

G2

NC3

K24

K25A6A7K18

R250

10

R250

10

Si32266/7/8/9

Rev. 1.2 23

3. Bill of Materials

Table 11. Si32267 Flyback Tracking DC-DC Converter Bill of Materials—Top Level

Ref Value Rating Volt Tol Type PCB Footprint Mfr Part Number Mfr

C1 (NI) 10uF 6.3V ±20% X5R C0603 C0603X5R6R3-106M Venkel

C120 (NI) C220 (NI)

10uF 25V ±20% X7R C1210 C1210X7R250-106M Venkel

C125 (NI)C225 (NI)

0.1uF 200V ±20% X7R C1206 C1206X7R201-104M Venkel

C126 (NI)C226 (NI)

470pF 100V ±10% X7R C0603 C0603X7R101-471K Venkel

D2 (NI) BAV23A 400mA 200V DUAL SOT23-KKA BAV23A Diodes Inc.

C105 C205 0.1uF 200V ±20% X7R C1206 C1206X7R201-104M Venkel

C130 120uF 600mA 63V ±20% Alum_Elec C5X10MM-RAD

EEUFC1J121 Panaso-nic

Q120 Q220 FQT7N10L 1.7A 100V Nchan SOT223-GDS FQT7N10L Fairchild

RF150 RF151 RF250 RF251

B0500T 0.5A 600V TelCom FUSE-B0500T B0500T Bourns

R61 10 1/16W ±1% ThickFilm R0603 CR0603-16W-10R0F Venkel

R100 R200 1.65M 1/10W ±1% ThickFilm R0805 CR0805-10W-1654F Venkel

R101 R102 R201 R202

681K 1/10W ±1% ThickFilm R0805 CR0805-10W-6813F Venkel

R103 R104 R203 R204


R106 R107 R206 R207

1.47M 1/8W ±1% ThickFilm R1206 CR1206-8W-1474F Venkel

R155 R156 0 2A ThickFilm R0805 CR0805-10W-000 Venkel

U1 Si32267 -136V MCM NBA50N6X8P0.5

Si32267-C SiLabs

R17 267K 1/10W ±1% ThickFilm R0805 CR0805-10W-2673F Venkel



R2 49.9K 1/16W ±0.5% ThickFilm R0603 CR0603-16W-4992D Venkel

J1 J2 RJ-11 RJ-11 RJ11-6-SMT 5555077-2 AMP

Si32266/7/8/9

24 Rev. 1.2

Table 12. Si32267 Flyback Tracking DC-DC Converter Bill of Materials—DC-DC

Ref Value Rating Volt Tol Type PCB Footprint

Mfr Part Number Mfr

D122 (NI)D222 (NI)

BAS16X 200mA 75V Single SOD523 BAS16XV2T1G On Semi

D155 (NI)D255 (NI)

BAS21HT1

200mA 250V Single SOD-323 BAS21HT1 On Semi

R20 (NI) 10K 1/16W ±5% ThickFilm R0402 CR0402-16W-103J Venkel

R127 (NI)R227 (NI)

15 1/2W ±5% ThickFilm R1210 CR1210-2W-150J Venkel

C2 C4 C7 C100 C106 C200 C206

0.1uF 10V ±10% X7R C0402 C0402X7R100-104K Venkel

C6 10uF 6.3V ±20% X5R C0603 C0603X5R6R3-106M Venkel

C108 C208 0.01uF 200V ±10% X7R C0805 C0805X7R201-103K Venkel


C122 C123 C124 C222 C223 C224


D120 D220 ES1F 1.0A 300V Single DO-214AC ES1F Fairchild

R108 R109 R208 R209


R121 R221 0.1 1/2W ±1% ThickFilm R1210 LCR1210-R100F Venkel

R122 R222 15 1/2W ±5% ThickFilm R1210 CR1210-2W-150J Venkel

R123 R223 15 1/16W ±1% ThickFilm R0402 CR0402-16W-15R0F Venkel

R124 R125 R224 R225

0 1A ThickFilm R0402 CR0402-16W-000 Venkel

R126 R226 68K 1/16W ±5% ThickFilm R0402 CR0402-16W-683J Venkel

T120 T220 8uH 4A XFMR-UTB01701s

UTB01890s UMEC

Si32266/7/8/9

Rev. 1.2 25

Table 13. Si32267 Flyback Tracking DC-DC Converter Bill of Materials—Protection


D121 (NI)D221 (NI)

75V 200mW 75V Zener SOD-123 BZX384C75-V Vishay

C101 C102 C103 C104 C201 C202 C203 C204


R150 R151 R250 R251

10 1/10W ±1% Thick-Film

R0805 CR0805-10W-10R0F Venkel

U151 U251 TISP61089BD

R

-150V SLIC SO8N6.0P1.27 TISP61089BDR Bourns

Table 14. Si32268 TSS DC-DC Converter Application Circuit Bill of Materials—Top Level


C1 (NI) 10uF 6.3V ±20% X5R C0603 C0603X5R6R3-106M Venkel

C120 (NI) 10uF 25V ±20% X7R C1210 C1210X7R250-106M Venkel

D155 (NI)D255 (NI)

BAS21HT1 200mA 250V Single SOD-323 BAS21HT1 On Semi

R20 (NI) 10K 1/16W ±5% ThickFilm R0402 CR0402-16W-103J Venkel

C2 C4 C7 C100 C106 C200 C206


D100 D200 BAS21HT1 200mA 250V Single SOD-323 BAS21HT1 On Semi

D120 D121 ES1D 1.0A 200V Single DO-214AC ES1D Diodes Inc.

RT152 RT153 RT252 RT253

PTC 3A 250V TelCom PTC-MF-SM013/250V MF-SM013/250V Bourns

R2 49.9K 1/16W ±0.5% ThickFilm R0603 CR0603-16W-4992D Venkel

R17 1.15M 1/10W ±1% ThickFilm R0805 CR0805-10W-1154F Venkel

R19 10K 1/16W ±5% ThickFilm R0402 CR0402-16W-103J Venkel

R60 R62 R63


R100 R200 1.65M 1/10W ±1% ThickFilm R0805 CR0805-10W-1654F Venkel

R101 R102 R201 R202


R103 R104 R203 R204


Si32266/7/8/9

26 Rev. 1.2

R106 R107 R206 R207

1.47M 1/8W ±1% ThickFilm R1206 CR1206-8W-1474F Venkel

R108 R109 R208 R209



U1 Si32268 –110V MCM NBA50N6X8P0.5 Si32268-C SiLabs

Table 15. Si32268 TSS DC-DC Converter Application Circuit Bill of Materials—DC-DC





C121 0.1uF 25V ±20% X7R C0603 C0603X7R250-104M Venkel

C122 C123 C128 C130


C124 3.3uF 200V ±20% Alum_Elec C2.5X6.3MM-RAD UVR2D3R3MED Nichicon

C125 10uF 160V ±20% Alum_Elec C5X10MM-RAD ECA2CM100 Panaso-nic

C132 470pF 100V ±10% X7R C0603 C0603X7R101-471K Venkel

Q100 Q200 CZT5551 2W 180V NPN SOT223-BCE CZT5551 Central Semi

R121 0.1 1/2W ±1% ThickFilm R1210 LCR1210-R100F Venkel

R122 R125 10 1/4W ±1% ThickFilm R1206 CR1206-4W-10R0F Venkel

R123 R143 R144


R126 68K 1/16W ±5% ThickFilm R0402 CR0402-16W-683J Venkel

R127 15 1/4W ±5% ThickFilm R1206 CR1206-4W-150J Venkel

T120 8uH 5A, 25W

XFMR-UTB01701s UTB01701s UMEC

Table 14. Si32268 TSS DC-DC Converter Application Circuit Bill of Materials—Top Level


Si32266/7/8/9

Rev. 1.2 27

Table 16. Si32268 TSS DC-DC Converter Application Circuit Bill of Materials—Power Offload


C131 220uF 555mA 25V ±20% Alum_Elec C3.5X8MM-RAD EEUFC1E221 Panasonic

J1 J2 RJ-11 RJ-11 RJ11-6-SMT 5555077-2 Tyco

R110 R210 24.9 1/4W ±1% ThickFilm R1206 CR1206-4W-24R9F

Venkel

Table 17. Si32268 TSS DC-DC Converter Application Circuit Bill of Materials—Protection


C6 10uF 6.3V ±20% X5R C0603 C0603X5R6R3-106M Venkel

C101 C102 C103 C104 C201 C202 C203 C204


Q120 FQT7N10L 1.7A 100V Nchan SOT223-GDS FQT7N10L Fairchild

R150 R151 R250 R251

10 1/10W ±1% ThickFilm R0805 CR0805-10W-10R0F Venkel

U150 U250 TISP61089BDR –150V SLIC SO8N6.0P1.27 TISP61089BDR Bourns

Si32266/7/8/9

28 Rev. 1.2

4. Functional Description

Figure 19. Functional Block Diagram

The Si3226x dual ProSLIC devices provide all SLIC,codec, DTMF detection, and signal generation functionsneeded for two complete analog telephone interfaces.They perform all battery, over-voltage, ringing,supervision, codec, hybrid, and test (BORSCHT)functions, and also support extensive metallic looptesting capabilities.

The Si3226x devices provide a standard voice-band (200 Hz–3.4 kHz) audio codec and, optionally, an audiocodec with both wideband (50 Hz–7 kHz) and standardvoiceband modes. The wideband mode provides anexpanded audio band with a 16 kHz sample rate forenhanced audio quality while the standard voice-bandmode provides standard telephony audio bandwidth.

The Si3226x devices incorporate programmable dc-dcconverter controllers that can operate in either batterytracking mode (Si32266/7) or a shared rail mode(Si32268/9). In both the battery tracking and the sharedrail modes the dc-dc converter controllers react to lineconditions to provide the optimal battery voltagerequired for each line-state. Multiple Si32268/9 devicescan also operate from fixed rail supplies controlledeither by one of the integrated dc-dc controllers or by anexternal dc-dc controller. The Si3226x devices areavailable with voltage ratings of –110 or –140 V tosupport a wide range of ringing voltages. See Section"8. Ordering Guide‚" on page 42 for the voltage rating ofeach version.

Programmable on-hook voltage, programmable offhookloop current, reverse battery operation, loop or groundstart operation, and on-hook transmission aresupported. Loop current and voltage are continuouslymonitored by an integrated monitoring ADC. TheSi3226x dual ProSLIC devices support balanced andunbalanced 5 REN ringing with or without aprogrammable dc offset, and can operate in low powerringing and adaptive ringing modes. The availableoffset, frequency, waveshape, and cadence options aredesigned to ring the widest variety of terminal devicesand to reduce external controller requirements.

A complete audio transmit and receive path isintegrated, including ac impedance and hybrid gain.These features are software-programmable, allowing asingle hardware design to meet global requirements.

PCM/

Interface

DSP

DTMF &Tone Gen

Pro

gram

mab

le

AC

Impe

danc

ean

d H

ybrid

Caller ID

RingingGenerator

ADC

DAC

CODEC SLICLinefeedControl

LinefeedMonitor

DC-DC Controller

Line Diagnostics

PLLPSCLK

MISO

MOSI

Inte

gra

ted

Ser

ial

Inte

rfac

e

DSP

DTMF &Tone Gen

Pro

gram

mab

le

AC

Impe

danc

ean

d H

ybrid

Caller ID

RingingGenerator

ADC

DAC

CODEC

DC-DC Controllers

Line Diagnostics

PLL

Si32266/7/8/9

DACRING

TIP

Line

feed

Channel A

CODEC SLIC

DACRING

TIP

Line

feed

Channel B

CODEC SLIC

ADC

ADC

LinefeedControl

LinefeedMonitor

LinefeedControl

LinefeedMonitor

Si32266/7/8/9

Rev. 1.2 29

5. FXS Features

5.1. DC Feed CharacteristicsProSLIC internal linefeed circuitry provides completelyprogrammable dc feed characteristics.

When in the active state, the ProSLIC operates in one ofthree dc linefeed operating regions: a constant-voltageregion, a constant-current region, or a resistive region,as shown in Figure 20. The constant-voltage region hasa low resistance, typically 160 . The constant-currentregion approximates infinite resistance.

Figure 20. Dual ProSLIC DC Feed Characteristics

5.2. Linefeed Operating StatesThe linefeed interface includes nine different register-programmable operating states as listed in Table 18.The Open state is the default condition in the absenceof any preloaded register settings. The device may alsoautomatically enter the open state in the event of alinefeed fault condition.

5.3. Line Voltage and Current MonitoringThe ProSLIC continuously monitors the TIP, RING, andbattery voltages and currents via an on-chip ADC andstores the resulting values in individual RAM locations.Additionally, the loop voltage (VTIP–VRING), loop current,and longitudinal current values are calculated based onthe TIP and RING measurements and are stored inunique register locations for further processing. TheADC updates all registers at a rate of 2 kHz or greater.

5.4. Power Monitoring and Power Fault Detection

The Si3226x line monitoring functions are used tocontinuously protect against excessive powerconditions. The Si3226x contains on-chip, analogsensing diodes that turn off the device when a presettemperature threshold is exceeded.

If the Si3226x detects a fault condition or overpowercondition, it automatically sets that line to the open stateand generates a "power alarm" interrupt.

The interrupt can be masked, but masking theautomatic transition to open is not recommended.

The various power alarms and linefeed faults supportingautomatic intervention are described below.

1. Total power exceeded.

2. Excessive foreign current or voltage on TIP and/or RING.

3. Thermal shutdown event.

5.5. Thermal Overload ShutdownIf the die temperature exceeds the maximum junctiontemperature threshold (TJmax) of 145 or 200 °C,depending on the operating state, the device has theability to shut itself down to a low-power state withoutuser intervention.

ILOOP (mA)I_RFEED

VTR(V)

I_ILIMI_VLIM

Resistive Region

Con

stan

t I R

egio

n

Constant V RegionV_VLIM

V_RFEED

V_ILIM

Si32266/7/8/9

30 Rev. 1.2

5.6. Loop Closure DetectionThe Si3226x provides a completely programmable loopclosure detection mechanism. The loop closuredetection scheme provides two unique thresholds toallow hysteresis, and also includes a programmabledebounce filter to eliminate false detection. A loopclosure detect status bit provides continuous status, anda maskable interrupt bit is also provided.

5.7. Ground Key DetectionThe Si3226x provides a ground key detect mechanismusing a programmable architecture similar to the loopclosure scheme. The ground key detect schemeprovides two unique thresholds to allow hysteresis andalso includes a programmable debounce filter toeliminate false detection. A ground key detect status bitprovides continuous status, and a maskable interrupt bitis also provided.

Table 18. Linefeed Operating States

Linefeed State Description

Open Output is high-impedance and all line supervision functions are powered down. Audio is not transmitted. This is the default state after powerup or following a hardware reset. This state can also be used in the presence of line fault conditions and to generate open switch intervals (OSIs). This state is used in line diagnostics mode as a high impedance state during linefeed testing. A power fault condition may also force the device into the open state.

Forward ActiveReverse Active

Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more posi-tive than the RING lead; in Reverse Active state, the RING lead is more positive than the TIP lead. Loop closure and ground key detect circuitry are active.

Forward OHTReverse OHT

Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING lead is more positive than the TIP lead.

TIP Open Provides an active linefeed on the RING lead and sets the TIP lead to high impedance (>400 k) for ground start operation in forward polarity. Loop closure and ground key detect circuitry are active.

RING Open Provides an active linefeed on the TIP lead and sets the RING lead to high impedance (>400 k) for ground start operation in reverse polarity. Loop closure and ground key detect circuitry are active.

Ringing Drives programmable ringing signal onto TIP and RING leads with or without dc offset.

Line Diagnostics The channel is put into diagnostic mode. In this mode, the channel has special diagnostic resources available.

Si32266/7/8/9

Rev. 1.2 31

5.8. Ringing GenerationThe Si3226x provides the ability to generate aprogrammable sinusoidal or trapezoidal ringingwaveform, with or without dc offset. The ringingfrequency, wave shape, cadence, and offset are allregister-programmable. Three ringing modes aresupported: balanced, unbalanced, and low-powerringing (LPR). Figure 21 illustrates the fundamentaldifferences between the three ringing modes.

The dual ProSLIC’s adaptive ringing capability allowsfurther power savings to be realized in systemsdesigned for long loop applications. In a long loopsystem, it may be necessary to generate a large ringingvoltage to ensure that sufficient voltage is presented to

a phone at the far end of the loop. However, insituations when a short loop is connected to an FXSinterface that was designed with the ability to ring longloops, the large ringing voltage in combination with alow resistance load will result in excessive andunnecessary power consumption. Silicon Labs’ Si3226xdual ProSLICs eliminate this unnecessary powerconsumption with their adaptive ringing capability. TheProSLIC automatically senses when excessive power isbeing consumed in the line feed circuit (due to the lowerresistance of a short loop) and will iteratively reduce theringing amplitude to a voltage that is appropriate for theload.

Figure 21. Ringing Modes

Figure 22. Adaptive Ringing

TIPRINGVBAT

Balanced

VBAT

TIPRING

LPR

TIP

RINGVBAT

UnbalancedGND GND GND

Si32266/7/8/9

32 Rev. 1.2

5.9. Polarity ReversalThe Si3226x supports polarity reversal for messagewaiting and various other signaling modes. The ramprate can be programmed for a smooth or abrupttransition to accommodate different applicationrequirements.

5.10. Two-Wire Impedance SynthesisThe ac two-wire impedance synthesis is generated on-chip using a DSP-based scheme to optimally match theoutput impedance of the Si3226x to the referenceimpedance. Most real or complex two-wire impedancescan be generated by using the coefficient generatorsoftware to simulate the desired line conditions andgenerate the required register coefficients.

5.11. Transhybrid Balance FilterThe trans-hybrid balance function is implemented on-chip using a DSP-based scheme to effectively cancelthe reflected receive path signal from the transmit path.The coefficient generator software is used to optimizethe filter coefficients.

5.12. Tone GeneratorsThe Si3226x includes two digital tone generators thatallow a wide variety of single- or dual-tone frequencyand amplitude combinations. Each tone generator hasits own set of registers that hold the desired frequency,amplitude, and cadence to allow generation of DTMFand call progress tones for different requirements. Thetones can be directed to either receive or transmit paths.

5.13. DTMF DetectionThe Dual ProSLIC performs DTMF detection.

5.14. Pulse MeteringThe pulse metering system for the Si3226x is designedto inject a 12 or 16 kHz billing tone into the audio pathwith maximum amplitude of 0.5 VRMS at TIP and RINGinto a 200 ac load impedance. The tone is generatedin the DSP via a table lookup that guarantees spectralpurity by not allowing drift. The tone will ramp up until itreaches a host-programmed threshold, at which point itwill maintain that level until instructed to ramp down,thus creating a trapezoidal envelope.

See AN381 for additional details and considerations onPulse Metering.

5.15. DC-DC ControllerThe Si32266/7 integrated line feeds are designed towork with a tracking high voltage input, one for eachchannel. The Si32266/7 integrates two dc-dc controllersthat can be used to control external tracking dc-dcconverters to generate high voltage supplies to the SLICchannels. The Si32266/7 VBATa and VBATb inputs areeach directly connected to the high voltage output oftwo tracking dc-dc converters, one for channel A andone for channel B. The VBAT voltage for each channelis optimized to minimize power consumption by closelytracking the SLIC state, even tracking the ringingwaveforms (see Section“2.1. Si32266/7 FlybackTracking DC-DC Converter” for schematics).

The Si32268/9 integrated line feeds are designed towork with two high voltage supplies shared by bothchannels. The Si32268/9 integrates a single dc-dccontroller that can be used to control a single externaldc-dc converter to generate two high voltage suppliesshared by both SLIC channels. The single flyback dc-dcconverter generates two rails using two taps on the dc-dc converter's transformer. External power offloadingtransistors are used to lower the power dissipated insidethe Si32268/8 devices by shunting excess power awayfrom the ProSLIC. In tracking shared supply (TSS)mode, in a two channel implementation, the dc-dcconverter is controlled by the integrated dc-dc controllerwhich allows the high voltage and low voltage outputsfrom the dc-dc converter to track the combined state ofthe two channels of the Si3226x ProSLIC, including theringing waveforms. Using the same schematic, the TSSmode of operation reduces system power consumptionsignificantly when compared to typical fixed rail sharedsupply designs (see Section “2.2. Si32268 TSS DC-DCConverter” for schematics).

The dc-dc controller outputs DCDRVa/b are driven byan internal charge pump which allows them to connectdirectly to the gate of the N-channel MOSFET switch ofa dc-dc converter. This connection eliminates the needfor the MOSFET pre-drive circuit that is required whenVTH is greater than VDD. See Table 6.

Si32266/7/8/9

33 Rev. 1.2

5.16. Wideband AudioThe Si3226x dual ProSLIC devices support a software-selectable wideband (50 Hz–7 kHz) and narrowband(200 Hz–3.4 kHz) audio codec. The wideband modeprovides an expanded audio band at a 16-bit, 16 kHzsample rate for enhanced audio quality whilemaintaining standard telephony audio compatibility. Inwideband operation, two time slots are used to transmitthe wideband signal and each slot contains 8-bits of the16-bit sample. These two time slots are transmitted andreceived half a frame apart, but within the same 8 kHzframe.

5.17. In-Circuit and Metallic Loop Testing A rich set of features is provided for in-circuit testing ofthe FXS system and the connected telephone line(MLT):

Tone generators

Audio diagnostic filters

Digital and analog loop-back modes

Internal test load

Monitor ADC

DSP algorithms

Using these facilities, it is possible to test the Si3226xdc-dc converter, codec, line-feed, PCM bus interface,DSP, SPI bus interface, and call progress state-machineas well as testing the connected telephone line andexternal protection circuitry.

The audio diagnostic filters on the FXS are intended toprovide programmable filtering of the TX digital audiosignal and calculate the peak and/or average signalpower of the filters’ outputs. The signal powers are thencompared to programmable thresholds. Theprogrammable filters can be used to band-pass filter acertain tone or notch out certain tones, so that the signalpower measurements are frequency selective. Thisfiltering is useful in a telephony system because it canmeasure harmonic distortion, intermodulation, noise,etc.

The Si3226x incorporates an internal test load with a2.2 k nominal value that can be connected across Tip/Ring (Figure 23). The audio diagnostics system andbuilt-in test load can be used to test the FXS interface(Si3226x) itself without requiring an external load, aconnected line, or any relays. This facility can be usedfor production and in-service testing of such things as:

Dial tone draw/break

Audio quality measurements

Pulse digit detection

DC feed

Ringtrip

Polarity reversal

Transmission loss

MLT, e.g., GR-909, is facilitated by the built-in DSP,monitor ADC, and test load. They provide the ability todetect multiple fault conditions within the CPE as well ason the Tip/Ring pair (T-R). Thirteen different measuredand/or calculated parameters are reported by theMonitor ADC. Host software for use in conjunction withthe ProSLIC API is available from Silicon Labs. TypicalMLT tests include:

Hazardous Potential Test – This checks for ac voltage > 50 VRMS or dc voltage > 135 V between Tip and Ground (T-G) or Ring and Ground (R-G).

Foreign Electromotive Force Test – Checks T-G or R-G for ac voltage > 10 VRMS or dc voltage > 6 V. Uses same threshold as for hazardous voltage test.

Resistive Faults Test – Checks for dc resistance from T-R, T-G or R-G. Any measurement < 150 k is considered a resistive fault.

Receiver-Off-Hook Test – Distinguishes between a T-R resistive fault and an off-hook condition.

Ringers Test – Measures the magnitude of the connected ring load (REN) across T-R. Results are > 0.175 REN and < 5 REN for a valid load

AC Line Impedance (line length) – T-R, T-G, and R-G. Generates a tone at several specific frequencies (audio band) and measures the reflected signal amplitude (complex spectrum) that comes back (with transhybrid balance filter disabled). The reflected signal is then used to calculate the line impedance based on certain assumptions of wire gauge, etc.

Line Capacitance – T-R, T-G, R-G. Generates a linear ramp function with polarity reversal, and measures the time constant.

Diagnostic information is available even in the presenceof fault conditions that cause the system’s protectiondevices (fuses, PTCs, etc.) to open. A high-impedancesensing path (pins SRINGC and STIPC) can be used tomeasure the conditions on Tip/Ring even when the FXSsystem is effectively disconnected from the line. Norelay is required and this sensing path inherently meetsDielectric Withstand per GR-49 (> 1000 V).

Si32266/7/8/9

34 Rev. 1.2

Figure 23. Si32266/7/8/9 Internal Test Load Circuit

TIP

RING

Test Load

RTL = 2.2 k (typical)

Si32266/7/8/9

Rev. 1.2 35

6. Integrated Serial Interface

The Si32266/7/8/9 devices' integrated serial interface (ISI) is a three-wire proprietary interface which serializes SPIand PCM communications, reducing the SoC interface from nine wires to three (PSCLK, MISO, MOSI). SPIcommunications and PCM data transfers are embedded in the serial data. The host side of the ISI is integratedonto selected SoCs from several vendors.

ISI is a point to point interface, it is not possible to daisy chain more than one ISI ProSLIC device.

Both µ-255 Law (µ-Law) and A-law companding formats are supported in addition to 16-bit linear data mode withno companding.

Si32266/7/8/9

36 Rev. 1.2

7. Pin Descriptions

7.1. Si32266/7 Pin Assignments

Pin # Pin Name Description

1 TIPaTIP Terminal—Channel A.Connect to the TIP lead of the channel A subscriber loop.

2 N/CNo Connect.This pin should be left unconnected.

3 GPIO2a/SRINGCaGeneral Purpose I/O or RING Coarse Sense Input—Channel A.RING channel A Voltage sensing outside protection circuit.

4 GPIO1a/STIPCaGeneral Purpose I/O or TIP Coarse Sense Input—Channel A.TIP channel A voltage sensing outside protection circuit.

5 SRINGDCaRING DC Sense Input—Channel A.Analog dc input to sense voltage on the channel A RING lead.

6 SRINGACaRING AC Sense Input—Channel A.Analog ac input to sense voltage on the channel A RING lead.

7 STIPACaTIP AC Sense Input—Channel A.Analog ac input to sense voltage on the channel A TIP lead.

8 STIPDCaTIP DC Sense Input—Channel A.Analog dc input to sense voltage on the channel A TIP lead.

9 CAPPaSLIC Stabilization Capacitor—Channel A.Capacitor used in low pass filter.

10 CAPMaSLIC Stabilization Capacitor—Channel A.Capacitor used in low pass filter.

11 SVBATaVBAT Sense—Channel A.Input to sense voltage on VBAT.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TIPa

N/C

GPIO2A / SRINGCa

GPIO1a / STIPCa

SRINGDCa

SRINGACa

STIPACa

STIPDCa

CAPPa

CAPMa

SVBATa

SVDC

RSTB

PSCLK

MIS

O

MO

SI

SD

CH

a

SD

CL

a

DC

DR

Va

DC

FF

a

DC

FF

b

DC

DR

Vb

SD

CLb

SD

CH

b

VDDREG

SVBATb

CAPMb

CAPPb

IREF

STIPDCb

STIPACb

SRINGACb

SRINGDCb

GPIO1b / STIPCb

GPIO2b / SRINGCb

VDDA

N/C

TIPb

VB

AT

b

N/CRIN

Gb

N/C

N/C

N/C

N/C

N/C

VR

EF

_BT

VB

AT

a

RIN

Ga

EPAD 2

15

16

17

18 19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

404142

4344454657

5849 474850

VD

DD

EPAD 1

Si32266/7/8/9

Rev. 1.2 37

12 SVDCDC-DC Input Voltage Sensor.Senses VDC input to dc-dc converters.

13 RSTReset Input.Active low input. Hardware reset used to place all control registers in the default state.

14 PSCLKISI Clock Input.Clock input for ISI bus timing.

15 MISOISI Data Output.Output data to ISI.

16 MOSIISI Data Input.Input data from ISI.

17 SDCHaDC Monitor—Channel A.DC-DC converter monitor input used to detect overcurrent situations in the converter.

18 SDCLaDC Monitor—Channel A.DC-DC converter monitor input used to detect overcurrent situations in the converter.

19 DCDRVaDC Drive—Channel A.DC-DC converter control signal output which drives external transistor.

20 DCFFaDC Flexible Function—Channel A.DC-DC controller flexible function I/O—channel A.

21 DCFFbDC Flexible Function—Channel B.DC-DC controller flexible function I/O—channel B.

22 DCDRVbDC Drive—Channel B.DC-DC converter control signal output which drives external transistor.

23 SDCLbDC Monitor—Channel B.DC-DC converter monitor input used to detect overcurrent situations in the converter.

24 SDCHbDC Monitor—Channel B.DC-DC converter monitor input used to detect overcurrent situations in the converter.

25 VDDDIC Voltage Supply.Digital power supply for internal digital circuitry.

26 VDDREG Regulated Core Power Supply.

27 SVBATbVBAT Sense—Channel B.Input to sense voltage on VBAT.

28 CAPMbSLIC Stabilization Capacitor—Channel B.Capacitor used in low pass filter.

29 CAPPbSLIC Stabilization Capacitor—Channel B.Capacitor used in low pass filter.

30 IREFCurrent Reference Input.Connects to an external resistor used to provide a high accuracy reference current.

31 STIPDCbTIP DC Sense Input—Channel B.Analog dc input to detect voltage on the channel B TIP lead.


Si32266/7/8/9

38 Rev. 1.2

32 STIPACbTIP AC Sense Input—Channel B.Analog ac input to sense voltage on the channel B TIP lead.

33 SRINGACbRING AC Sense Input—Channel B.Analog ac input to sense voltage on the channel B RING lead.

34 SRINGDCbRING DC Sense Input—Channel B.Analog dc input to sense voltage on the channel B RING lead.

35 GPIO1b/STIPCbGeneral Purpose I/O or TIP Coarse Sense Input—Channel B.TIP channel A voltage sensing outside protection circuit.

36 GPIO2b/SRINGCbGeneral Purpose I/O or RING Coarse Sense Input—Channel B.RING channel A Voltage sensing outside protection circuit.

37 VDDAAnalog Supply Voltage.Analog power supply for internal analog circuitry.


39 TIPbTIP Terminal—Channel B.Connect to the TIP lead of the channel B subscriber loop.


41 RINGbRING Terminal—Channel B.Connect to the RING lead of the channel B subscriber loop.


43 VBATbBattery Voltage Supply—Channel B.Connect to battery supply for Channel B.


45 VREF_BTProtection Reference Voltage.Provides a reference trigger voltage for battery tracking protection.

46 N/C No Connect.

47 VBATaBattery Voltage Supply—Channel A.Connect to battery supply for Channel A.


49 RINGaRING Terminal—Channel A.Connect to the RING lead of the channel A subscriber loop.


ep2 EPAD2Exposed paddle.Connect to ground.

ep1 EPAD1Exposed paddle.Connect to electrically-isolated low thermal impedance inner layer and/or backside thermal plane using multiple thermal vias.


Si32266/7/8/9

Rev. 1.2 39

7.2. Si32268/9 Pin Assignments


1 RINGaRing Terminal—Channel A.Connect to the RING lead of the channel A subscriber loop.


3 TIPaTIP Terminal—Channel A.Connect to the TIP lead of the channel A subscriber loop.


5 GPIO2a/SRINGCaGeneral Purpose I/O or RING Coarse Sense Input—Channel A.RING channel A Voltage sensing outside protection circuit.

6 GPIO1a/STIPCaGeneral Purpose I/O or TIP Coarse Sense Input—Channel A.TIP channel A voltage sensing outside protection circuit.

7 SRINGDCaRING DC Sense Input—Channel A.Analog dc input to sense voltage on the channel A RING lead.

8 SRINGACaRING AC Sense Input—Channel A.Analog ac input to sense voltage on the channel A RING lead.

9 STIPACaTIP AC Sense Input—Channel A.Analog ac input to sense voltage on the channel A TIP lead.

10 STIPDCaTIP DC Sense Input—Channel A.Analog dc input to sense voltage on the channel A TIP lead.

11 CAPPaSLIC Stabilization Capacitor—Channel A.Capacitor used in low pass filter.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

RINGa

N/C

TIPa

GPIO2a / SRINGCa

GPIO1a / STIPCa

SRINGDCa

STIPACa

STIPDCa

CAPPa

CAPMa

SVBATa

SVDC

RS

TB

PS

CLK

MIS

O

MO

SI

DC

FF

a

DC

FF

b

DC

DR

Vb

SD

CLb

SD

CH

b

VD

DR

EG

SVBATb

CAPMb

CAPPb

IREF

STIPDCb

STIPACb

SRINGACb

SRINGDCb

GPIO1b / STIPCb

GPIO2b / SRINGCb

VDDA

N/C

TIPb

VB

AT

b

N/C

RIN

Gb

N/C

N/C

N/C

N/C

BA

SE

a

VB

AT

a

BA

SE

b

EPAD 2

15 16 17 18 19

20 21 22 23 24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

404142

4344454657

5849 474850

VD

DD

N/C

SRINGACa

N/C

BA

T_P

O

EPAD 1

Si32266/7/8/9

40 Rev. 1.2

12 CAPMaSLIC Stabilization Capacitor—Channel A.Capacitor used in low pass filter.

13 SVBATaVBAT Sense—Channel A.Input to sense voltage on VBAT.

14 SVDCDC-DC Input Voltage Sensor.Senses VDC input to dc-dc converters.

15 RSTBReset Input.Active low input. Hardware reset used to place all control registers in the default state.

16 PSCLKISI Clock Input.Clock input for ISI timing.

17 MISOISI Data Output.Output data to ISI.

18 MOSIISI Data Input.Input data from ISI.

19 DCFFaDC Flexible Function—Channel A.DC-DC controller flexible function I/O—channel A.

20 DCFFbDC Flexible Function—Channel B.DC-DC controller flexible function I/O—channel B.

21 DCDRVbDC Drive—Channel B.DC-DC converter control signal output which drives external transistor.

22 SDCLbDC Monitor—Channel B.DC-DC converter monitor input used to detect overcurrent situations in the converter.

23 SDCHbDC Monitor—Channel B.DC-DC converter monitor input used to detect overcurrent situations in the converter.

24 VDDDIC Voltage Supply.Digital power supply for internal digital circuitry.

25 VDDREG Regulated Core Power Supply.

26 SVBATbVBAT Sense—Channel B.Input to sense voltage on VBAT.

27 CAPMbSLIC Stabilization Capacitor—Channel B.Capacitor used in low pass filter.

28 CAPPbSLIC Stabilization Capacitor—Channel B.Capacitor used in low pass filter.

29 IREFCurrent Reference Input.Connects to an external resistor used to provide a high accuracy reference current.

30 STIPDCbTIP DC Sense Input—Channel B.Analog dc input to detect voltage on the channel B TIP lead.

31 STIPACbTIP AC Sense Input—Channel B.Analog ac input to sense voltage on the channel B TIP lead.

32 SRINGACbRING AC Sense Input—Channel B.Analog ac input to sense voltage on the channel B RING lead.


Si32266/7/8/9

Rev. 1.2 41

33 SRINGDCbRING DC Sense Input—Channel B.Analog dc input to sense voltage on the channel B RING lead.

34 GPIO1b / STIPCbGeneral Purpose I/O or TIP Coarse Sense Input—Channel B.TIP channel A voltage sensing outside protection circuit.

35GPIO2b / SRI-

NGCbGeneral Purpose I/O or RING Coarse Sense Input—Channel B.RING channel A Voltage sensing outside protection circuit.

36 VDDAAnalog Supply Voltage.Analog power supply for internal analog circuitry.


38 TIPbTIP Terminal—Channel B.Connect to the TIP lead of the channel B subscriber loop.


40 RINGbRING Terminal—Channel B.Connect to the RING lead of the channel B subscriber loop.


42 VBATbBattery Voltage Supply—Channel B.Connect to battery supply for Channel B.


44 BASEbOffloading Base Control Output—Channel B.Output to control base of power offloading transistor (fixed rail).


46 BAT_POPower Offloading Battery Voltage Input.Output from fixed rail dc-dc converter.

47 BASEaOffloading Base Control Output—Channel A.Output to control base of power offloading transistor (fixed rail).


49 VBATaBattery Voltage Supply—Channel A.Connect to battery supply for Channel A.


ep2 EPAD2Exposed paddle.Connect to ground.

ep1 EPAD1Exposed paddle.Connect to electrically-isolated low thermal impedance inner layer and/or backside thermal plane using multiple thermal vias.


Si32266/7/8/9

42 Rev. 1.2

8. Ordering Guide

Table 19. Device Ordering Guide1

FXS P/N Description Package Max VBAT Temperature

Si32266-C-FM1 Dual wideband FXS, integrated serial interface, tracking dc-dc

LGA2 –110 V 0 to 70 °C

Si32266-C-GM1 Dual wideband FXS, integrated serial interface, tracking dc-dc

LGA2 –110 V –40 to 85 °C

Si32267-C-FM1 Dual wideband FXS, integrated serial interface, tracking dc-dc

LGA2 –140 V 0 to 70 °C

Si32267-C-GM1 Dual wideband FXS, integrated serial interface, tracking dc-dc

LGA2 –140 V –40 to 85 °C

Si32268-C-FM1 Dual wideband FXS, integrated serial interface, shared dc-dc

LGA2 –110 V 0 to 70 °C

Si32268-C-GM1 Dual wideband FXS, integrated serial interface, shared dc-dc

LGA2 –110 V –40 to 85 °C

Si32269-C-FM1 Dual wideband FXS, integrated serial interface, shared dc-dc

LGA2 –140 V 0 to 70 °C

Si32269-C-GM1 Dual wideband FXS, integrated serial interface, shared dc-dc

LGA2 –140 V –40 to 85 °C

Si32266-C-FM Dual wideband FXS, integrated serial interface, tracking dc-dc

NBA3 –110 V 0 to 70 °C

Si32266-C-GM Dual wideband FXS, integrated serial interface, tracking dc-dc

NBA3 –110 V –40 to 85 °C

Si32267-C-FM Dual wideband FXS, integrated serial interface, tracking dc-dc

NBA3 –140 V 0 to 70 °C

Si32267-C-GM Dual wideband FXS, integrated serial interface, tracking dc-dc

NBA3 –140 V –40 to 85 °C

Si32268-C-FM Dual wideband FXS, integrated serial interface, shared dc-dc

NBA3 –110 V 0 to 70 °C

Si32268-C-GM Dual wideband FXS, integrated serial interface, shared dc-dc

NBA3 –110 V –40 to 85 °C

Si32269-C-FM Dual wideband FXS, integrated serial interface, shared dc-dc

NBA3 –140 V 0 to 70 °C

Si32269-C-GM Dual wideband FXS, integrated serial interface, shared dc-dc

NBA3 –140 V –40 to 85 °C

Notes:1. Adding the suffix "R" to the part number (e.g. Si32268-C-FMR) denotes tape and reel.2. LGA - Land Grid Array.3. NBA - No Ball Array. Not recommended for new designs. This package option must be used only with high Tg PCB

material (> 170 °C) when using Pb-free reflow profiles.

Si32266/7/8/9

Rev. 1.2 43

Table 20. Evaluation Kit Ordering Guide

Part Number Supported ProSLIC

Description VBAT Max

Interface

Si32260PB20SL0-EVB Si322601 PMOS buck boost dc-dc converter EVB

–110 V PCM/SPI to Voice Motherboard

Si32260TS20SL0-EVB Si322602 Tracking Shared Supply (TSS) dc-dc converter EVB


Si32260QC20SL0-EVB Si322601 Low cost quasi-Ćuk (MOSFET/Inductor based) full tracking dc-dc

converter EVB


Si32261FBMB0-EVB Si32260, Si322611

Flyback (transformer based) full tracking dc-dc converter EVB


Si32261QC20SL0-EVB Si32260, Si322611

Quasi-Ćuk (MOSFET/Inductor based) full tracking dc-dc converter

EVB


Si32266PB20SL0-EVB Si32266 ISI PMOS buck boost dc-dc converter EVB

–110 V ISI to SoC with ISI

Si32268TS20SL1-EVB Si32268 Fully isolated ISI Tracking SharedSupply (TSS) dc-dc converter EVB

–100 V ISI to SoC with ISI

Notes:1. Can also be used for software development for Si32266 and Si32267 (only the SoC physical interface is different).2. Can also be used for software development for Si32268 and Si32269 (only the SoC physical interface is different).

Si32266/7/8/9

44 Rev. 1.2

9. Product Identification

The product identification number is a finished goods part number or is specified by a finished goods part number,such as a special customer part number.

Example:

Si32268-C-FM1R

Shipping Option Blank = TraysR = Tape and ReelProduct Revision

Product Designator

Package Type M1 = QFN/LGAM = QFN/NBA

Part Type / Lead Finish F = Commercial / RoHS-CompliantG = Industrial / RoHS-Compliant

Si32266/7/8/9

Rev. 1.2 45

10. Package Outlines

10.1. 50-Pin QFN/LGAFigure 24 illustrates the package details for the Si32266/7/8/9 50-Pin QFN/LGA. Table 22 lists the values for thedimensions shown in the illustration.

Figure 24. 50-Pin (QFN/LGA Package)

Table 21. 50-Pin QFN/LGA Package Diagram Dimensions

Dimension Min Nom Max Dimension Min Nom Max

A 0.74 0.84 0.94 E4 3.55 3.60 3.65

b 0.20 0.25 0.30 L 0.35 0.40 0.45

D 6.00 BSC. L1 0.05 0.10 0.15

D2 4.55 4.60 4.65 aaa — — 0.15

e 0.50 BSC. bbb — — 0.15

E 8.00 BSC. ccc — — 0.10

E2 6.35 6.40 6.45 ddd — — 0.10

E3 2.25 2.30 2.35

Notes:1. All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si32266/7/8/9

46 Rev. 1.2

10.2. 50-Pin QFN/NBAFigure 25 illustrates the package details for the Si32266/7/8/9 50-Pin QFN/NBA. Table 22 lists the values for thedimensions shown in the illustration.

Figure 25. 50-Pin (QFN/NBA Package)

Table 22. 50-Pin QFN/NBA Package Diagram Dimensions

Dimension Min Nom Max Dimension Min Nom Max

A 0.60 0.65 0.70 E4 3.55 3.60 3.65

b 0.20 0.25 0.30 L 0.35 0.40 0.45

D 6.00 BSC. L1 0.05 0.10 0.15

D2 4.55 4.60 4.65 aaa — — 0.15

e 0.50 BSC. bbb — — 0.15

E 8.00 BSC. ccc — — 0.10

E2 6.35 6.40 6.45 ddd — — 0.10

E3 2.25 2.30 2.35

Notes:1. All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si32266/7/8/9

Rev. 1.2 47

11. PCB Land Pattern: LGA and NBA Packages

11.1. Land Pattern and Solder Mask Design

Dimension mm

C1 6.00

C2 8.00

E 0.50

X1 0.30

X2 4.60

Y1 0.80

Y2 2.30

Y3 3.60

Y4 6.40

Notes:General

1. All dimensions shown are in millimeters (mm).2. This Land Pattern Design is based on the IPC-7351 guidelines.3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition

(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad.

Si32266/7/8/9

48 Rev. 1.2

11.2. Thermal Via Layout

Dimension Min Max

d 1.00 —

Kx — 3.2

Ky — 5.2

Notes:1. High-Tg PCB materials (Tg ≥ 170 °C) are recommended for Pb-Free reflow profiles, per

standard industry practice. This is required for reliable board assembly when using the NBA package.

2. The customer’s PCB design must provide sufficient thermal dissipation for high power operation of the device. See layout guidelines in Applications Note AN381 for further details.

3. A minimum of eight thermal vias are required in each center pad. The recommended via diameter is 0.20 - 0.30 mm (8 - 12 mils).

4. Thermal vias placed in the center pads must have a minimum spacing of 1.0 mm from the edge of the via to the closest pin pad metal (d ≥ 1.0 mm).

5. Vias may be placed as desired within the non-hatched area of the center pads. 6. Vias placed within the center pad areas must be either filled or tented on the top side of the

board to prevent solder thieving from under the device.

Si32266/7/8/9

Rev. 1.2 49

11.3. Stencil Aperture Design

Dimension mm

E 0.50

P1 2.30

P2 2.05

P3 1.80

P4 4.35

X1 0.30

X2 1.85

X3 1.90

Y1 0.80

Y2 1.85

Y3 1.40

Notes:Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).Card Assembly

3. A No-Clean, Type-3 solder paste is recommended.4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.5. Reflow profile measured at device should be > 245 °C for 20s minimum.

Si32266/7/8/9

50 Rev. 1.2

12. Top Markings

12.1. 50-Pin LGA Top Marking

12.2. 50-Pin LGA Top Marking Explanation

Mark Method: Laser

Font Size: 2.0 Point (2.8 mils)Right-Justified

Line 1 Marking: Device Part Number Si32268-FM1

Line 2 Marking: YY = YearWW = Work Week

Assigned by the Assembly House. Corresponds to the year and work week of the assembly release.

TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.

Line 3 Marking: Circle = 0.75 mm DiameterLower Left-Justified

Pin 1 Identifier

Circle = 1.3 mm DiameterCenter-Justified

“e4” Pb-Free Symbol

Country of OriginISO Code Abbreviation

KR

Si32266/7/8/9

Rev. 1.2 51

12.3. 50-Pin NBA Top Marking

12.4. 50-Pin NBA Top Marking Explanation

Mark Method: Laser

Font Size: 2.0 Point (2.8 mils)Right-Justified

Line 1 Marking: Device Part Number Si32266-FM

Line 2 Marking: YY = YearWW = Work Week

Assigned by the Assembly House. Corresponds to the year and work week of the assembly release.

TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.

Line 3 Marking: Circle = 0.75 mm DiameterLower Left-Justified

Pin 1 Identifier

Circle = 1.3 mm DiameterCenter-Justified

“e4” Pb-Free Symbol

Country of OriginISO Code Abbreviation

TW

Si32266/7/8/9

52 Rev. 1.2

NOTES:

Si32266/7/8/9

Rev. 1.2 53

DOCUMENT CHANGE LIST:

Revision 0.3 to Revision 1.0 Added Thermal resistance and continuous power

dissipation values.

Updated the protection schematics for the TSS dc-dc converter application. Pins "A" of the TISP61089BDR are now connected to GROUND, and the pin labeled "G" (the GATE) is now connected to VBAT.

Updated order of data sheet elements in accordance with new style guide SOPs.

Cosmetic updates to schematics and BOMs

Changed test load impedance to 2.2 k (was listed as 5.3 k or 600 ).

Added RST leakage current specs.

Increased absolute maximum VBAT, TIP, and RING voltages to –142 V (was –140 V).

Added absolute maximum positive voltage specs for TIP and RING of +0.4 V.

Revision 1.0 to Revision 1.1 Added LGA package information.

Revision 1.1 to Revision 1.2 Added ISI and removed PCM/SPI interfaces from

feature list.

Corrected block diagram to remove PCLK

Corrected title of Figure 2 to be "ISI timing diagram" (not SPI)

Added ISI boards to EVB ordering guide

Added note that NBA packages are not recommended for new designs

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DisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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SINGLE HIP UAL PROSLIC WITH INTEGRATED SERIAL … · Rev. 1.2 5 1. Electrical Specifications Table...

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