Single-Electron Transistor INTERRA PPT

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Single-electron Transistor By ARKA DUTTA ECE HERITAGE INSTITUTE OF TECHNOLOGY , KOLKATA [email protected]

description

By ARKA [email protected] HERITAGE INSTITUTE OF TECHNOLOGY , KOLKATAWHY NANOTECH DEVICES ?‡ Moore's law : describes that the number of transistors thatcan be placed inexpensively on an integrated circuit has doubled approximately every two years. ‡ Nanotech Devices: Invented to solve the problem of downsizing NEED AND PROBLEMS: Power consumption challenges high performance and high density chip design Faster and more information processing resulting in generating more he

Transcript of Single-Electron Transistor INTERRA PPT

Page 1: Single-Electron Transistor INTERRA PPT

Single-electron Transistor By

ARKA DUTTA

ECEHERITAGE INSTITUTE OF

TECHNOLOGY , KOLKATA

[email protected]

Page 2: Single-Electron Transistor INTERRA PPT

• Moore's law : describes that the number of transistors that can be placed inexpensively on an integrated circuit has doubled approximately every two years. • Nanotech Devices: Invented to solve the problem of downsizing

NEED AND PROBLEMS:Power consumption challengeshigh performance and high density chip designFaster and more information processing resulting in generating more heat flux

SOLUTION:Reduce the corresponding charge per bit!! THUS

Single-electron Device!!!

WHY NANOTECH DEVICES ?

Page 3: Single-Electron Transistor INTERRA PPT

Single-electron transistor (SET)

Architecture

Equivalent circuit

gate

C

g

V

g

V

b

Source

Drain

Tunnel junctionsisl

and C

1

C

2

+q1

-q1

+q2

-q2

q

V

2

V

1

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Operation principleCoulomb blockade Quantum mechanical Single

electron tunneling

0 < V < Vmin Vmin< V < 2Vmin single-electron tunnelingI = Imin

2Vmin< V < 3VminThe event of double single-electron tunnelingI = 2Imin

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Thank You!Any

questions?