SINAN SABAH MAHMOODpsasir.upm.edu.my/id/eprint/67896/1/FK 2018 29 IR.pdf · dalam lima struktur...

UNIVERSITI PUTRA MALAYSIA

SNEAK PATH CURRENT TOLERANT RESISTIVE CROSSBAR ARRAY STRUCTURES BASED ON SELF-RECTIFYING MEMRISTOR MODEL

FOR MEMORY APPLICATIONS

SINAN SABAH MAHMOOD

FK 2018 29

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SNEAK PATH CURRENT TOLERANT RESISTIVE CROSSBAR ARRAY

STRUCTURES BASED ON SELF-RECTIFYING MEMRISTOR MODEL


By

SINAN SABAH MAHMOOD

Thesis Submitted to the School of Graduate Studies, Universiti Putra Malaysia,

in Fulfillment of the Requirements for the Degree of Doctor of Philosophy

December 2017

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COPYRIGHT

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Commercial use of materials may only be made with a prior written permission of

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DEDICATION

My beloved wife for her endless love and support

My daughter and son for their innocent smile and bright faces that motivates me

My father and mother for their encourage words throughout my entire life

My brother, my sisters, and their families for their well-wishes during my study

Special Thanks to my supervisor, my friends, my home country, Iraq, and my second

country, Malaysia

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Abstract of thesis presented to the Senate of Universiti Putra Malaysia in fulfillment

of the requirement for the degree of Doctor of Philosophy

SNEAK PATH CURRENT TOLERANT RESISTIVE CROSSBAR ARRAY

STRUCTURES BASED ON SELF-RECTIFYING MEMRISTOR MODEL


By

SINAN SABAH MAHMOOD

December 2017

Chairman : Nasri Bin Sulaiman, PhD

Faculty : Engineering

The demands for continuous miniaturization of electronic devices and circuits have

kept on increasing to fulfill consumer needs. However, today’s conventional

technologies are facing major challenges related to scaling and design issues.

Nanoscale memristive devices are one of the promising futuristic technologies that

are compatible with CMOS process and fit several potential applications. Inspired by

its non-volatility feature, the memristor is used as a memory cell in crossbar array

structures. Despite their high density and less complexity, memristive crossbar

memory arrays face a major problem related to the sneak current flowing through the

pathways of the unselected memory cells. This is referred as sneak path current

problem that causes faulty memory read and write operations and ultimately limits

the memory size. The aim of this thesis is to present a method to alleviate the sneak

path current based on modified crossbar structures with self-rectifying memristive

devices. On one hand, memristors featuring self-rectification characteristic would

suppress the sneak current when reverse biased. Whereas modifying the structure of

crossbar array by introducing insulating crosspoints would further enhance the

system performance To achieve the thesis objectives, a unique self-rectifying

memristor model is proposed. The proposed model is developed according to the

behavior of the self-rectifying memristors and it is adequately adaptive to fit

different experimental data and other memristor models. Subsequently, a device-

level memristor model is implemented in Verilog-A and embedded as a memory cell

in five different crossbar structures. Circuit-level memristive crossbar arrays are

developed and simulated using Cadence Virtuoso. Defining a set of figures of merit

in relation to the sneak current problem, the performance of the memristive crossbar

arrays is evaluated while considering worst case read and write scenarios with

different parameter variations. Thesis results show that the proposed memristor

model properly describes the self-rectification behavior of a-Si memristors and can

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be used by leading circuit simulators for testing memristor applications. In addition,

the results prove the concept of using self-rectifying memristors as memory device

that can intrinsically suppress the sneak path current in selector-less memristive

crossbar arrays. The results of the proposed SRM-based column and row array

structure summarized as follows; during read operation, the maximum achievable

normalized voltage margin is 97.94% for grounded terminals scheme and the

minimum consumed power is 62.2nW for floating terminals scheme. During write

operation, the minimum word line current is 7.61pA for floating terminals scheme

while the minimum consumed power is 15.2pW.

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Abstrak tesis yang dikemukakan kepada Senat Universiti Putra Malaysia sebagai

memenuhi keperluan untuk ijazah Doktor Falsafah

STRUKTUR SUSUNAN PALANG RINTANGAN TAHAN ARUS LALUAN

SUSUPAN BERDASARKAN MODEL MEMRISTOR PENERUS KENDIRI

UNTUK APLIKASI MEMORI

Oleh

SINAN SABAH MAHMOOD

Disember 2017

Pengerusi : Nasri Bin Sulaiman, PhD

Fakulti : Kejuruteraan

Permintaan yang berterusan untuk pengecilan alat dan litar elektronik terus

meningkat bagi memenuhi keperluan pengguna. Walau bagaimanapun, teknologi

konvensional hari ini menghadapi cabaran besar dalam isu penskalaan dan reka

bentuk. Peranti memristif nanoskala adalah salah satu teknologi futuristik yang

menggalakkan serta serasi dengan proses CMOS dan mempunyai beberapa aplikasi

yang berpotensi. Memandangkan cirinya yang tidak meruap, memristor digunakan

sebagai sel memori dalam struktur susunan palang. Walaupun ketumpatannya tinggi

dan kurang rumit, susunan memori palang memristif menghadapi masalah besar

yang berkaitan dengan aliran arus susupan melalui laluan sel memori tidak terpilih.

Ini dirujuk sebagai masalah arus laluan susupan yang menyebabkan kesilapan

memori dalam operasi membaca dan menulis dan akhirnya mengehadkan saiz

memori. Tujuan tesis ini adalah untuk mengemukakan kaedah bagi mengatasi arus

laluan susupan berdasarkan struktur palang yang diubahsuai dengan peranti

memristif rektifikasi kendiri. Di satu pihak, memristor yang mempunyai ciri

rektifikasi kendiri akan menyekat arus susupan apabila terpincang mundur.

Manakala mengubah suai struktur susunan palang dengan menggunakan penebat

persilangan akan meningkatkan prestasi sistem. Untuk mencapai matlamat tesis,

model memristor rektifikasi kendiri yang unik dicadangkan. Model yang

dicadangkan dibangunkan mengikut tingkah laku memristor rektifikasi kendiri dan ia

dapat menyesuaikan diri secukupnya agar sesuai dengan data eksperimen yang

berbeza-beza dan dengan model memristor yang lain. Seterusnya, model memristor

peringkat peranti dilaksanakan dalam Verilog-A dan terbenam sebagai sel memori

dalam lima struktur palang yang berlainan. Susunan palang memristif peringkat litar

dibangunkan dan disimulasikan menggunakan Cadence Virtuoso. Dengan

menetapkan satu set angka merit tentang masalah arus susupan, prestasi susunan

palang memristif dinilai dan pada masa yang sama mempertimbangkan kes paling

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buruk senario membaca dan menulis dengan pelbagai parameter yang berbeza.

Dapatan tesis menunjukkan bahawa model memristor yang dicadangkan

menerangkan dengan sempurna tingkah laku rektifikasi kendiri satu memristor Si

dan boleh digunakan oleh simulator litar utama untuk menguji aplikasi memristor.

Di samping itu, pencapaian ini membuktikan konsep penggunaan memristor

rektifikasi kendiri sebagai peranti memori secara intrinsik boleh mengatasi arus

laluan susupan dalam susunan palang memrisif tiada pemilih. Hasil daripada lajur

berasaskan SRM dan struktur susunan baris yang dicadangkan dapat diringkaskan

seperti berikut; semasa operasi membaca ingatan, voltan margin ternormal yang

boleh dicapai secara maksimum adalah 97.94% untuk skema terminal terbumi dan

kuasa minimum yang digunakan ialah 62.2nW untuk skema terminal terapung.

Semasa operasi menulis ingatan, arus baris perkataan minimum adalah 7.61pA untuk

skim terminal terapung manakala kuasa minimum yang digunakan adalah 15.2pW.

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ACKNOWLEDGEMENTS

First and foremost, Alhamdulillah, all thanks and praise is due to the most gracious

Allah for giving me the required good health, guidance, spiritual comfort, and

faithfulness throughout my research journey.

I would like to thank my senior supervisor, Dr. Nasri Bin Sulaiman, for his

invaluable time and relentless effort in guiding me during the time required to finish

my Ph.D. research and dissertation. He has been a wise and excellent mentor who

teaches how to define and solve an engineering problem and provides advices and

suggestions at the right time. With his knowledge, encouragement, and friendship

towards me, he continuously directed me in producing high quality work.

I would also like to express my appreciation to the supervisory committee member

Dr. Nor Hisham Bin Hamid for his inspiring discussions that helped me to learn how

to think critically and in innovative way. He always managed to free some of his

busy time and effort to improve the research and advise me to the right direction.

A special thanks to the other members of my supervisory committee, Dr. Mohd

Nizar Hamidon and Dr. Nurul Amziah Md. Yunus for their suggestions, comments

and additional support during my research period.

My thanks also goes to the staff members of Universiti Putra Malaysia who offered

to help me continuously. In addition I would like to thank my colleagues and friends

at the faculty of Engineering, University of Baghdad for giving me the chance to

study abroad and sponsoring my research.

Finally, I would like to introduce my sincere gratitude to all my family members .

My wife, son, and daughter with whom life would be relentless in Malaysia without

their inspiration and encouragement. My father and mother who always have been so

ambitious about the success of my career.

Thank you every one who assisted me in every step of my education for your

contributions. I would like to admit that this thesis would not be possible without

your support.

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This thesis was submitted to the Senate of Universiti Putra Malaysia and has been

accepted as fulfillment of the requirement for the degree of Doctor of Philosophy.

The members of the Supervisory Committee were as follows:

Nasri Bin Sulaiman, PhD

Senior Lecturer

Faculty of Engineering

Universiti Putra Malaysia

(Chairman)

Nurul Amziah Md. Yunus, PhD

Associate Professor



(Member)

Mohd Nizar Hamidon, PhD

Associate Professor



(Member)

Nor Hisham Bin Hamid, PhD

Associate Professor


Universiti Teknologi PETRONAS

(Member)

ROBIAH BINTI YUNUS, PhD

Professor and Dean

School of Graduate Studies


Date:

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Declaration by graduate student

I hereby confirm that:

this thesis is my original work;

quotations, illustrations, and citations have been duly referenced;

this thesis has not been submitted previously or concurrently for any other degree

at any other institutions;

intellectual property from the thesis and copyright of thesis are fully-owned by

Universiti Putra Malaysia, as according to the Universiti Putra Malaysia

(Research) Rules 2012;

written permission must be obtained from supervisor and the office of Deputy

Vice-Chancellor (Research and Innovation) before thesis is published (in the

form of written, printed or in electronic form) including books, journals, mod-

ules, proceedings, popular writings, seminar papers, manuscripts, posters,

reports, lecture notes, learning modules or any other materials as stated in the

Universiti Putra Malaysia (Research) Rules 2012;

there is no plagiarism or data falsification/fabrication in the thesis, and scholarly

integrity is upheld as according to the Universiti Putra Malaysia (Graduate

Studies) Rules 2003 (Revision 2012-2013) and the Universiti Putra Malaysia

(Research) Rules 2012. The thesis has undergone plagiarism detection software.

Signature: _______________________ Date: _____________________

Name and Matric No.: Sinan Sabah Mahmood, GS39251

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Declaration by the Members of Supervisory Committee

This is to certify that:

the research conducted and the writing of the thesis was under our supervision;

supervision of responsibilities as slated in the Universiti Putra Malaysia

(Graduate studies) Rules 2003 (Revision 2012-2013) were adhered to.

Signature:

Name of

Chairman of

Supervisory

Committee:

Dr. Nasri Bin Sulaiman

Signature:

Name of

Member of

Supervisory

Committee:

Associate Professor Dr. Nurul Amziah Md. Yunus

Signature:

Name of

Member of

Supervisory

Committee:

Associate Professor Dr. Mohd Nizar Hamidon

Signature:

Name of

Member of

Supervisory

Committee:

Associate Professor Dr. Nor Hisham Bin Hamid

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TABLE OF CONTENTS

Page

ABSTRACT i

ABSTRAK iii

ACKNOWLEDGEMENTS v

APPROVAL vi

DECLARATION viii

LIST OF TABLES xiii

LIST OF FIGURES xv

LIST OF ABBREVIATIONS xxiv

CHAPTER

1 INTRODUCTION 1 1.1 Background 1 1.2 Introduction to Memristors 1 1.3 Problem Statement 6

4.1 Knowledge Gap in the Field of Study 8 1.5 Aim and Objectives 8

1.6 Research Questions 9 1.7 Thesis Contributions 10 1.8 Scope of the Thesis 11 1.9 Organization of the Thesis 11

2 LITERATURE REVIEW 13 2.1 Origins of the Memristor 13

2.2 The HP Memristor 17 2.3 Memristor Models 19

2.3.1 Linear Ion Drift Model 19 2.3.2 Window Functions 21

2.3.3 Nonlinear Ion Drift Model 25 2.3.4 Simmons Tunneling Barrier Model 25

2.3.5 Threshold Adaptive Memristor (TEAM) Model 26 2.3.6 Yakopcic Model 28 2.3.7 Self-Rectifying Memristor Model 30

2.4 Potential Memristor Applications 34 2.4.1 Analog Applications 34

2.4.2 Digital Applications 36

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2.5 Memristive Crossbar Arrays 38 2.5.1 Defective Devices 39 2.5.2 Sneak Path Current 41 2.5.3 Crossbar Line Resistance 44

2.6 Proposed Solutions for Sneak Path Problem 46 2.6.1 Write Operation 46 2.6.2 Read Operation 48

2.6.2.1 Bias Schemes 48 2.6.2.2 Selector Devices 49 2.6.2.3 Memristor’s Nonlinearity 56 2.6.2.4 Self-Rectifying Memristive Device 57 2.6.2.5 Complementary Resistive Switch 59

2.6.2.6 Modified Read Operation 60 2.6.2.7 Crossbar Array Structure Modification 62

2.7 Summary 66

3 RESEARCH METHODOLOGY 71 3.1 Research Methodology 71 3.2 Self-Rectifying Memristor Model 73

3.2.1 State Variable Derivative Equation 74 3.2.2 Current-Voltage Relationship 79 3.2.3 Model Validation 80

3.2.3.1 Memristor Fingerprints 81

3.2.3.2 Fitting the proposed SRM Model to Experimental

Data 82 3.2.3.3 Fitting and Comparison of the proposed SRM

model with existing model 83 3.2.4 Device-Level SRM Model For Circuit Simulators 88 3.2.5 Device Schematic 89

3.3 Development of Memristive Crossbar Array 90 3.3.1 Developing Crossbar Array Structures 92 3.3.2 Integration of Memristive Device In Crossbar Structure 93

3.4 Simulation and Evaluation of the Self-rectifying Memristive

Crossbar Array 95 3.4.1 Memory Read Operation Process 95

3.4.2 Memory Write Operation Process 98 3.5 Performance Benchmarking 102 3.6 Summary 105

4 SIMULATION RESULTS, BENCHMARKING, AND

DISCUSSION 106 4.1 Memory Read Operation Performance 106

4.1.1 Crossbar Characteristics Variation 107 4.1.1.1 Array Size, Structure, and Biasing Scheme 108 4.1.1.2 Interconnect Resistance Dependence 113

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4.1.2 SRM Parameters Variation 117 4.1.2.1 Read Voltage Margin 117 4.1.2.2 Power Consumption 123

4.2 Memory Write Operation Performance 128 4.2.1 Write Disturbance Analysis 129

4.2.1.1 Array Size and Structure 129 4.2.1.2 Interconnect Resistance Dependence 131 4.2.1.3 SRM Parameters Variation 131

4.2.2 Write Failure Analysis 137 4.2.2.1 Array Size and Structure 137 4.2.2.2 Interconnect Resistance Dependence 142 4.2.2.3 SRM Parameters Variation 147

4.3 Comparison and Discussion 163 4.3.1 Memory Read Operation Performance Comparison 163

4.3.1.1 Comparison with Linear Memristor 163 4.3.1.2 Comparison with Full Array Structure 169

4.3.2 Memory Write Operation Performance Comparison 170 4.3.2.1 Comparison with Linear Memristor 171 4.3.2.2 Comparison with Full Array Structure 174

4.4 Validation of Sneak Path Effect Reduction for the Proposed

System 178 4.5 Summary 181

5 CONCLUSION AND FUTURE WORK 182 5.1 Conclusion 182 5.2 Thesis Contributions 183 5.3 Recommendations for Future Work 184

REFERENCES 186

APPENDICES 202 BIODATA OF STUDENT 209

LIST OF PUBLICATIONS 210

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LIST OF TABLES

Table Page

1.1 Functional table of the memristor’s operation. 3

1.2 Device features of common and emerging memory technologies

[14].

6

1.3 Sneak path current effects on the functionality of memristive

array.

8

2.1 Comparison of available window functions. 23

2.2 Comparison of available linear memristive device models

presented in the literature.

33

2.3 Different CBReRAM biasing schemes. 29

2.4 Summary of unipolar ReRAM cell selectors published in the

literature.

52

2.5 Summary of bipolar ReRAM cell selectors published in the

literature.

55

2.6 Summary of sneak path current solutions reviewed in the

literature.

68

3.1 Proposed SRM model parameters fitted to other memristive device

characteristics.

82

3.2 Proposed SRM model parameters fitted to other SRM models. 84

3.3 A comparison between VTEAM model, Gao’s model, and the

proposed SRM model.

887

3.4 Measured metrics representing the performance of the memristive

crossbar array in relation with sneak path current.

100

3.5 Array structure and type of memristor of different references used

in the benchmark.

103

4.1 SRM device and crossbar array parameters used during the read

performance evaluation.

107

4.2 SRM device and crossbar array parameters used during the write 129

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performance evaluation.

4.3 Comparison of Δ\V and power consumption of linear memristor

and SRM-based modified crossbar array structures for read

operation. Array size is 64×64.

167

4.4 Comparison of Δ\V and power consumption of proposed and full

crossbar array structures for read operation. array size is 64×64.

170

4.5 Comparison of Vselected cell of linear memristor and SRM-based

modified crossbar array structures for write operation. Array size

is 64×64. (Higher number is better).

172

4.6 Comparison of Iword of linear memristor and SRM-based modified

crossbar array structures for write operation. Array size is 64×64.

(Lower number is better).

173

4.7 Comparison of power consumption of linear memristor and SRM-

based modified crossbar array structures for write operation. Array

size is 64×64. (Lower number is better).

174

4.8 Comparison of Vunselected cell and Vselected cell of proposed

and full crossbar array structures for write operation. Array size is

64×64.

175

4.9 Comparison of Iword and power consumption of proposed and full

crossbar array structures for write operation. Array size is 64×64.

177

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LIST OF FIGURES

Figure Page

1.1 The memristor. (a) Electrical symbol, and (b) i-v characteristics

showing the pinched hysteresis loop [10].

2

1.2 Memristor’s operation. (a) direction of barrier drift for Vin>0, (b)

direction of barrier drift for Vin<0.

3

1.3 Classification of memristive switches. (a) unipolar, and (b) bipolar

memristive devices.

5

1.4 Classification of memristor behavior. (a) linear memristor, and (b)

self-rectifying memristor.

5

1.5 Sneak path current in a memristive crossbar array structure. 7

1.6 Scope of the thesis research. 11

2.1 Illustration of the interrelation between the four fundamental

circuit variables. A memristor links between the charge (q) and

flux (Ψ).

15

2.2 i-v characteristics of the memristor showing relation of the

pinched hysteresis loop with the input signal frequency.

16

2.3 HP’s TiO2 MIM memristor structure [38]. The magnified part

shows the switching element sandwiched between two Pt

electrodes.

18

2.4 HP’s memristor behavior. (a) when no bias is applied, (b) applying

a positive bias to the top electrode, and (c) applying a negative

bias on the top electrode.

18

2.5 A schematic representation of the HP’s memristor model. 20

2.6 Memristor’s structure in Simmons Tunneling barrier model [48]. 26

2.7 i-v characteristics of a memristor with self-rectifying behavior

[71].

30

2.8 Schematic of memristor-based phase shift oscillator [78]. 34

2.9 Circuit diagram of a memristor-based variable gain amplifier [86].

The memristance is controlled by Vc while Rc provides a voltage

to current control signal.

35

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2.10 Diagrams of memristor-MOSFET amplifier circuits [88]. (a)

Common source amplifier. (b) Common drain amplifier. (c)

Differential amplifier.

35

2.11 Memristive-based IMPLY function [96]. (a) P and Q memristors

are two-state elements that act as either open or closed switches.

(b) IMPLY truth table. (c) IMPLY gate.

36

2.12 NAND memristor implementation [94]. (a) NAND operation

realized by two IMPLY gates. (b) Sequential truth table. (c)

NAND operation realized by three memristors P, Q, and S.

37

2.13 Integration of the memristor in a crossbar structure. 38

2.14 The arrangement of CMOS layer (peripheral circuit) with

memristive crossbar array.

39

2.15 Defects in memristive crossbar architecture [116]. (a) Open (red

color) and bridge (blue color) defects in a crossbar array. (b) Open

(red color) and bridge (blue color) defects in CMOS-to-Nanowire

circuit.

41

2.16 Sneak path current during read operation of CBReRAM. (a) ideal

case with no sneak path current. (b) realistic case with sneak path

current.

42

2.17 Illustration of the voltage margin. 44

2.18 Illustration of the write failure and write disturbance situations. 45

2.19 An m×n CBReRAM schematic. (a) V/2 bias scheme. (b) V/3 bias

scheme. The array can be divided into three groups: selected cell,

unselected cells, and partially selected cells.

47

2.20 Proposed sneak path current solutions based on the literature. 48

2.21 Schematic of CBReRAM with (a) transistor, (b) nonlinear device,

or (c) diode selectors.

50

2.22 1T+1R CBReRAM schematic. 51

2.23 Experimental i-v curve of a bipolar nonlinear selector. The inset

shows an exponential decrement in selector resistance with voltage

increment.

54

2.24 Memristor’s nonlinear i-v characteristics. 56

2.25 The structure of the Ag/a-Si/p-Si self-rectifying memristor. (a)

crosssectional schematic of the device [192]. (b) crossbar array

57

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formed by the same memristor [193].

2.26 Ag/a-Si/p-Si SRM device behavior [192]. (a) i-v characteristics

(inset logarithmic plot of i-v curve). (b) device response to

multiple voltage magnitudes.

58

2.27 A complementary resistive switch. (a) device schematic. (b) i-v

characteristics.

59

2.28 Multiport read operation as proposed in [204]. (a) linking the

crossbar terminals, (b) equivalent circuit, and (c) multiport read

operation.

61

2.29 CBReRAM with load capacitors used for AC sensing. 62

2.30 Unfolded memristive crossbar array structure. 63

2.31 An example of different arrangements of 16-bit crossbar array

with different aspect ratios.

64

2.32 Modified crossbar array structures proposed by Vourkas et al.

[21].

65

3.1 The sequence of research methodology stages. 79

3.2 SRM device model and schematic development process. 75

3.3 Effect of a window function. (a) limiting the bounds of

w∈[woff,won], (b) deceleration of dw/dt at the bound.

79

3.4 Memristor circuit for plotting the i-v response of the proposed

SRM model.

80

3.5 SRM device model i-v response for different input frequencies.

Inset: input voltage with f=1kHz.

81

3.6 Fitting the proposed SRM model to Ag/a-Si/SiGe memristor. (a)

i-v characteristics of the proposed SRM device, (b) i-v

characteristics of Ag/a-Si/SiGe memristor [70]. Inset window is

the applied voltage across the memristor.

83

3.7 Fitting the proposed SRM model to Ag/a-Si/p-Si memristor. (a) i-v

characteristics of the proposed SRM device, (b) i-v characteristics

of Ag/a-Si/p-Si memristor [192]. Inset window is the applied

voltage across the memristor.

83

3.8 Fitting the proposed SRM model to other SRM models. (a) SRM

model fitted to Gao’s model, and (b) i-v characteristics of Gao’s

SRM model [18]. Inset window is a logarithmic plot of i-v curve.

Sinusoidal voltage signal of 2V amplitude and 10MHz frequency

84

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is applied to the memristor’s terminals.

3.9 Flowchart of the proposed SRM device-level model to be

implemented in Verilog-A.

89

3.10 Developing SRM device for Cadence Simulations. (a) creating a

new library (MemristorLibrary), (b) creating device cellview using

the Verilog-A code, (c) SRM device symbol implementation, and

(d) finalized Cadence memristor library.

91

3.11 The arrangement of CBReRAM line resistance and cell

capacitance.

92

3.12 4kbit crossbar array schematic based on SRM device. Referring to

the magnified part, the developed crossbar takes into consideration

the existence of Rwire, Ccouple, and CwtB during simulations.

94

3.13 Illustration of worst case read situation. The selected cell is located

at the furthest corner and the unselected cells are all ON.

98

3.14 Location and state of memory cells for testing (a) write failure

ofselected cell, and (b) write disturbance of unselected cell.

101

3.15 Performance benchmarking of the proposed system. 102

3.16 Linear memristive device model i-v characteristics fitted to the

device introduced in section 3.2. Device parameters are

Roff=500MΩ, Ron=500kΩ, voff=−1.5V, von=1.5V,

koff=20m/sec, kon=17.5x10−3m/sec, aoff=5, aon=1, woff=0nm,

won=10nm.

104

4.1 Δ\V versus crossbar size for different bias schemes and array

structure. (a) column topology, (b) row topology, (c) column and

row topology, (d) rectangular ring topology, and (e) diagonal

distribution topology.

109

4.2 The sneak path current behavior in G-G scheme. (a) Partially

selected word line cells. (b) Partially selected bit line cells. (c)

Unselected cells.

110

4.3 Consumed power versus crossbar size for different bias schemes

and array structure. (a) column topology, (b) row topology, (c)

column and row topology, (d) rectangular ring topology, and (e)

diagonal distribution topology.

112

4.4 Δ\V versus line resistance for different bias schemes and array

structure. (a) column topology, (b) row topology, (c) column and


114

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distribution topology. Array size is 64×64.

4.5 Consumed power versus line resistance for different bias schemes

and array structure. (a) column topology, (b) row topology, (c)


diagonal distribution topology. Array size is 64×64

116

4.6 Δ\V versus Ron for different Roff/Ron. (a) 10, (b) 100, (c) 1000,

(d) 10000. Column topology. Array size is 64×64.

119


(d) 10000. Row topology. Array size is 64×64.

120


(d) 10000. Column and Row topology. Array size is 64×64.

121


(d) 10000. Rectangular Ring topology. Array size is 64×64.

122


(d) 10000. Diagonal Distribution topology. Array size is 64×64.

123

4.11 Power consumption versus Ron for different Roff/Ron. (a) 10, (b)

100, (c) 1000, (d) 10000. Column topology. Array size is 64×64.

124


100, (c) 1000, (d) 10000. Row topology. Array size is 64×64.

125


100, (c) 1000, (d) 10000. Column and Row topology. Array size is

64×64.

126


100, (c) 1000, (d) 10000. Rectangular Ring topology. Array size is

64×64.

127


100, (c) 1000, (d) 10000. Diagonal Distribution topology. Array

size is 64×64.

128

4.16 Unselected cell voltage versus crossbar size for different array

structures. The biasing scheme is F-F.

130

4.17 Unselected cell voltage versus interconnect line resistance for

different array structures. Array size is 64×64 and the biasing

scheme is F-F.

131

4.18 Unselected cell voltage versus Ron for different Roff /Ron ratio.

(a) 10, (b) 100, (c) 1000, (d) 10000. Column topology. CBReRAM

132

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array size is 64×64.


(a) 10, (b) 100, (c) 1000, (d) 10000. Row topology. CBReRAM


133


(a) 10, (b) 100, (c) 1000, (d) 10000. Column and Row topology.

CBReRAM array size is 64×64.

134


(a) 10, (b) 100, (c) 1000, (d) 10000. Rectangular Ring topology.


135


(a) 10, (b) 100, (c) 1000, (d) 10000. Diagonal Distribution

topology. CBReRAM array size is 64×64.

136

4.23 Selected cell voltage versus crossbar array size for different bias

schemes and array structures. (a) column topology, (b) row

topology, (c) column and row topology, (d) rectangular ring

topology, and (e) diagonal distribution topology.

138

4.24 Word line current versus crossbar array size for different bias




140

4.25 Power consumption versus crossbar array size for different bias




141

4.26 Selected cell voltage versus interconnect line resistance for

different bias schemes and array structures. (a) column topology,

(b) row topology, (c) column and row topology, (d) rectangular

ring topology, and (e) diagonal distribution topology. Array size is

64×64.

143

4.27 Word line current versus interconnect line resistance for different

bias schemes and array structures. (a) column topology, (b) row


topology, and (e) diagonal distribution topology. Array size is

64×64.

144

4.28 Power consumption versus interconnect line resistance for

different bias schemes and array structures. (a) column topology,

(b) row topology, (c) column and row topology, (d) rectangular

ring topology, and (e) diagonal distribution topology. Array size is

146

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64×64.

4.29 Selected cell voltage versus Ron for different Roff/Ron ratio. (a)

10, (b) 100, (c) 1000, (d) 10000. Column topology. CBReRAM


148


10, (b) 100, (c) 1000, (d) 10000. Row topology. CBReRAM array

size is 64×64.

149


10, (b) 100, (c) 1000, (d) 10000. Column and Row topology.


150


10, (b) 100, (c) 1000, (d) 10000. Rectangular Ring topology.


151


10, (b) 100, (c) 1000, (d) 10000. Diagonal Distribution topology.


152

4.34 Word line current versus Ron for different Roff/Ron ratio. (a) 10,

(b) 100, (c) 1000, (d) 10000. Column topology. CBReRAM array

size is 64×64.

153


(b) 100, (c) 1000, (d) 10000. Row topology. CBReRAM array size

is 64×64.

154


(b) 100, (c) 1000, (d) 10000. Column and Row topology.


155


(b) 100, (c) 1000, (d) 10000. Rectangular Ring topology.


156


(b) 100, (c) 1000, (d) 10000. Diagonal Distribution topology.


157

4.39 Power consumption versus Ron for different Roff/Ron ratio. (a)

10, (b) 100, (c) 1000, (d) 10000. Column topology. CBReRAM


158


10, (b) 100, (c) 1000, (d) 10000. Row topology. CBReRAM array

159

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size is 64×64.


10, (b) 100, (c) 1000, (d) 10000. Column and Row topology.


160


10, (b) 100, (c) 1000, (d) 10000. Rectangular Ring topology.


161


10, (b) 100, (c) 1000, (d) 10000. Diagonal Distribution topology.


162

4.44 Δ\V versus crossbar size for different bias schemes and array

structures. (a) column topology, (b) row topology, (c) column and


distribution topology. Linear memristive device is used.

165

4.45 Consumed power versus crossbar size for different bias schemes

and array structures. (a) column topology, (b) row topology, (c)


diagonal distribution topology. Linear memristive device is used.

166

4.46 The number of available memory cells (memristors) in different

crossbar structures. Array size is 64×64.

169

4.47 Unselected cell voltage versus crossbar size for different array

structures. Linear memristive device is used. Biasing scheme is F-

F.

171

4.48 Normalized voltage margin of the proposed CBReRAM during

read operation (higher number is better). All array structures are

64×64.

178

4.49 Total array power consumption of the proposed CBReRAM

during read operation (lower number is better). All array structures

are 64×64.

179

4.50 Disturbance voltage window of the proposed CBReRAM during

write operation (higher number is better). All array structures are

64×64.

179

4.51 Disturbance voltage window of the proposed CBReRAM during


64×64.

180

4.52 Word line current window of the proposed CBReRAM during


180

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64×64.

4.53 Power consumption of the proposed CBReRAM during write

operation (lower number is better). All array structures are 64×64.

181

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LIST OF ABBREVIATIONS

ADE Analog Design Environment

ANN Artificial Neural Network

CAD Computer Aided Design

CBReRAM Crossbar Resistive Random Access Memory

CMOS Complementary Metal Oxide Semiconductor

CRS Complementary Resistive Switch

DRAM Dynamic Random Access Memory

EDA Electronic Design Automation

F-F Floating-Floating

G-G Grounded-Grounded

HDL Hardware Description Language

HRS High Resistance State

ITRS International Technology Roadmap for Semiconductors

LRS Low Resistance State

MIM Metal-Insulator-Metal

NVM Nonvolatile Memory

PCRAM Phase Change Random Access Memory

ReRAM Resistive Random Access Memory

SRAM Static Random Access Memory

SRM Self-Rectifying Memristor

STT-RAM Spin Torque Transfer Random Access Memory

TEAM Threshold Adaptive Memristor

VTEAM Voltage Threshold Adaptive Memristor

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CHAPTER 1

1 INTRODUCTION

This chapter provides an introduction to the latest development in emerging

nonvolatile memory, specifically those based on memristive devices. Various analog

and digital applications have been proposed using memristor due to its appealing

characteristics. Then it describes the sneak path problem related to memristor-based

crossbar arrays and how it affects the system performance. Moreover, the chapter

states the aim of the research, objectives to be achieved, and the research questions

to be fulfilled throughout this research. Then, contributions of the thesis and scope of

the research are also presented. Lastly, the chapter summarizes the organization of

the thesis.

1.1 Background

In the 1960s, Gordon Moore predicted that the density of the transistors integrated

into a chip doubles every 18 months that revised later to double every two years [1].

Moore’s Law has been fairly well verified for more than 40 years, yet many

researchers reported that its end is near as the semiconductor integrated circuits are

almost reached their scaling limits, device reliability, and manufacturing costs [2, 3].

On one hand, the current CMOS technology is scarcely scaled to few nanometers

due to the tunnel current increment, difficult gate control, and higher threshold

vacillations [4, 5]. On the other hand, charge-storage based memories (i.e. Dynamic

Random Access Memory and NAND Flash) suffer from a decline of stored charges

and higher transistor leakage current [6]. In addition, the every-day growing use of

portable electronic gadgets and embedded systems is pushing the demands for

diverse types of nonvolatile memory (NVM) with lower power consumption and

higher memory density. As a consequence, the electronic device market is

demanding alternative technologies to satisfy the consumers.

Over the past decade, many research groups and memory manufacturers have

brought to light different emerging memory technologies including phase change

memory (PCRAM), spin-torque-transfer memory (STT-RAM), and resistive

memory (ReRAM) [7, 8]. According to the International Technology Roadmap for

Semiconductors (ITRS), Redox-based (or memristive) memory has been identified

as the leading competitive memory technology among the other candidates [9].

1.2 Introduction to Memristors

The term “memristor” (a contraction of memory-resistor) appeared for the first time

in an article published in 1971 by Leon Chua [10]. A memristor is a two-terminal

passive device capable of varying its electrical resistance (usually nonlinearly) based

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on the magnitude and direction of the applied voltage signal across its terminals.

Furthermore, it can retain its last resistance status for quite long period of time even

if the signal is turned off. The electrical symbol of the memristor and its i-v

characteristics are shown in Figure 1.1. The i-v characteristics represents a pinched

hysteresis loop because, given a voltage value, two different current values can be

obtained, depending on the previous voltage applied across the memristor’s

terminals.

Figure 1.1 : The memristor. (a) Electrical symbol, (b) i-v characteristics

showing the pinched hysteresis loop [10]

However, no experimental evidence of the memristor had been found in the behavior

of any device at that time and the only possible to achieve similar behavior was by

using different active components. Consequently, the scientific communities were

not interested in memristive devices and Chua’s hypothesis was almost abandoned.

It was not until 2008 that a research group in HP laboratories found a way to

fabricate the first memristor using a solid-state thin layer of suitably doped titanium

dioxide [11]. Since then, the breakthrough memristive devices have gained much

interest by many research groups and the number of related publications has

increased dramatically.

Generally, both HP’s memristor and the subsequent memristors were based on

metal-insulator-metal structure, in which the insulator represents the switching

material and the metal serves as electrodes. The insulator layer is divided into two

sublayers, one is highly resistive while the other is highly conductive, as shown in

Figure 1.2. More importantly, the position of the barrier between these two sublayers

can be changed in both directions if a proper bias is applied across the memristor’s

terminals so that the memristor possesses different resistive states. This is due to the

fact that the conductive sublayer has vacancies that can drift freely once biased. In

addition, the barrier holds its last position if the bias goes off. As a result, the

resistance of the memristor is proportional to the ratio of width of the conductive

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sublayer (𝑤) to the total width of the device (D) (i.e. 𝑅𝑚 ∝ 𝑤/𝐷). A functional table

of the basic operation of the memristor is shown in Table 1.1.

Table 1.1 : Functional table of the memristor’s operation

Before going into further detailed description of the memristor, it is important to

define several terms that are commonly used later.

Low Resistance State (LRS): it is the state of the memristor in which the width

of the conductive sublayer equals to the total device width (i.e. 𝑤=D). In this

case, the resistance between device terminals is at its lowest value and the

memristor is said to be ON (i.e. logic “1”).

Figure 1.2 : Memristor’s operation. (a) direction of barrier drift for Vin>0, (b)

direction of barrier drift for Vin<0

Input voltage 𝑤𝑖𝑛𝑖𝑡𝑖𝑎𝑙 𝑤𝑓𝑖𝑛𝑎𝑙 𝑅𝑚 𝑖𝑛𝑖𝑡𝑖𝑎𝑙

𝑅𝑚 𝑓𝑖𝑛𝑎𝑙𝑙

𝑉𝑖𝑛 > 0 0 D high low

𝑉𝑖𝑛 < 0 D 0 low high

𝑉𝑖𝑛 = 0 No change No change

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High Resistance state (HRS): it is the state of the memristor in which the width

of the conductive sublayer equals to the 0. In this case, the resistance between

device terminals is at its highest value and the memristor is said to be OFF (i.e.

logic “0”).

Threshold Voltage (Vth): it is the minimum required voltage to be applied across

the memristor’s terminals in order to change its conductivity. Any memristor has

two different threshold voltages (𝑣𝑜𝑛 and 𝑣𝑜𝑓𝑓) related to its material and

fabrication technology.

Write Operation: it is the process of changing the conductivity state of the

memristor by applying a voltage greater than the threshold voltage. The write

operation is either SET (changing the device conductivity from low to high) or

RESET (changing the device conductivity from high to low).

Read Operation: it is the process of sensing the memristor’s conductivity state

by applying a voltage below the threshold voltage so that the state is unaltered.

Bipolar memristor: it is a memristor that has two threshold voltages (𝑣𝑜𝑛 , 𝑣𝑜𝑓𝑓)

of opposite signs, as shown in Figure 1.3(a). In accordance, a bipolar memristor

requires forward bias (i.e. positive voltage) for SET process and reverse bias (i.e.

negative voltage) for RESET operation. If 𝑣𝑜𝑛 = −𝑣𝑜𝑓𝑓, then the device is said

to be symmetric bipolar memristor. Whereas if 𝑣𝑜𝑛 ≠ −𝑣𝑜𝑓𝑓, then the device is

said to be asymmetric bipolar memristor.

Unipolar Memristor: it is a memristor that has two threshold voltages of the

same sign, as shown in Figure 1.3(b). Therefore, both SET and RESET processes

arise in the positive quadrant of the i-v characteristics.

Linear Memristor: it is the memristor that is able to show either high or low

resistance states (or any state in between) in both positive and negative quadrants

of its i-v characteristics, as shown in Figure 1.4(a).

Self-rectifying Memristor (SRM): it is a special type of memristive devices that

is able to show either high or low resistance state (or any state in between) in the

positive quadrant only (i.e. when forward biased) while it shows only a high

resistance state in the negative quadrant (i.e. when reverse biased), as shown in

Figure 1.4(b).

Since memristors are two-terminal devices with nonvolatile feature, they can be

arranged in crossbar array to minimize congestion. A crossbar array is formed by a

set of thin parallel wires perpendicularly crossing another set of thin wires. The

intersections between any two perpendicular wires are called crosspoints, and in

each crosspoint there is a memristor instead of the usual diode or transistor. The

memristor at each crosspoint is either in a low, a high, or an unknown resistance

state, or it is even possible that the memristor is not there [12].

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Figure 1.3 : Classification of memristive switches. (a) unipolar, and (b) bipolar

memristive devices

Figure 1.4 : Classification of memristor behavior. (a) linear memristor, and (b)

self-rectifying memristor

In comparison with SRAM, memristor-based memory (or simply, ReRAM) has the

advantages of higher cell density, multi-bit storage capability, and nonvolatility.

Furthermore, ReRAM has the additional advantage of being able to be manufactured

in 3-D architecture [13]. In addition, ReRAM is drawing more attention to replace

the NOR FLASH for code storage and NAND FLASH for data storage due to its

lower programming voltage, faster read/write speed, and longer device endurance.

Table 1.2 shows a comparison in terms of device features between the mainstream

and emerging memory technologies.

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Table 1.2 : Device features of common and emerging memory technologies [14]

1.3 Problem Statement

In order to achieve the maximum memory density, memristive memories are

constructed in crossbar arrays [15]. It is considered a most convenient structure to

construct high-density memory systems due to its simple layout.

However, these high-density memristive crossbar arrays suffer from the flow of the

current through undesired (sneak) paths, referred as sneak path current and shown in

Figure 1.5 [16, 17]. On one hand, this problem is a result of the crossbar structure

and resistive nature of memristive devices [18]. On the other hand, it ultimately

degrades array performance in terms of consumed power, limits the memory size,

and increases read/write latency [19].

Particularly, due to the sneak path current in memristive crossbar array structure, the

following problems have been identified throughout this research:

1. In the read operation, while current flows through the memory cell being read, it

also flows through an unknown number of nearby cells. Because of this situation,

the sneak path cells are combined in parallel with the target cell. Consequently, the

output voltage of the read operation will reflect the total resistance caused by the

parallel combination instead of the resistance state of the target cell. Besides higher

Common Memories Emerging Memories

SRAM DRAM FLASH STT-

RAM PCRAM ReRAM

NOR NAND

Single Cell

Area > 100F2 6F2 10F2 < 4 F2 (3D) 6~20F2 4~20 F2

< 4 F2

(3D)

Multi-bit

storage No No Yes (2) Yes (3) No Yes (2) Yes (2)

Programming

Voltage < 1V < 1V > 10V > 10V < 2V < 3V < 3V

Read Latency ~1ns ~10ns ~50ns ~10µs < 10ns < 10ns < 10ns

Write

Latency ~1ns ~10ns 10µs~1ms 100µs~1ms < 5ns ~50ns < 10ns

Data

Retention

Time

N/A ~64ms > 10years > 10years >

10years

>

10years > 10years

Device

Endurance 161> > 116 > 15 > 14 > 115 > 19 > 16~112

Write Energy

(J/bit) ~fJ ~10fJ 100pJ ~10fJ ~0.1pJ ~10pJ ~0.1pJ

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power consumption, the voltage margin between the different resistance states

significantly narrows and leads to a wrong estimation of the stored state [17].

2. In the write operation, the applied voltage across the target cell should be high

enough to change the state (resistance) of the memristor (to avoid write failure).

This leads to the conclusion that the current during a write operation is relatively

higher than the read operation current. The high write current will definitely

produce a higher voltage drop not only across the target cell but also across other

cells. As a result, an unknown number of sneak path cells will be vulnerable to a

change in state by mistake (write disturbance) [20].

Figure 1.5 : Sneak path current in a memristive crossbar array structure

An important feature of the sneak path current is that there exists at least one

memristive cell that encounter reverse biasing. This is inevitable situation due to the

fact that the sneak path current flows in the reverse direction through several

unselected memristors, as shown in Figure 1.5. Based on this feature, the usage of

SRMs as memory cells instead of linear memristors might hold a solution to reduce

the sneak path current besides its memory function. Such practice introduces a

number of high resistance cells (since these cells are reverse biased) that can oppose

the flow of the sneak path current in crossbar structure without using additional cell

selectors. Besides using the SRMs, the crossbar structure itself can be modified by

introducing a number of insulating nodes sorted in different locations in order to

further restrain the flow of the sneak path current. The effect of sneak path current

on the operation of crossbar array is listed in Table 1.3.

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Table 1.3 : Sneak path current effects on the functionality of memristive array

1.4 Knowledge Gap in the Field of Study

The vast majority of the previous work in this area has focused on using memory

cells combined of linear memristors and cell selectors to block the flow of unwanted

sneak path current [17]. To the best of author’s knowledge, there is only a single

study carried out by Gao et al. [18], which focused on engaging SRM model in

crossbar arrays. However, the authors’ attempt to establish a link between SRM and

sneak path current is questionable. First of all, the study has not treated the

memristor model in much details such as fitting to experimental data and compliance

with memristor’s fingerprints. Secondly, the study only focused on the memory read

operation performance while much uncertainty still exists about the memory write

operation performance in arrays with SRMs.

Apart from the above research, Vourkas et al. [21] investigated the impact of

introducing insulating crosspoints within the crossbar to alleviate the sneak path

current. By developing five different crossbar structures, such trend realized

improvement in the sensed voltage. However, the perception of combining SRMs

within these crossbar structures has not been established. This indicates a need to

examine the read/write performance of these structures based on SRM model with

the existence of internal resistive and capacitive loads of the crossbar.

1.5 Aim and Objectives

The aim of this thesis is to design and verify through simulation different memristive

crossbar structures that are able to tolerate the sneak path current. The proposed

solution will realize a functional memory system such that the read voltage margin is

high enough and prevent faulty write process as well. Despite that there are several

solutions proposed to solve this problem, each method has its own limitations.

Without sneak current With sneak current

Total current 𝐼𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟

= 𝑉𝑖𝑛 𝑅𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟⁄

𝐼𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟 + 𝐼𝑠𝑛𝑒𝑎𝑘 𝑝𝑎𝑡ℎ

= 𝑉𝑖𝑛 𝑅𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟⁄ + 𝑉𝑖𝑛 𝑅𝑢𝑛𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟𝑠⁄

Output

voltage

𝑉𝑖𝑛 × 𝑅𝑠𝑒𝑛𝑠𝑒𝑅𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟 + 𝑅𝑠𝑒𝑛𝑠𝑒

𝑉𝑖𝑛 × 𝑅𝑠𝑒𝑛𝑠𝑒

(𝑅𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟//𝑅𝑢𝑛𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟𝑠) + 𝑅𝑠𝑒𝑛𝑠𝑒

Unselected

sneak path

memristor

voltage

0 𝐼𝑠𝑛𝑒𝑎𝑘 𝑝𝑎𝑡ℎ × 𝑅𝑢𝑛𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑 𝑚𝑒𝑚𝑟𝑖𝑠𝑡𝑜𝑟

Consumed

power Low Higher

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Therefore, this research attempts to accomplish the following objectives:

1. To present a mathematical memristor model that complies with the memristor

fingerprints and is able to reproduce the experimental data of actual SRM

devices. This objective is substantial to build a robust memristor model that can

be used in different computer-aided design tools.

2. To develop five schematics of modified crossbar architectures based on inserting

insulating junctions arranged in different pattern. The SRM model developed in

the first objective is integrated within the available memory cell locations of

these architectures, producing modified crossbar arrays based on SRM model.

3. To evaluate and benchmark the performance of the proposed system for memory

application during read and write operations under different device and crossbar

array conditions related to the sneak path current problem.

1.6 Research Questions

The following research questions arise and have not been answered in the literature.

These questions are outlined to be answered throughout this research.

1. How to propose a mathematical model for the SRM device, and how to develop a

memristor device library to be used by different circuit simulators?

2. How to develop a complete crossbar array schematic with the proposed SRM

integrated at every crosspoint?

3. Will the integration of the SRMs in different modified crossbar structures reduce

the sneak path current and improve the performance? How much will be the

improvement?

4. While using different crossbar structures and bias schemes, will these structures

perform similarly in terms of sneak path current?

5. For more accurate evaluation, what is the impact of the line resistance and array

internal capacitance on the performance?

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1.7 Thesis Contributions

In accordance with the methodology stages described above, this research

contributes the followings.

1. Introducing a model for the SRM device.

A model of the SRM is introduced in chapter 3. The proposed model is different

from the existing memristor models in two ways. First, the model replicates the

behavior of memristors with self-rectification feature using a nonlinear state

variable derivative equation, while the other previous models have not dealt with

the rectification behavior of the memristor. Secondly, based on SRM

functionality, the proposed model can suppress the sneak current when reverse

biased in addition to its storage capability without using extra cell selector

devices.

2. Integration of the SRMs into modified crossbar structures.

Combining the superior behavior of the SRM with the modified array structures

realize a further improvement towards solving the sneak path current problem.

Such combination is profitable in many aspects and differs from the others such

that it mixes between two different solutions (i.e. SRM and crossbar structure

modification).

3. Significant improvement in the memristive crossbar array performance

compared to previous works.

It is shown that the proposed circuit outperforms in terms of the voltage margin

and power consumption for both read and write operations in comparison with

the other existing solutions and moving resistive memories further step towards

market production.

4. Incorporating the effect of crossbar array line resistance and capacitance

effects.

The research shows that additional sneak paths and operation latency might come

into picture due to line-to-line coupling capacitance of the array. Previous

researchers assume negligible effects of the capacitive loads. However, for more

realistic results, it is unsuitable to disregard the array’s parasitic capacitance

especially when space between the crossbar lines is just a few nanometers. In

addition, the smaller wire dimension of the array involves higher resistivity that

will disrupt the voltage being delivered to the targeted memory cell so it affects

the overall performance.

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1.8 Scope of the Thesis

Based on the problem statement and proposed solution, the scope of this research is

shown in Figure 1.6. On one hand, the solid red line represents the direction

followed in this thesis to accomplish the objectives. On the other hand, the dotted

lines refer to other research areas that are beyond the scope of this work. The

research scope shows that this thesis is concerned with the SRM modeling and

crossbar array for memory application. The possible link between the SRM and

modified crossbar structures is regarded as a state-of-the-art solution for the sneak

path current problem.

Figure 1.6 : Scope of the thesis research

1.9 Organization of the Thesis

The first chapter presents a brief introduction of the future trends in emerging

memory devices, especially memristor-based memories. Then, statement of the

problem and thesis objectives are established. In addition, research questions and

emerging thesis contributions are demonstrated.

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Chapter 2 presents a comprehensive literature review of memristor models and sneak

path current problem associated with memristive crossbar array memory. It begins

with the exploration of the memristor and the development of different device

models. Then, several applications of the memristor device are reported. Lastly,

memristor crossbar arrays are explained focusing on the sneak path current problem.

Previously proposed solutions are extensively reviewed and compared to identify the

advantages and limitations of each solution.

Chapter 3 presents the research methodology in details. First of all, a SRM model is

proposed while completely describing each development stage to achieve the first

thesis objective. Later, it presents the development of modified crossbar structures

and the integration of memristor device, achieving the second objective. Lastly, the

complete read and write procedures are described and the system performance

metrics to be collected and processed are also defined.

In chapter 4, the developed system is simulated and raw data are collected. After

processing the acquired data, performance metrics are presented for memory read

and write operations individually to achieve the third objective. In addition,

performance benchmarking is accomplished in order to verify the improvement of

the proposed system against other related studies.

In chapter 5, a conclusion of the thesis is introduced, followed by reporting the

contributions of the this research. Lastly, few recommended future research

directions are proposed for further inspection.

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LIST OF PUBLICATIONS

Refereed Journal Articles

S. Sabah, N. B. Sulaiman, N. A. Yunus, M. N. Hamidon, and N. H. Hamid, "Read

operation performance analysis of modified crossbar array structures with self-

rectifying memristive device model," International Journal of Control Theory

and Applications, vol. 9, no. 31, pp. 53-61, 2016.

S. Sabah, N. B. Sulaiman, N. A. Yunus, M. N. Hamidon, and N. H. Hamid, "Sneak

Path Current Analysis of Alternative Crossbar Array Architectures based on

Self-Rectifying Memristive Device Model," IEEE Transactions on Circuits and

Systems I: Regular Papers, (Submitted).

Reviewed Conference Proceedings

S. Sabah, N. B. Sulaiman, N. A. Yunus, M. N. Hamidon, and N. H. Hamid, "Read

operation performance analysis of modified crossbar array structures with self-

rectifying memristive device model," International Conference on Electrical &

Electronic Technology, 2016, Malaysia.

S. Sabah, N. B. Sulaiman, N. A. Yunus, M. N. Hamidon, and N. H. Hamid, "A Self-

Rectifying Memristor Model for Circuit Simulations," IEEE Asia Pacific

Conference on Postgraduate Research in Microelectronics and Electronics

(PrimeAsia), 2017, Malaysia (Submitted).

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