Simultaneous Clock Buffer Sizing and Polarity Assignment for Power/Ground Noise Minimization
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Transcript of Simultaneous Clock Buffer Sizing and Polarity Assignment for Power/Ground Noise Minimization
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Simultaneous Clock Buffer Sizing
and Polarity Assignmentfor Power/Ground Noise
MinimizationHochang Jang, Taewhan Kim
Seoul National University,KoreaDAC’09
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Introduction Previous work Problem formulation Algorithm Experimental results Conclusions
Outline
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The power and ground noise has a crucial effect on the circuit performance, such as the delay of switching signal.◦ 0.1V power noise incurs 79.8% delay variation of an
inverter (Vdd=0.6, Berkeley Predictive Technology 45nm Model)
The clock buffers consume the current at the clock edges => A large amount of current is generated around the clock edges. ◦ The clock buffers be one of the major sources of
power/ground noise.
Introduction
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[3] proposed to schedule the clock arrival times of FFs (flip-flops) in order to disperse the peak current. ([5][6])
[7] first proposed to assign positive polarity onto a half of clock Buffers and negative polarity onto the remaining half of the clock buffers.
Previous work
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Minimizing Peak Current via Opposite Phase Clock Tree[7]
Previous work
Idd
Iss
A
A
Vdd
Vss
Idd
Iss
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Minimizing Peak Current via Opposite Phase Clock Tree[7]
Previous work
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Clock buffer polarity assignment for power noise reduction[8]
Previous work
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Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization[11]
Previous work
Clock routing tree generation
Clock bufferpolarity assignment
Phase 1.
Phase 2.
Min. P/G noise for non-sinksMin. WLSat. skew constraint
Min. P/G noise for sinks
Clock routing tree w/ buffers
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Simultaneous polarity assignment and buffer/ inverter sizing for noise minimization while satisfying the clock skew constraint
Problem formulation
L : set of leaf clock buffering elements B : set of clock buffers in standard cell library I : set of clock inverters in standard cell library κ : skew bound
Find the mapping function φ : L → {B∪I } that minimizes the quantities of
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Algorithm
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Time intervals:◦ H[t-k,t]
Feasible time intervals◦ Each sink has at least one buffer or inverter type to be
assigned such that the resulting earliest and latest arrival times are in this time interval.
Completely feasible: ◦ An arrival time interval is called completely feasible if it is
feasible where each sinks has one buffer and inverter type to be assigned
Algorithm
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Phase 1:Generation of a minimal set of feasible time intervals◦ from right to left, feasible time intervals, until completely-
feasible time interval occurs.
Algorithm
skew bound
arrival time
e1
e2
e3
e36
not feasiblecompletely-feasible
Period of arrival times to FFs clocked by buffer / inverter
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For an interval, sinks are classified into 4 groups:
The interval is called a feasible time interval if G4 is empty
The interval is called a completely feasible time interval if G2, G3,and G4 are all empty.
Algorithm
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Phase 2 : Finding a feasible interval of minimum noise
Algorithm
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Algorithm
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Algorithm
leaf1
leaf2
leaf3
leaf4
leaf5
leaf6
arrival time
skew constraint
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Experimental results
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Experimental results
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19.1% less power noise,16.2% ground noise, and 15.6% less total peak current over that by the conventional method which solved the problem of polarity assignment only.
Future work◦ Need to extend the buffer sizing to the non-sink buffering
elements
Conclusions