Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff...
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![Page 1: Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun.](https://reader030.fdocuments.in/reader030/viewer/2022032522/56649d6b5503460f94a4aa8b/html5/thumbnails/1.jpg)
Simultaneous Buffer Insertion and Wire Sizing Considering
Systematic CMP Variation and Random Leff Variation
Lei He1, Andrew Kahng2,
King Ho Tam1, Jinjun Xiong1
1Univ. of California, Los Angeles2Blaze DFM, Inc. & Univ. of California, San Diego
Sponsors: 1NSF CAREER, SRC, UC MICRO sponsored by Analog Devices, Fujitsu Lab., Intel and LSI Logic, IBM Faculty Partner Award; 2MARCO Gigascale System Research Center, NSF.
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Existing Work on Variation-Aware Buffer Insertion
Buffer insertion for length variation [Khandelwal-ICCAD] Variation sources from difference between
estimated and actual wire length Buffer insertion for process variation [Xiong-
DATE] Random Leff and interconnect width variations Brute-force numerical manipulation of joint
probability density functions (JPDFs), not efficient
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Buffer Insertion and Wire Sizing (SBW) with Process Variations
Variations models Leff – random variation
In reality, 50% systematic and 50% random Interconnect RC – systematic variation due to Chemical
Mechanical Planarization (CMP) Random component of global interconnect variation
on performance is insignificant in general Efficient variation-aware algorithms
Table-based capacitance and fill insertion under CMP Efficient pruning to deal with random variation
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Outline
SBW and fill insertion (SBWF) under CMP variation Modeling RC variation CMP-aware SBW and fill insertion algorithm Experiment: CMP-aware vs CMP-oblivious
Extension to Leff variation Conclusion
![Page 5: Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun.](https://reader030.fdocuments.in/reader030/viewer/2022032522/56649d6b5503460f94a4aa8b/html5/thumbnails/5.jpg)
Chemical Mechanical Planarization (CMP)
Metallization process Etch trenches Deposit Cu bulk Cu removal by CMP
Dishing/Erosion Loss of Cu thickness due
to over-polishing Fix: dummy fill insertion
for more uniform Cu loss Dummy fill insertion
Increase coupling cap
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Chemical Mechanical Planarization (CMP)
Dishing and erosion lead to Up to 31.7% increase in resistance No change in capacitance
Fill insertion [He-SPIE] can lead to 1.5x increase in coupling capacitance (Cc) 2% increase in total capacitance (Cs)
Can be up to 10% increase if fill pattern is not optimized
width (μm) space (μm) R w/CMP Cc w/CMP Cs w/CMP
0.24 0.95 +28.7% +33.1% -0.11%
2.61 0.95 +30.6% +26.3% -1.35%
4.75 0.95 +31.4% +26.5% -0.23%
0.24 1.43 +28.8% +142.7% +1.88%
2.61 1.43 +30.9% +141.8% +0.36%
4.75 1.43 +31.7% +148.8% -0.69%
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Problem Formulation
RAT = 1800ps
C = 18fF
RAT = 1200ps
C = 21fF
RAT = 2500ps
C = 25fF
RAT = 2000ps
C = 10fF
RAT = 900ps
C = 30fFRAT = 1200ps
C = 2fF
RAT = 2000ps
C = 15fF
RAT = 2200ps
C = 8fF
Reff = 100Ω
ρ2
ρ1ρ6
ρ5
ρ4ρ3
RATopt
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CMP-aware RC Parasitics
Optimal (min-Cx) dummy fill pattern insertion Pre-compute dummy fill pattern by enumeration [He-SPIE]
Tabulate both cap and fill pattern, indexed by wire width/space and fill amount
Post-dummy fill dishing/erosion calculation Using Tugbawa-Boning’s model from MIT [Tugbawa-thesis] Input: effective metal density, wire width/space
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SBWF Algorithm
Extended dynamic programming [van Ginneken-ISCS] CMP model is deterministic
Amount of variation calculated from metal features Use CMP-aware RC
Prune sub-optimal/invalid partial solutions Inferior: Cinf > Cn & ATint < ATn
Rise-time violation: Dsubtree > Dbound
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Experiment
Experimental settings ITRS 65nm (interconnect) & BSIM 4 (device) RAT at sinks = 0, Tr < 100ps
SBW + Fill Solving SBW using CMP-oblivious RC, i.e. no
dishing/erosion/fill insertion Risetime constraint set to 83ps during optimization to get
solution that meets the Tr < 100ps constraint Solution to be verified after under CMP-aware RC
SBWF Simultaneous buffering, wire sizing and fill insertion
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Experiment:SBW + Fill vs SBWF
r1 – r5: benchmarks from [Tsay-TCAD]
SBWF improves over SBW + Fill design1. by 1.0% arrival time on average
2. by 5.7% power per switch
SBW + Fill SBWF
net # sinks Src AT (ps)
Power (pJ)
Runtime (s)
Src AT (ps) Power (pJ) Runtime (s)
r1 267 -2437 266 67 -2427 (0.4%) 250 (-6.2%) 86
r2 598 -3080 531 173 -3044 (1.2%) 486 (-8.5%) 193
r3 862 -3684 662 207 -3636 (1.3%) 613 (-7.4%) 257
r4 1903 -5372 1358 389 -5319 (1.0%) 1243 (-8.5%) 459
r5 3101 -6005 2025 512 -5960 (0.7%) 1865 (-7.9%) 727
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Outline
SBW and fill insertion (SBWF) under CMP variation Modeling RC variation CMP-aware SBW and fill insertion algorithm Experiment: CMP-aware vs CMP-oblivious
Extension to Leff variation Conclusion
![Page 13: Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun.](https://reader030.fdocuments.in/reader030/viewer/2022032522/56649d6b5503460f94a4aa8b/html5/thumbnails/13.jpg)
Statistical Buffer Insertion under Random Leff Variation
Leff variation leads to delay variation
Pick the solution with the desired distribution Objective in this work: maximize “required arrival
time” at the source for majority of dies
Delay =
Delay =
Delay = T =
1Cumulative
Probability
RATRAT @ 90%
This portion subject to AT optimization
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Modeling Buffer Delay due to Leff Variation
Buffer characterization by Input capacitance (Cin) insensitive to Leff variation
For total Leff of a buffer at the largest 1% corner, input capacitance only increases by 3%
Output resistance (Reff) and intrinsic delay (Dbuf) sensitive to Leff and their variations are correlated Joint probability density function: PDFR,d(Reff, Dbuf)
Delay with load Lbuf: Dload = Lbuf · Reff + Dbuf
Modeled by cumulative distribution functions (CDFs) CDFd(L)(Dload) =
loadD
effeffbufeffdR dxdRRLxRPDF ,,
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Challenges in Statistical Buffer Insertion Problem
Efficient manipulation of statistical calculation Arrival time as a random variable for optimization
Captured by CDF Calculation is slow by brute-force manipulation
Our approach: piece-wise linear (PWL) modeling Pruning rules to remove sub-optimal options
Deterministic AT1 > AT2 and L1 < L2 – establishes total order
Probabilistic P(AT1 > AT2 Λ L1 < L2) – only forms partial order
eg. P(AT1 > AT2) = 0.6: sol 1 >> 2, but with a low probability
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Statistical Operations in Buffer Insertion Problem
Buffer insertion-related timing calculation Adding a wire
ATi = ATj – r*dij*Lj – 0.5*r*c*dij2
Adding a buffer ATbuf = ATi – d – Reff*Li
Merging two branches ATi = min(ATj, ATk)
Key operations on variables StatisticalStatistical subtraction (addition) and minimum
(maximum)
+i j
+i buf
jki
min?
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Statistical Operations in Buffer Insertion Problem
Add: z = x + y (if x and y independent) CDFz(t) = PDFx(t) ⊕ CDFy(t)
Max: z = max(x, y) (if x and y independent) CDFz(t) = CDFx(t) * CDFy(t)
Independence of random variables Adding wire Adding buffer Merging branches
+i j
constanti
+ bufuncorrelated
j+
ki from independent subtrees
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Modeling Cumulative Distribution Functions (CDFs)
CDF: PWL curve [Devgan-ICCAD] Statistical addition (convolution) and maximum
(multiplication) has closed-form solutions under PWL modeling FAST!!
Sampling at pre-set percentile points on the y-axis is performed after operations to keep PWL form
PDF: Piecewise constant (PWC) curve Obtained by differentiating the PWL of CDF
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Key to Pruning: Definition of Dominance
CDF Dominance Dominated curve completely on the L.H.S. of some others
Yield-cutoff dominance Compare the AT only at the target timing yield rate (Yt)
CDF Dominance Yield-cutoff dominance
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CDF Pruning
Accurate as it does not drop options that may lead to the optimal solution
Ineffective as it does not form total-order
⊕ or *
=
dominatedstill dominated
Not dominating one another under CDF Dominance,
i.e., must keep both curves
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Yield-cutoff Pruning
No partial-ordering issue, i.e. effective
Experimentally proven to achieve same accuracy as CDF Pruning
CDF Pruning Yield-cutoff Pruning
Testcase Mean (ps) SD (ps) Δ Mean Δ SD
Line -6569 338 0% 0%
5-sink -11543 505 0% 1.2%
6-sink -9189 437 0.03% 0.002%
log(runtime) (s)
wire length (um)
CDF PruningYield-cutoff Pruning
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Experimental Settings
Experimental settings Target timing yield rate at 90%
i.e. maximize the AT of 90% of dies Risetime at any node has 99% chance < 100ps
SBW+Fill as our baseline CMP as after-thought and no Leff variation Requires over-constrained slew rate ratio 0.75
i.e. design under 75ps to satisfy risetime constraint
vSBWF: SBWF + Leff variation
![Page 23: Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun.](https://reader030.fdocuments.in/reader030/viewer/2022032522/56649d6b5503460f94a4aa8b/html5/thumbnails/23.jpg)
Definition of Timing Yield
AT with 90% timing yield for vSBWF Yield rate at the same AT of SBW+Fill is only 25.1%
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Experiment: SBW+Fill vs vSBWF
Timing yield SBW+Fill: 45.7% on average vSBWF: 90% as targeted
Runtime of vSBWF 8.3x that of SBW+Fill
SBW+Fill vSBWF
testcase # sinks yield (%) runtime (s) yield (%) runtime(s)
r1 267 0.1% 101 90% 1054
r2 598 6.7% 213 90% 2126
r3 862 5.9% 277 90% 2140
r4 1903 9.0% 607 90% 4429
r5 3101 1.5% 972 90% 7440
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Conclusion
Developed SBWF: CMP-aware buffering, wire sizing and fill insertion Reduced 1.0% delay and 5.7% power
Extended SBWF to Leff random variation Proposed efficient yet effective yield-cutoff pruning rules Improved timing yield rate by 44.3% Finished largest example (3000+ sinks) in 2 hours