Simulation & Synthesis
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Transcript of Simulation & Synthesis
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Simulation & Synthesisof UART HD-6402 using VHDL
[02-384] Deepak Patel
Presented by
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Scope of our Project
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VLSI and its Emergence
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Chip Complexity
1975: transistor size = 10m
1985: transistor size = 2m
1995: transistor size = 0.4m
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Introduction to VHDL
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Design Process
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Required product
Design specifications
Initial design
Simulation
Design correct?
Redesign
Prototype implementation
Testing
Meets specifications?
Finished product
Minor errors?
Make corrections
No
Yes
No
Yes
Yes
No
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Concept of Design Review
Design SpecificationsSimulationRTL SimulationSynthesis DescriptionVerify Synthesis ResultsTiming AnalysisImplementation( FPGAs , ASICs )
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UART Basics for our project
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Communication system
SourceTransmitter
EncoderReceiverDecoder
DestinationChannel
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Asynchronous Communication
Start Bit Stop Bit
8 Data Bits
Mark
Space
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What is UART ?
niversal
synchronous
eceiver
ransmitter
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Basic UART Interface
PARALLEL DATA BUSPARALLEL DATA BUS
UART
P ExternalDevice
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Need for UART
To convert the parallel data from P systems to serial data to external devices Or vice-versa. It is necessary to have an interfacing device.
External devices are capable of communicating only serially
Computer and P systems often send/receive data in parallel format
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Block Diagram of UART
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Block Diagram of UART
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Control Word
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Advantages of Implementing UART using VHDL
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How Stuff works ???
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PARITY FUNCTION
CLS2 CLS1 DATA LENGTH
0 0 5 BITS
0 1 6 BITS
1 0 7 BITS
1 1 8 BITS
CLS2 CLS1 8 BIT DATA
PARITY GENERATOR
PARITY BIT
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TRANSMITTER
CLS2 CLS1 PI EPE SBS
P1: If CRL is High load CONTROLWORD
P2:
0 to 5 Bits 1 to 2 Bits 0 or 1 Bit 5 to 8 Bits 1 Bit
Extra
bits
Stop
bits
Parity
bits
Data
bits
Start
bits
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P3: Generation of TRE, TBRE.
CLS2 CLS1 PI EPE SBS
If CTRLWORD is 000X0 counter = 8If CTRLWORD is 000X1 counter = 9 Shifting 12 bit contents to right bit by bit.
Transmit serial Data at TRO pin.
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RECEIVER
CLS2 CLS1 SBS PI EPE
P1: If CRL is High load CONTROLWORD.Receive data from transmitter bit by bit.
P2: To see that data is not overwritten with the help of DR pin.To store each bit serially in a register.
11 10 9 8 7 6 5 4 3 2 1 0
If CONTROLWORD is 0001X => 1 start 5 data 0 parity 1 stopSo 5th bit is checked and if 0 then DR is set
Data In
Data
Out
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P3: In it valid data is send into receiver register and extra zeros are padded.
If CONTROLWORD is 0001X =>1 start 5 data 0 parity 1 stop
So valid data bits are from 10 to 6.
P4: In it PE, FE, OE are generated.
If CTRLWORD is XX101- check 9th bit.
If CTRLWORD is XX001- check 10th bit.
If CTRLWORD is XX0XX- check 11th bit for Stop bit.
If CTRLWORD is XX1XX- check 10th and 11th bit for Stop bit.
P5: Sends 8 Bit data to RBR and sends error output to output pins.
CLS2 CLS1 SBS PI EPE
11 10 9 8 7 6 5 4 3 2 1 0Data In
Data
Out
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