Mentor Graphics Mentor Graphics Simulation Tools for ASIC Simulation Tools for ASIC

Design Design

Victor P. Nelson

ASIC Design FlowASIC Design Flow

BehavioralModel

VHDL/Verilog

Gate-LevelNetlist

Transistor-LevelNetlist

PhysicalLayout

Map/Place/Route

DFT/BIST& ATPG

VerifyBehavior

VerifyFunction

Verify Function& Timing

Verify Function& Timing

DRC & LVSVerification

IC Mask Data

Standard Cell IC & FPGA/CPLD

Synthesis

Test vectors Full-custom IC

Simulation

ADVance MSADVance MSDigital, Analog, Mixed-Signal Digital, Analog, Mixed-Signal

SimulationSimulation

ADVance MS

WorkingLibrary

Design_1Design_2

VITAL

IEEE 1164 ResourceLibraries

SimulationSetup

EZwaveor Xelga

InputStimuli

VHDL,Verilog,VHDL-AMS, Verilog-A,

SPICE Netlists

Eldo,Eldo RF ModelSim

View ResultsMach TAMach PA

Analog(SPICE) Digital

(VHDL,Verilog)

Mixed Signal(VHDL-AMS, Verilog-A)

SPICEmodels

Mentor Graphics Legacy Mentor Graphics Legacy SimulatorsSimulators

Originally designed for PCB designOriginally designed for PCB design– Quicksim IIQuicksim II : digital, gate-level simulation : digital, gate-level simulation

Invoke : Invoke : quicksimquicksim ASIC Design Kit : ASIC Design Kit : adk_quicksimadk_quicksim Xilinx FPGA : Xilinx FPGA : pld_quicksimpld_quicksim, Altera : , Altera :

max2_quicksimmax2_quicksim

– Quicksim ProQuicksim Pro : mixed schematic & HDL : mixed schematic & HDL Uses Uses bothboth Quicksim II and Modelsim EE Quicksim II and Modelsim EE Invoke: Invoke: qsproqspro

– AccusimAccusim : analog simulation (SPICE) : analog simulation (SPICE) Invoke :Invoke : adk_accusim adk_accusim

Basic simulation Basic simulation environmentenvironment

Logic verification

Timing analysis

Netlist

Component models

Test vectors

Design

Simulator

Behavior/

-Digital values,-Digital values,-Analog -Analog voltages/voltages/ currents,currents,-Waveforms-Waveforms

-Behavioral -Behavioral description,description,-Circuit -Circuit structure/netlist,structure/netlist,-Timing information, -Timing information, etc.etc.

Results listings, graphical waveforms,Results listings, graphical waveforms,Reports of measurements, result checks, Reports of measurements, result checks, constraint violations, etc.constraint violations, etc.

-Generic,-Technology- specific

Mentor Graphics ASIC Design Kit Mentor Graphics ASIC Design Kit (ADK)(ADK)

ASIC technology files & standard cell librariesASIC technology files & standard cell libraries– AMI: ami12, ami05 AMI: ami12, ami05 (1.2, 0.5 (1.2, 0.5 μμm)m)– TSMC: tsmc035, tsmc025, tsmc018 TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 (0.35, 0.25, 0.18 μμm)m)

IC flow & DFT tool support files:IC flow & DFT tool support files:– Simulation Simulation

VHDL/Verilog/Mixed-Signal modelsVHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)(Modelsim/ADVance MS) Analog (SPICE) modelsAnalog (SPICE) models (Eldo/Accusim)(Eldo/Accusim) Post-layout verification Post-layout verification (Mach TA)(Mach TA) Digital schematic Digital schematic ((Quicksim II, Quicksim Pro)Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018)(exc. tsmc025,tsmc018)

– Synthesis library of std. cells Synthesis library of std. cells (LeonardoSpectrum)(LeonardoSpectrum)– Design for test & ATPG Design for test & ATPG (DFT Advisor, Flextest/Fastscan)(DFT Advisor, Flextest/Fastscan)– Schematic capture Schematic capture (Design Architect-IC)(Design Architect-IC)– IC physical design (standard cell & custom) IC physical design (standard cell & custom)

Floorplan, place & route Floorplan, place & route (IC Station)(IC Station) Design rule check, layout vs schematic, parameter extraction Design rule check, layout vs schematic, parameter extraction

(Calibre)(Calibre)

HDLs in Digital System HDLs in Digital System DesignDesign

Model and document digital systemsModel and document digital systems– Hierarchical modelsHierarchical models

System, RTL (Register Transfer Level), gatesSystem, RTL (Register Transfer Level), gates

– Different levels of abstractionDifferent levels of abstraction Behavior, structureBehavior, structure

Verify circuit/system design via Verify circuit/system design via simulationsimulation– Modelsim EEModelsim EE (VHDL, Verilog, System C) (VHDL, Verilog, System C)– ADVance MSADVance MS (above + VHDL-AMS, Verilog-A) (above + VHDL-AMS, Verilog-A)

Synthesize circuits from HDL modelsSynthesize circuits from HDL models– LeonardoLeonardo (Synopsis) (Synopsis)

-- count4.vhd 4-bit parallel-load synchronous counter-- count4.vhd 4-bit parallel-load synchronous counterLIBRARY ieee;LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;

ENTITY count4 ISENTITY count4 IS PORT (clock,clear,enable,load_count : IN STD_LOGIC;PORT (clock,clear,enable,load_count : IN STD_LOGIC;

D: IN unsigned(3 downto 0);D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0));Q: OUT unsigned(3 downto 0));END count4;END count4;

ARCHITECTURE rtl OF count4 ISARCHITECTURE rtl OF count4 ISSIGNAL int : unsigned(3 downto 0);SIGNAL int : unsigned(3 downto 0);BEGINBEGIN PROCESS(clear, clock, enable)PROCESS(clear, clock, enable) BEGIN BEGIN IF (clear = '1') THEN IF (clear = '1') THEN int <= "0000";int <= "0000"; ELSIF (clock'EVENT AND clock='1') THEN ELSIF (clock'EVENT AND clock='1') THEN IF (enable = '1') THEN IF (enable = '1') THEN

IF (load_count = '1') THENIF (load_count = '1') THEN int <= D;int <= D; ELSEELSE

int <= int + "01";int <= int + "01"; END IF;END IF; END IF;END IF; END IF;END IF; END PROCESS; END PROCESS; Q <= int;Q <= int;END rtl;END rtl;

Typical VHDLbehavioral model

Test stimulus:Test stimulus:Modelsim “do” file: count4_rtl.doModelsim “do” file: count4_rtl.do

add wave /clock /clear /enable /load_count /D /Qadd wave /clock /clear /enable /load_count /D /Qadd list /clock /clear /enable /load_count /D /Qadd list /clock /clear /enable /load_count /D /Qforce /clock 0 0, 1 10 -repeat 20force /clock 0 0, 1 10 -repeat 20force /clear 0 0, 1 5, 0 10force /clear 0 0, 1 5, 0 10force /enable 0 0, 1 25force /enable 0 0, 1 25force /load_count 0 0, 1 20, 0 35, 1 330, 0 350force /load_count 0 0, 1 20, 0 35, 1 330, 0 350force /D 10#5 0, 10#9 300force /D 10#5 0, 10#9 300run 400run 400

Testbench: Testbench: count4_bench.vhdcount4_bench.vhdLIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;

ENTITY count4_bench is end count4_bench;ENTITY count4_bench is end count4_bench;ARCHITECTURE test of count4_bench isARCHITECTURE test of count4_bench is component count4component count4 PORT (clock,clear,enable,load_count : IN STD_LOGIC;PORT (clock,clear,enable,load_count : IN STD_LOGIC;

D: IN unsigned(3 downto 0);D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0));Q: OUT unsigned(3 downto 0)); end component;end component; for all: count4 use entity work.count4(behavior);for all: count4 use entity work.count4(behavior); signal clk : STD_LOGIC := '0';signal clk : STD_LOGIC := '0'; signal clr, en, ld: STD_LOGIC;signal clr, en, ld: STD_LOGIC; signal din, qout: unsigned(3 downto 0);signal din, qout: unsigned(3 downto 0);beginbegin C4: count4 port map(clk,clr,en,ld,din,qout);C4: count4 port map(clk,clr,en,ld,din,qout); clk <= not clk after 10 ns;clk <= not clk after 10 ns; P1: processP1: process beginbegin din <= "0101"; clr <= '1'; en <= '1'; ld <= '1';din <= "0101"; clr <= '1'; en <= '1'; ld <= '1'; wait for 10 ns;wait for 10 ns; clr <= '0'; clr <= '0'; wait for 20 ns;wait for 20 ns; ld <= '0';ld <= '0'; wait for 200 ns;wait for 200 ns; end process;end process;end;end;

Alternative to “do” file

Could check results &“assert” error messages

Count4 – Simulation Count4 – Simulation waveformwaveform

ParallelLoad

Counting

Clear

ADVance MS : mixed-signal ADVance MS : mixed-signal simulationsimulation

A/D converter

digital

analogVHDL-AMS

VHDL-AMS modelsVHDL-AMS models

D/A converter

Comparator

ADVance MS: mixed Verilog-ADVance MS: mixed Verilog-SPICESPICE

SPICEsubcircuit

Verilog top(test bench)

Leonardo synthesis procedureLeonardo synthesis procedure

1.1. Invoke Invoke leonardoleonardo2.2. Select & load a technology library Select & load a technology library (ASIC or (ASIC or

FPGA)FPGA)– ASIC > ADK > TSMC 0.35 micronASIC > ADK > TSMC 0.35 micron

3.3. Read input VHDL/Verilog file(s): Read input VHDL/Verilog file(s): count4.vhdcount4.vhd

4.4. Enter any constraints (clock freq, delays, etc.)Enter any constraints (clock freq, delays, etc.)5.5. Optimize for area/delay/effort levelOptimize for area/delay/effort level6.6. Write output file(s)Write output file(s)

– count4_0.vhdcount4_0.vhd - VHDL netlist - VHDL netlist (for simulation)(for simulation)– count4.vcount4.v - Verilog netlist - Verilog netlist (for IC layout)(for IC layout)– count4.sdf count4.sdf - Standard delay format file - Standard delay format file (for (for

timing)timing)– count4.edf count4.edf - EDIF netlist - EDIF netlist (for Xilinx/Altera FPGA)(for Xilinx/Altera FPGA)

Leonardo-synthesized netlist count4_0.vhdLeonardo-synthesized netlist count4_0.vhdlibrary IEEE; use IEEE.STD_LOGIC_1164.all;library IEEE; use IEEE.STD_LOGIC_1164.all;library adk; use adk.adk_components.all; -- ADDED BY VPNlibrary adk; use adk.adk_components.all; -- ADDED BY VPNentity count4 isentity count4 is port (port ( clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ;clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ;D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ;end count4 ;end count4 ;

architecturearchitecture netlistnetlist of count4 isof count4 is signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189: std_logic ;nx183, nx185, nx187, nx189: std_logic ;beginbegin Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ;Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear);Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable );ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable ); ix9 : oai21 port map ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 );ix9 : oai21 port map ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 ); ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count);ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count); Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock,

R=>clear);R=>clear); ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable);ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable); ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22);ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22); ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count);ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count); Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear);Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable);ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable); ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189);ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR);ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR); ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187); ix186 : inv01 port map ( Y=>nx185, A=>load_count);ix186 : inv01 port map ( Y=>nx185, A=>load_count); ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR);ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR); ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count);ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count); Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear);Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable);ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable); ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count);ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count); ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);end netlist ;end netlist ;

Post-synthesis simulationPost-synthesis simulation((LeonardoLeonardo-generated netlist)-generated netlist)

Verify synthesized netlist matches behavioral Verify synthesized netlist matches behavioral modelmodel

Create simulation primitives library for std Create simulation primitives library for std cells:cells:

>vlib adk>vlib adk>vcom $ADK/technology/adk.vhd>vcom $ADK/technology/adk.vhd>vcom $ADK/technology/adk_comp.vhd>vcom $ADK/technology/adk_comp.vhd

Insert library/package declaration into netlistInsert library/package declaration into netlistlibrary adk;library adk;use adk.adk_components.all;use adk.adk_components.all;

Simulate in Modelsim, using “do file” or test bench Simulate in Modelsim, using “do file” or test bench from original behavioral simulation from original behavioral simulation – results should matchresults should match

models of all ADK std cells

Preparation for LayoutPreparation for Layout1.1. Convert Verilog netlist to Mentor Graphics “EDDM” Convert Verilog netlist to Mentor Graphics “EDDM”

schematic/netlist formatschematic/netlist format– Invoke Design Architect-IC Invoke Design Architect-IC (adk_daic)(adk_daic)– On menu bar, select On menu bar, select File > Import VerilogFile > Import Verilog

Netlist file: Netlist file: count4.v count4.v (the Verilog netlist)(the Verilog netlist) Output directory: Output directory: count4count4 (for the EDDM netlist)(for the EDDM netlist) Mapping file Mapping file $ADK/technology/adk_map.vmp$ADK/technology/adk_map.vmp

2.2. Open the schematic for viewingOpen the schematic for viewing– Click Click SchematicSchematic in DA-IC palette in DA-IC palette – Select schematic in directory named above Select schematic in directory named above (see next slide)(see next slide)– Click Click Update LVS Update LVS in the schematic palette to create a netlist in the schematic palette to create a netlist

to be used later by “Calibre”to be used later by “Calibre”

3.3. Create design viewpoints for ICstation toolsCreate design viewpoints for ICstation tools– adk_dve count4 –t tsmc035 adk_dve count4 –t tsmc035 (V.P’s: layout, lvs, sdl, (V.P’s: layout, lvs, sdl,

tsmc035)tsmc035)

Can also draw gate/transistor schematics directly in Can also draw gate/transistor schematics directly in DA-IC using components from the ADK libraryDA-IC using components from the ADK library

““count4” schematic count4” schematic (from Leonardo-generated netlist)(from Leonardo-generated netlist)

Simulating the schematic Simulating the schematic modelmodel

Quicksim IIQuicksim II (legacy – “Falcon Framework”)(legacy – “Falcon Framework”)– EDDM netlist modelsEDDM netlist models

create in Design Architect/Design Architect-ICcreate in Design Architect/Design Architect-IC component models component models

– Stimulus in “do file”, similar to ModelsimStimulus in “do file”, similar to Modelsim EldoEldo – analog/SPICE simulator – analog/SPICE simulator

– AccusimAccusim – legacy analog/SPICE simulator – legacy analog/SPICE simulator Export VHDL/Verilog netlist for HDL Export VHDL/Verilog netlist for HDL

simulatorsimulator

Mentor Graphics “Falcon” Mentor Graphics “Falcon” Framework ToolsFramework Tools

Preparation for using Quicksim Preparation for using Quicksim IIII

Create netlist & design viewpointsCreate netlist & design viewpoints ““Design viewpoint” provides downstream Design viewpoint” provides downstream

tools with tool-specific informationtools with tool-specific information– primitives, properties, parameters primitives, properties, parameters – technology-specific simulation modelstechnology-specific simulation models

Create viewpoints Create viewpoints one timeone time for each for each schematicschematic

adk_dve design –technology tsmc035adk_dve design –technology tsmc035 designdesign = schematic netlist component name = schematic netlist component name tsmc035tsmc035 = ASIC technology to be used = ASIC technology to be used

– ASIC technologies available in ADK:ASIC technologies available in ADK:

tsmc018**, tsmc025**, tsmc035, ami05, ami12 tsmc018**, tsmc025**, tsmc035, ami05, ami12

(** no Quicksim models)(** no Quicksim models)

Design viewpoints for component Design viewpoints for component “bob”“bob”

Quicksim IIviewpoint

Accusimviewpoint

ICgraph Layout viewpoint

Layout vs.schematiccheck viewpoint

Schematic-drivenlayout viewpoint(ICgraph)Transistor-level

Back annotationfile for layoutparameterextraction

Schematic

Logic symbol

Mentor Graphics “Design Manager”

Quicksim II operationQuicksim II operation Invoke Quicksim II: Invoke Quicksim II: adk_quicksim adk_quicksim

bob/tsmc035bob/tsmc035– ““bobbob” = design component” = design component– ““tsmc035tsmc035” = quicksim viewpoint” = quicksim viewpoint

Quicksim II “kernel” has three modes:Quicksim II “kernel” has three modes:– Unit (default):Unit (default): all components have 1 unit of delay all components have 1 unit of delay– DelayDelay: delays specified as “triplets”: delays specified as “triplets”

(min-delay typ-delay max-delay)(min-delay typ-delay max-delay) from technology filesfrom technology files

– ConstraintConstraint: same as Delay, but with detection of : same as Delay, but with detection of glitches, contraint violations, etc.glitches, contraint violations, etc.

Quicksim II multi-valued Quicksim II multi-valued simulationsimulation

Each signal has a “state” and a drive Each signal has a “state” and a drive “strength”“strength”

ValueValue Logic stateLogic state

00 ZeroZero

11 OneOne

XX UnknownUnknown

ValueValue Drive strengthDrive strength

ss StrongStrong

rr ResistiveResistive

zz Float (no drive)Float (no drive)

ii IndeterminateIndeterminate

Example: 1s = strongly driven to 1 1r = resistively pulled up to 1

force a 0 0force a 0 0force a 1 25force a 1 25force a 0 55force a 0 55force r 1 0force r 1 0force r 0 7force r 0 7force r 1 12force r 1 12set clock period 20 set clock period 20 force c 0 0 -repeat force c 0 0 -repeat force c 1 10 -repeatforce c 1 10 -repeat

Example “force file” for circuit Example “force file” for circuit “bob”“bob”

(similar to Modelsim EE)(similar to Modelsim EE)

ValueState

Clock definition

Quicksim II simulation of Quicksim II simulation of “bob”“bob”

Eldo simulation from DA-ICEldo simulation from DA-IC

Run simulations from within DA-ICRun simulations from within DA-IC– EldoEldo, , ADVance MSADVance MS, , Mach TAMach TA

DA-IC invokes a “netlister” to create DA-IC invokes a “netlister” to create a circuit model from the schematica circuit model from the schematic– SPICE model for SPICE model for EldoEldo & & Mach TAMach TA

Eldo analyses, forces, probes, etc. Eldo analyses, forces, probes, etc. same as SPICEsame as SPICE

View results in View results in EZwaveEZwave or or XelgaXelga

Eldo input and output filesEldo input and output files

-Netlist-Simulation cmds-Stimulus

SPICE netlist for modulo7 counterSPICE “circuit” file generated by DA-IC

Force values (created interactively)

From ADKlibrary

Eldo simulation of modulo7 Eldo simulation of modulo7 countercounter

(transient analysis)(transient analysis)

Post-layout simulation with Post-layout simulation with MachTAMachTA

MachTA is an accelerated Spice simulatorMachTA is an accelerated Spice simulator– Digital & mixed-signal circuitsDigital & mixed-signal circuits– Analyze timing effects pre- and post-layoutAnalyze timing effects pre- and post-layout

SPICE netlists with parasitic R/CSPICE netlists with parasitic R/C

– Execute test vector file to verify functionalityExecute test vector file to verify functionality Algorithms support large designs Algorithms support large designs

– Partition design, simulate only partitions with Partition design, simulate only partitions with changeschanges

– Combine time-driven & event-driven operationCombine time-driven & event-driven operation– Solves linearized models using a proprietary

high-performance, graph-theory based, matrix solution algorithm

Mach TA flow diagramMach TA flow diagram

SPICEnetlist

$ADK/technology/mta/tsmc035

Post-layout simulation with Post-layout simulation with Mach TAMach TA

(netlist extracted by Calibre PEX)(netlist extracted by Calibre PEX) Prepare netlist Prepare netlist (remove subcircuits for (remove subcircuits for

Mach TA)Mach TA)– Extracted netlist = Extracted netlist = count4.pex.netlistcount4.pex.netlist– Command: Command: $ADK/bin/mta_prep count4$ADK/bin/mta_prep count4– Creates SPICE file: Creates SPICE file: count4.spcount4.sp

Invoke Mach TA:Invoke Mach TA:anaana - command file to initialize Anacad SW- command file to initialize Anacad SW

mta –ezw –t $ADK/technology/mta/tsmc035 mta –ezw –t $ADK/technology/mta/tsmc035 count4.spcount4.sp Mach PA (mpa) does current & power analysis

Mach TA main windowMach TA main window

Mach TA simulation Mach TA simulation commandscommands

Sample Mach TA “dofile”Sample Mach TA “dofile”(transient analysis)(transient analysis)

plot v(clk) v(q[2]) v(q[1]) v(q[0])plot v(clk) v(q[2]) v(q[1]) v(q[0])measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0])

VAL=2.5vVAL=2.5vl loadl loadl resetl reseth counth countl clkl clkrun 5 nsrun 5 nsh reseth reseth clkh clkrun 5 nsrun 5 nsl clkl clkrun 5 nsrun 5 nsh clkh clkrun 5 nsrun 5 ns

Signals to observe in EZwave

Measure time from rising edge of clk (TRIGger)to 1st rising edge of q[0] (TARGet) - voltages

Drive signals low/high (Lsim format)

Simulate for 5 ns

Command to execute: dofile file.do

EZwave waveform viewerEZwave waveform viewer(results for previous dofile)(results for previous dofile)

Double-clicksignal nameto display.

Alternative Mach TA “dofile”Alternative Mach TA “dofile”(same result as previous example)(same result as previous example)

plot v(clk) v(q[2]) v(q[1]) v(q[0])plot v(clk) v(q[2]) v(q[1]) v(q[0])measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG

v(q[0]) VAL=2.5vv(q[0]) VAL=2.5vvpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n

20n)20n)l loadl loadl resetl reseth counth countrun 5 nsrun 5 nsh reseth resetrun 200 nsrun 200 ns

Voltage source name

Nodes to whichsource connected

v-levels delay rise fall width period

Periodic pulses

Mach TA – test vector fileMach TA – test vector file

Verify design functionality/behaviorVerify design functionality/behavior– apply test vectorsapply test vectors– capture outputscapture outputs– compare outputs to expected resultcompare outputs to expected result– vectors/outputs from behavioral vectors/outputs from behavioral

simulationsimulation Command to execute a test vector Command to execute a test vector

file:file:run –tvend tvfile.tvrun –tvend tvfile.tvtest vector file (next slide)

Test vector file formatTest vector file format# Test vector file for modulo7 counter# Test vector file for modulo7 counterCODEFILECODEFILEUNITS psUNITS psRISE_TIME 50RISE_TIME 50FALL_TIME 50FALL_TIME 50INPUTS clk,reset,load,count,i[2],i[1],i[0];INPUTS clk,reset,load,count,i[2],i[1],i[0];OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);CODING(ROM)CODING(ROM)RADIX <11113>3;RADIX <11113>3;@0 <01105>X;@0 <01105>X;@2000 <00105>0;@2000 <00105>0;@7000 <01105>0;@7000 <01105>0;@10000 <11105>5;@10000 <11105>5;@20000 <01015>5;@20000 <01015>5;@30000 <11015>6;@30000 <11015>6;@40000 <01015>6;@40000 <01015>6;@50000 <11015>0;@50000 <11015>0;@60000 <01015>0;@60000 <01015>0;……....ENDEND

Header

Vectors: @time <input_vector>expected_output

Sample 5 fs before next vector

signal order within vectors

Test vectors derived from behavioral simulation results

Vector format

Behavioral simulation listing Corresponding Mach TA test vector file

Alternate test vector fileAlternate test vector file(clock generated separately by voltage (clock generated separately by voltage

source)source)

vpulse vclk clk 0 pulse(0 3.3 10n .5n .5n 10n 20n)

Can mix other simulationcommands with test vectorapplication.

Mach TA structure & schematic Mach TA structure & schematic viewerviewer

SummarySummary Simulation at each stage of ASIC design Simulation at each stage of ASIC design

– behavioral modelbehavioral model– synthesized netlistsynthesized netlist– pre-layout schematic/netlistpre-layout schematic/netlist– post-layout netlistpost-layout netlist

ADVance MSADVance MS combines 3 technologies to combines 3 technologies to cover the abovecover the above– digital (VHDL, Verilog)digital (VHDL, Verilog)– analog/mixed-signal (VHDL-AMS, Verilog-A)analog/mixed-signal (VHDL-AMS, Verilog-A)– transistor level (Eldo, Mach TA)transistor level (Eldo, Mach TA)

ASIC Design KitASIC Design Kit (ADK) supports all tools in (ADK) supports all tools in the design flow, including simulationthe design flow, including simulation