Silicon Strip Readout and the XYTER Electronics Development

Silicon Strip Readout

and the

XYTER Electronics Development

Christian J. Schmidt et al.,GSI Darmstadt

10th CBM Collaboration Meeting, Dresden, Sept. 24. – 28., 2007

10th CBM Collaboration Meeting, Dresden Sept. 24 – 28, 2007

Challenging Experiments, Challenging Detector Specs

As a fixed target machine, very high event-rates (1000 tracks at 10MHz for CBM)

Up to 5% channel occupancy,

Very inhomogeneous track distribution (forward cone)

Signal latency will be too large for a timely, reasonable trigger decision,

Event overlap expected

Need front-end electronics:

MIPs at high input capacitance

highly integrated,

asynchronous, autonomous hit

detection,

time stamp labeling.


Additionally

Very harsh radiation environment (10 MRad)

Very high density channels with need for either

low radiation-length detector design (CBM-STS, PANDA TPC, PANDA forward GEM trackers, CBM TRD)

... or very compact detector design (e.g. CBM-Muon Chambers)


n-XYTER: Novel FE-Chip Architecture Cast in Silicon

Architectural Solution for FAIR CBM and PANDA.Starting point towards a FAIR dedicated XYTER front-end ASICOur work-horse readout ASIC for detector prototyping

detector readout ASIC for high-density and high statistical rate time and amplitude measurement

128 channels @ 50.7 µ pitch

freely running,

self triggered autonomous hit detection

850 (1000) ENC at 30 pF

dynamic range for 6 MIPs (300µ Si)

positive and negative signals

Per channel analogue energy and digital time stamp FIFO (1ns resolution)

De-randomizing, sparsifying Token Ring readout at 32 MHz

n-XYTER was

developed for neutron

applications within EU

FP-6 NMI3


chargepreamp

FASTshaper 18.5 ns

peaking

SLOW shaper(2 stages)

140 ns peaking time

Peakdetector &

hold,free running

comparatorTime Walk

Compensationcircuit

PDHreset

pulse height

output

triggertimestamp reg.

chargeinput

Data Driven Front-End: Asynchronous Channel Trigger

dig. FIFO

analogue FIFO

Asynchronous registry and storage in

4-level fifo guarantees data loss < 4 %

when read-out through token ring

The DETNI ASIC 1.0, a front-end evaluation chip in AMS 0.35µ

detection of statistical, poisson distributed signals


Analogue Signal Sequence (Test Channel)

Testpulse Release

Slow Shaper

Fast Shaper

Discriminator Output


Test Board for Tests on n-XYTER

64/128 chan. connected

I²C-Interface

Test points accessible

All functional tests possible

Digital output accessible

One additional analogue test channel is available for direct access of slow and fast shaper outputs... with output buffer would

have been even more useful


Analogue Pulses, Peaking Time, Front-End Noise

FAST channel SLOW channel

ENC26.9 e/pF + 200 e

12.7 e/pF + 233 epeaking

timea (1% to 99%)

18.5 ns 139 ns

Engineered for 30 pF, giving (850 ) 1000 e 600 e

pre-amp and shaper power consumption: 12.8 mW per channel; OK for neutrons!


Slow Shaper Output, the Energy Channel

-250 0 250 500 750 1000 1250 15000,5

0,6

0,7

0,8

0,9

1,0

1,1

1,2

1,3

slow

sha

per

outp

ut (

V)

t in ns

20 fC 6,6 fC 3,1 fC

detector cap 10,2 pF

-1000 -500 0 500 1000 1500

-0,40

-0,35

-0,30

-0,25

Slo

w S

hape

r O

utpu

t (V

)

t in ns

4,9 pF 10,2 pF 21,2 pF 99,2 pF

Measurements on the test channel #129

varying input charge

varying input capacitance


Some Inter-Channel Pick-Up, Ongoing Detective Work

Cin = 0 pF, bond wire removed

System Effect

No dependence upon no. of bond wires, power or gnd

May be worsened with discriminator settings (TWC)

Cin = 22 pF

Feedback via spurious coupling through epitaxial, optical layer,

substrate to the input


Some In-Channel Discriminator Feedback Detected

...upon removal of discriminator-power decoupling

These issues are particularly important with the self triggered architecture!

They will be addressed even more in the next engineering run.

correlates with internal discriminator trigger

correlates with external test-pulse release signal (blue)


Channel layout overview, Clock Domains and Power

analogue front end , PDHcomp – TWC

trim regmaskreg.

analoguemem.

ch.ID

tokencell

TSlatch

digitalmem.

monosynchcontrol

input MOSGND

analogueGND

& BULK

analogueVDD

A/Dguard ring

digitalBULK

digitalGND

digitalVDD

clocktree

comparatorVDD

memory control ( 9 bit )PDH reset

comp

PAD

analogue domainno clock

digital domainsystem clock

8 mm

time stampfast clock

5 mm

total of 4 nF on chip MIM caps


Token Ring Readout, Data Transmission

-100n 0 100n 200n 300n 400n 500n 600n

Time (s)

Input Trg

CLK (128) CLK (32)

D7 D6 D5 D4 D3 D2 D1 D0

Data Valid

TS grey codedCh# grey coded

data transfer tested at 35 MHz, will also work at 128 MHz

Measurement: Transmission of four data elements on channels 1, 8, 30, 82


Analogue Differential Output, the Energy Channel

-1000 0 1000 2000 3000 4000 5000-0,30

-0,25

-0,20

-0,15

-0,10

-0,05

0,00

0,05

0,10

0,15

Diff

eren

tial O

utpu

t B

uffe

r S

igna

l (V

)

Time in ns

-10 -5 0 5 10 15 20

-0,16

-0,14

-0,12

-0,10

-0,08

-0,06

-0,04

-0,02

An

alo

g D

iffe

ren

tial O

utp

ut (

V)

t in ns

Signal settling upon successive data

Three signals, one signal altered


Power Consumption

preamplifier 7.4mW

fast shaper 2.5mW

slow shaper stage 1 1.7 mW

slow shaper stage 2 2.5 mW

discriminator 2.1 mW

peak detector and hold 2.7 mW

analogue FIFO 2.3 mW

overall we find 21 mW/channel operating power


Testing Summary

Slow Control Operative

Clocking at 256 MHz possible

Grey coded time stamp generated

Analogue readout operative

Features operative: Positive and negative signal processing

Global threshold, local threshold fine tune

On chip test pulse generation

Channel masking

Channel forced trigger (baseline determination)

Individual channel shut down

Pile-up lableing, fifo overflow identification

Testers involved:

Gerd Modzel (PI HD)

Markus Höhl (GSI)

Knut Solvag (GSI)

Sharma Anurag (Dehli)

Rafal Lalik (AGH, GSI)

Adam Czermak (AGH)

thanks for his support to

Sven Loechner (GSI) and others


n-XYTER Engineering Run in Preparation

Engineering Run Targeted for Jan. 2008

H. K. Soltveit (PI Heidelberg)

Addresses active feedback baseline adjustment

full dynamic range, no temp. co. on base-line

Addresses spurious feedback coupling through substrate

Reduction of power consumption where easily possible

From 250 Dies to Work Horse Electronics for Detector Prototyping

Will yield several thousand chips for prototyping of

CBM STS, PANDA TPC and other detectors

as well as the DAQ chain and beyond.

Go

Detector

Prototyping


Dedicated XYTER Development for FAIR

Generic n-XYTER architecture finds broad applications within FAIR:

CBM Silicon Strips STS, High Rate GEM TPC as well as large area

gas detectors (micro structures or wire chambers)

Twin chip development with XYTER architecture and diversities for:

• Radiation hard design in UMC 0,180 µm (better than 10 MRad)• Minimized power consumption • Integration of modern, low power ADC on chip purely digital interface• Highly multiplexed data interface (minimize cableing)• Optimized system synchronization capabilities• SEU tolerance• Detector DC coupling capability• Dense mounting capability

Silicon Strip MIP detection,

micro-structured gas detectors

Larger dynamic range,

ion tail cancellation specialties


Groups Involved In XYTER Development

AGH Krakow, (Robert Szczygiel, Pawel Grybos et al.)

TI Heidelberg (Peter Fischer and Tim Armbruster)

MEPHI, Moscow (E. Atkin et al)

PI Heidelberg and HD ASIC-Lab (H. K. Soltveit)

GSI Darmstadt, C.J. Schmidt (coordination) and Sven Loechner

Further engaged:

S. Chattopadhyay et al, Kolkatta on individual design items

University Bergen, K. Ulaland and D. Röhrig et al

We will structure the XYTER development collaboration Friday morning 9:00 to 11:00

CBM


Thank you for your attention

CBM


Token Ring Architectural Pros/Cons

High Efficiency Empty channels automatically skipped in readout process Built-in fair distribution of readout bandwidth, automatic bandwidth focussing

Built-in De-Randomization: 100% bandwidth used on data

Error Robustness

Any problematic channel (e.g. continuously firering) will divert and occupy a

maximum of 1/nth of the bandwidth.

Built-in, non-perfect readout probability avoids unrecoverable logic deadlock:

Problematic situations like any kind of pile-up, logic hang-ups or glitch

cause mere deadtime but the “show will go on”.

But: Data needs to be tagged with a time-stampData needs to be resorted and re-bunched after readout


Investigating Individual Channels, Triggerefficiency

Trigger efficiency in Treshold Scan: The S-Curves

- Input of test pulses at fixed rate,- scan threshold while measuring detection rate

Derivative gives image of noise!


Trigger efficiency tested for all channels

origin of 2 ch periodicity attributed to four fold pulser circuitry

Channel number

note bonded and non-bonded channels


Token Ring Readout Process

Focus bandwidth where there is data

32 MHz data readout Automatic zero

suppression (sparsification)

Analog FIFO

Timestamp FIFO

datareadout

bus

token cycle

Disc.

token cell control logic for

data readout or token passskip channels without data, asynchronously rush through empty channels until data found


Modelling FIFO Occupancy

FIFO can virtually be filled with up to 2*n events with no data losssince n elements are read while data comes in.

1 2 3 4 5 6 7 8 9 10 11 1200

0.05

0.1

0.15

0.21 2 3 4 5 6 7 8 9 10 11 12 13

We loose from here on

Pro

bab i

li ty

Poisson Distribution(): e.g.: fifo depth n = 4, so expect 4 events during readout if incoming rate equals maximum readout rate. = 4.


n-XYTER Front-End Topology

Silicon Strip Readout and the XYTER Electronics Development

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Transcript of Silicon Strip Readout and the XYTER Electronics Development