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SiliconSilicon--onon--Sapphire (SOS) Technology Sapphire (SOS) Technology and the Linkand the Link--onon--Chip Design for Chip Design for LArLAr

FrontFront--end Readoutend Readout

Ping Gui, Jingbo Ye, Ryszard StroynowskiPing Gui, Jingbo Ye, Ryszard Stroynowski

Department of Electrical EngineeringDepartment of Electrical EngineeringPhysics DepartmentPhysics Department

Southern Methodist UniversitySouthern Methodist University

ATLAS Liquid Argon Colorimeter Upgrade WorkshopATLAS Liquid Argon Colorimeter Upgrade WorkshopJune 23, 2006June 23, 2006

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OutlineOutline

IntroductionIntroduction

SiliconSilicon--onon--Sapphire (Sapphire (SoSSoS) ) TechnologyTechnology

SoSSoS Test ChipTest Chip

LinkLink--onon--Chip DesignChip Design

33

RadiationRadiation--hardeninghardening--byby--Design (RHBD)Design (RHBD)

The wide availability of commercial IC processes has led to the philosophy of “radiation hardening by design”.

Explore circuit topologies and layout techniques to create radiation-tolerant circuits

• Submicron bulk CMOS inexpensive

• BiCMOSideal for mixed-signal design, but very expensive

• SOI/SOSrelatively new, growing in popularity

44

Radiation Hardening by DesignRadiation Hardening by Design

Total Dose EffectTotal Dose Effect•• Enclosed layout TransistorsEnclosed layout Transistors•• Guarded ringGuarded ring

Single Event EffectSingle Event Effect

•• Marjory vote circuitsMarjory vote circuits•• Error detection/correction CodingError detection/correction Coding• Charge dissipation technique• Temporal filtering technique

Trade-off between radiation tolerance, performance, area and power dissipation.

G. Anelli, 2000 IEEE Nuclear Science Symposium andMedical Imaging Conference

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RadiationRadiation--hard design challengeshard design challenges

Techniques that minimize one radiation mechanism may have little or no effect on another.

Years ago, total dose concerns dominated radiation tolerant design, but they are now secondary to single event effects (SEEs).

SEEs have grown in importance as feature sizes, capacitances, and operating voltages have been reduced.

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IC Feature Size and Radiation EffectsIC Feature Size and Radiation Effects

Tim Holman, Radiation Effects on Microelectronics Short Course 2001

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PeregrinePeregrine’’s SOS Technologys SOS Technology

Insulating sapphire substrate

sio2

N channel FETP channel FET

Insulating sapphire substrate

SOS Process

sio2

200 μm

100 nm

BULK CMOS

Peregrine’s SOSindustry’s first and only commercially qualified SOS technology

•No Single-event Latch-up in SoS CMOS!

•Increased immunity to SEE

•Ideal for radiation-tolerant mixed-signal circuit design due to minimum substrate noise

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Process FeaturesProcess FeaturesMinimum substrate noiseMinimum substrate noise•• Higher level integration of RF, Higher level integration of RF,

mixedmixed--signal and digital signal and digital circuitry.circuitry.

Reduced Parasitic capacitanceReduced Parasitic capacitance

High performanceHigh performance

Low Power consumptionLow Power consumption

Minimum crosstalkMinimum crosstalk

Widely used in RF and space Widely used in RF and space productsproducts

Transparent substrate allows for Transparent substrate allows for compact and simple integration compact and simple integration with optical deviceswith optical devices

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Flipped OE devices on Flipped OE devices on SoSSoS substratesubstrate

transparent sapphire substrate(UTSi)

active CMOS layer

quad PIN array

flip chip attachment

quad VCSEL array

UTSi integrated photo detector

MMF ribbon fiber

VCSEL driver circuitry receiver circuitry

UTSi integrated circuitry

200 um

FlipFlip--chip bonding of OE devices to CMOS on sapphirechip bonding of OE devices to CMOS on sapphire•• No wireNo wire--bonds bonds –– package performance scales to higher data ratespackage performance scales to higher data rates•• Rugged and compact packageRugged and compact package

1010

Peregrine Space Optical TransceiverPeregrine Space Optical Transceiver

15 mm heightBerg MegArray PCB socket

MTP Connector Module 0.50.5--um um SoSSoS

Single 4+4 transceiver component Single 4+4 transceiver component with variable data rates (CML with variable data rates (CML interface) interface) •• Minimum data rate Minimum data rate –– 10 Mbps10 Mbps•• Maximum data rate Maximum data rate –– 2.7 Gbps per 2.7 Gbps per

channelchannel

RadiationRadiation•• Total Ionizing Dose: 100 Total Ionizing Dose: 100 kRad(SikRad(Si))•• SEU: > 20 MeVSEU: > 20 MeV--cm2/mgcm2/mg

15 year operational lifetime15 year operational lifetime

125 mW per channel power 125 mW per channel power consumption (dissipated to panel consumption (dissipated to panel mount)mount)

VibrationVibration•• 15.33 gRMS for 3 minutes total15.33 gRMS for 3 minutes total

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SoSSoS CMOS CMOS v.sv.s. Bulk CMOS. Bulk CMOS

$800k for wafer mask $800k for wafer mask set; $800 per waferset; $800 per wafer

$100k for wafer mask set;$100k for wafer mask set;$1000 per wafer$1000 per wafer

CostCost

Substrate noise causes Substrate noise causes crosstalk between crosstalk between channelschannels

Minimum crosstalk due to Minimum crosstalk due to reduced substrate capacitancereduced substrate capacitance

CrosstalkCrosstalk

Reduced parasitic capacitance Reduced parasitic capacitance also leads to a lower power also leads to a lower power dissipationdissipation

Power Power DissipationDissipation

High Leakage currentHigh Leakage currentSubstrate as an insulator Substrate as an insulator (10(101414 ohm/m at room ohm/m at room

temperaturetemperature).). Reduced Reduced substrate junction capacitance substrate junction capacitance leads to lower leakage leads to lower leakage current.current.

Leakage Leakage CurrentCurrent

Up to 10 GHzUp to 10 GHzUp to 10 GHzUp to 10 GHzPerformancePerformance

0.13 0.13 μμm Bulk CMOSm Bulk CMOS0.25 0.25 μμm m SoSSoS

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BackBack--channel Leakage Current in SOSchannel Leakage Current in SOS

Possible Leakage path along the Si/Sapphire interface

1313

Preliminary Radiation Test Results on Preliminary Radiation Test Results on 0.50.5--µµm m SoSSoS CMOS TechnologyCMOS Technology

2.5GbpsBefore radiation

2.5GbpsPost-rad100Mrad

Transceiver chip made in0.5um SoS CMOS Technology

Radiation test setup at the Northeast Proton Therapy Center

1.6 GbpsPost-rad100Mrad

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Dedicated Radiation Test Chip for a Dedicated Radiation Test Chip for a 0.250.25--µµm SOS CMOSm SOS CMOS

•• Single NMOS and PMOSSingle NMOS and PMOS

•• Ring Oscillators Ring Oscillators to characterize the to characterize the performance and power performance and power dissipationdissipation

•• Shift registers to Shift registers to characterize SEEcharacterize SEE

Standard layout, edgeless Standard layout, edgeless layout, majority vote layout, majority vote circuit, resistively hardened circuit, resistively hardened cellscells

•• Digital Standard cellsDigital Standard cells

•• Current mirrorsCurrent mirrors

•• ResistorsResistors

TransistorXY matrix

Current mirrors/resistors

IndividualStandard Cells

Ring oscillators,

Ring oscillators

Shift registers

Shift registers

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Transistor Test StructuresTransistor Test StructuresNMOS and PMOS ArrayNMOS and PMOS Array

PMOS and NMOS with different sizePMOS and NMOS with different size•• Different lengths to characterize backDifferent lengths to characterize back--channel leakage channel leakage

currentcurrentEach transistor implemented in four layoutsEach transistor implemented in four layouts

•• Standard, edgeless (ELT), twoStandard, edgeless (ELT), two--finger and fourfinger and four--finger layout finger layout to characterize edge leakage currentto characterize edge leakage current

510

Edgeless (ELT) Two-fingerOne-finger

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SOS SOS RadRad--hard Test Chip Layouthard Test Chip Layout

Transistorsarray

PLL cells

CMOS Ring Oscillators

Shift Registers

Individual gates

Resistors

DifferentialRing

Oscillator

Majority votecircuitry

Chip was submitted for fabrication in Oct. 2005

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LinkLink--onon--Chip ArchitectureChip Architecture

Opticaldata

Improve performanceImprove performance•• No offNo off--chip high speed lineschip high speed lines•• FlipFlip--chip bonding reduces capacitance and inductancechip bonding reduces capacitance and inductance

Reduce power consumptionReduce power consumption•• No 50No 50--Ohm transmission lines between chipsOhm transmission lines between chips

LaserLaserDriverserializer

encoder

Flip-chipbonding

TXParallelData

REFclock

transmitter Module

Photonic

PIN

Receiver Module

TIA/LADe-serializerDecoder

Parallel Data

Clock/Datarecovery

Flip-chipbonding

REFclock

PLL and clock generator

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2.52.5--Gbps Serializer ArchitectureGbps Serializer Architecture

Word clock (125MHz)

SR1

SR2

SR3

SR4

Load clk(125MHz)

Latch

Latch

Mux1

Mux2 Latch

Mux3

Half bit clk(625MHz) Bit clk

(1.25GHz)

Bits 1,3,5,7,9,11,13,15,17,19

Bits 2,4,6,8,10,12,14,16,18,20

(1,5,9,13,17)

(3,7,11,15,19)

(2,6,10,14,18)

(4,8,12,16,20)

20-bitWord Latch

Shift registers

Ref_clk

20bit

5 bit

5 bit

5 bit

5 bit

Serialoutput

PLL &Clk generator

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PLL and Clock GeneratorPLL and Clock Generator

2020

PhasePhase--Locked LoopLocked Loop

SelfSelf--biasing structure [1]biasing structure [1]•• Remove process technology and environmental Remove process technology and environmental

variability, low input tracking jitter, Wide variability, low input tracking jitter, Wide operating frequency rangeoperating frequency range

PhasePhase--frequency detector frequency detector •• with equal short duration output pulses for inwith equal short duration output pulses for in--

phase inputsphase inputs

ChargeCharge--pump with symmetric loadpump with symmetric loadVCO with differential buffer delay stage with VCO with differential buffer delay stage with symmetric loadssymmetric loadsLoop filterLoop filter

[1] J. G. Maneatis, “low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE JSCC, Vol. 31, No. 11, Nov. 1996.

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PLL LayoutPLL Layout

Charge Pump1

Charge Pump2

VCOdiv4

div5

PFD S2D

D2S Bias Gen

startup

vddgnd

Vcntrl1Vcntrl2

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Serializer LayoutSerializer Layout

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Serializer + PLL & Clock GeneratorSerializer + PLL & Clock Generator

Serializer Clk generator PLL

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1.25GHz PLL Simulation Results1.25GHz PLL Simulation Results

Lock time=1.5us

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Clock Generator Output @ 1.25GHzClock Generator Output @ 1.25GHz

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Serializer Simulation at 2.5Serializer Simulation at 2.5--GbpsGbps

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Clock generator simulation Clock generator simulation @ 1.6GHz@ 1.6GHz

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Serializer Simulation Serializer Simulation @ 3.2Gpbs@ 3.2Gpbs

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ConclusionConclusion

Dedicated test Chip lab has been tested and Dedicated test Chip lab has been tested and fabricatedfabricated

Lab and radiation testing is in progressLab and radiation testing is in progress

LinkLink--onon--Chip serializer and PLL & clock Chip serializer and PLL & clock generator components are completed.generator components are completed.

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AcknowledgementAcknowledgement

Paulo Moreira at CERNPaulo Moreira at CERN--EP/MIC for EP/MIC for sharing GOL link design and many sharing GOL link design and many useful discussionsuseful discussionsPeregrine for sharing the cost of the Peregrine for sharing the cost of the chip fabricationchip fabrication

Thank You!Thank You!