SILICIDES ARE NOT SILLY!

Mehul C. Raval – Doctorate Student, NCPRE

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Outline Importance of silicides in VLSI Properties of important silicides Advantages of NiSi Phase diagram of Ni silicide Properties of different Ni silicides Annealing conditions for NiSi formation Ni silicide in solar cells Fabrication of Ni seed layer for solar cell

metallization

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Silicides in VLSI Almost all metals in periodic table react with

Si to silicides with general formula ‘MxSiy’. Silicides have ‘metal-like’ properties.

Silicides

Refractory Metal Silicides

TiSi2, WSi

Near-Noble Metal Silicides

PtSi, CoSi2

Rare Earth Metal Silcides

ErSi2

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Early use of silicides to make contact for Schottky diodes*.

Interconnects made from WSi2 silicides had reduced line resistance**.

Gate length, junction depth and contact surface are important parameters for CMOS transistors.

Miniaturization below 0.5 µm would require technological changes in the transistor itself.

Self-Aligned silicides (SALICIDE) play an important role for contact formation.

* - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & Mikael Östling, 2003.** - Simply irresistible silicides,Karen Maex, Physics World November 1995.

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Figure. SALICIDE Formation Process Flow*

* - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & Mikael Östling, 2003.

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Figure. Cross-section of a MOSFET*

* - Simply irresistible silicides,Karen Maex, Physics World November 1995.

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Properties of important silicides *Silicide Formation

Temp(°C)ρ(µΩcm) ФB(eV) Dominating

Diffusion species

Si consumed/nm of metal(nm)

C49 TiSi2 350-700 60-80 - Si -

C54TiSi2 750 15-20 0.6 Si 2.3

Co2Si 350 110 - Co 0.9

CoSi 375 147 0.68 Si 1.8

CoSi2 600-700 15-20 0.64 Co 3.6

NiSi 350-750 10.5-15 0.65 Ni 1.8

NiSi2 750-1000 34 0.66 Ni 3.6

Pd2Si 200-500 25-35 - - 0.7

• Limitations of CoSi2:** - Rise in resistance for narrow lines. - Reduction in available Si for reaction. - Introduction of Si-Ge substrates.

• Limitations of TiSi2:*** - As dimensions reduce, temp for C49 to C54 change ↑. - Max temp to prevent agglomeration ↓. - Junction leakage due to ↑ Si consumption.

* - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & Mikael Östling, 2003.** - Chapter 5, Silicide Technology for IC, Lih J. Chen,2004.*** - Chapter 3, Silicide Technology for IC, Lih J. Chen,2004.

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Advantages of NiSi *

Reduced Thermal Budget - As NiSi forms at low temperatures.

Lower Resistivity. Reduced Si consumption – Due to reduced

resistivity and decreased Si consumption. Silicide formation controlled by Ni diffusion –

Important to avoid bridging at edges of gates.

* - Chapter 5, Silicide Technology for Integrated Circuits, Lih J. Chen,2004.

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Phase Diagram of Ni Silicides

Figure. Illustrative Phase Diagram *

Liquid

100%A

100%B

Eutectic Point

(α + β) - Solid

α + Liquidβ + Liquid

α

βEutectic Line

Liquidus Line

Solid Solubility Line

Remains a solid solution here

Tie LineIsothermal Line

CL %CO %Cα %

X

Temp

eratur

e

Melting point of ‘A’

Melting point of ‘B’

* - http://www.southampton.ac.uk/~pasr1/index.htm

10Figure. Ni-Si Phase Diagram

Ni3SiNi2SiNi31Si12/Ni5Si2

Ni3Si2NiSiNiSi2

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Properties of Ni silcides

Figure. Ni silcide phase formation*

* - Silicides and ohmic contacts, J.P. Gambino & E.G. Colgan, Materials Chemistry and Physics 52 ( 1998) 99-146

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Phase Density(gm/cm^3

Silicide t / Ni t

Si consumed t / Ni t

ρ(µΩcm) Melting Point(°C)

Ni 8.91 1 0 7-10 1455

Ni3Si 7.87 1.31 0.61 80-90 1035/1170

Ni2Si 7.51 1.47 0.91 24-30 1255/1306

Ni3Si2 6.71 1.75 1.22 60-70 830/845

NiSi 5.97 2.2 1.83 10.5-18 992

NiSi2 4.8 3.61 3.66 34-50 981/993

Si 2.33 - - Dopant dependent

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Table. Properties of different Ni silicides*

• For 15 nm Si on poly-Si, Ni31Si12/ strained Ni2Si was observed for annealing at 200°C and Ni3Si2 observed between 300°C-400°C.*

* - Chapter 5, Silicide Technology for Integrated Circuits, Lih J. Chen,2004.

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Annealing Conditions for NiSi Ni

Thickness(nm)Substrate Doping(cm^

-3)Anneal Conditions

°C s AmbientSilicide Phase

Additional Information

Ref

20 350nm poly-Si on p-type (100)

P- 8 x 10^20 400 30 N2 NiSi Silicide thickness = 40nm

1

25 Si(100) - 500 30 Vacuum NiSi Silicide thickness = 50nm

2

12 Si(001) - 400 600 - NiSi, epi NiSi2

Ni2Si is not observed

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20 N-type Si(100) 1.6-2.1 Ω-cm

- 350 1800 Vacuum NiSi Silcide 35nm to 40nm thick

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10 Si(100) - 300 30 He Ni2Si 5

10 Si(100) As & B doped

300-340

30 He NiSi Excessive silicidation at

edges

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10 Si(100) As & B doped

364 Spike He NiSi 5

10 Si(100) As 270 30 He Ni2Si -> NiSi

RTP2 – 450°C, 30s.No excessive silicidation

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125 n-type Si(100) As- 2 x 10^20 cm^-3

550 30 N2 NiSi Ramp Up – 80°C/s, Down- 25°C/s. NiSi initiates from 400C

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12 -do- -do- 450 30 N2 NiSi -do- 6

50 -do- -do- & P- 10^15 cm^-3

500 30 N2 NiSi -do-, Also for p-type B doped.

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Ni Thickness(nm)

Substrate Doping(cm^-

3)

Anneal Conditions(°C) s Ambient

Contact Resistivity,ρc(Ω-sq.cm)

Comments Ref

20 N-type Si(100)

n-type : 2

x 10^20 cm^-3

350 1800 Vacuum 4.2 x 10^-8 4

20 P-type Si(100)

p-type: 1 x

10^20 cm^-3.

350 1800 Vacuum 7 X 10^-8 4

20-40 P+ Poly-Si

B: 2 x 10 ^ 20

600 30 - 3 x 10^-9 Contact Area = 1 µ sq.m

Assumption – L < 0.5 LT

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20-40 N+ Poly Si

As: 2 x 10^20

600 30 - 4 x 10^-9 -do- 7

10 N-type 10 X 10^19 cm^-3

300470

4343

< 10^-8 2-step anneal 8

Table. Contact Resistivity Data for NiSi

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Ni Thickness(nm) Anneal Temperature(°C)

Anneal Time(s)

10-12 300-350 30 to 600

20-50 400-500 30 to 1800

> 100 550 30

Figure. Variation of ρc for NiSi with doping concentration [8]

Table. Variation of Annealing Conditions for varying Ni thickness

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Ni silicide in solar cells

Ni Thickness(nm)

Bath Anneal Conditions(°C,s)

FF(%) Rs(Ω-sq.cm)

Rsh(Ω-sq.cm)

ρc(Ω-sq.cm)

Ref

30-40 EN,pH: 9 to 11,T < 60 s,

- 78.2 0.36 15000 - 9

145 ± 20 EN,pH: 8 to 10, T- 75°C-90°C

350°C-750°C

- - - 6m 10

- EN 400°C 79.8 0.64 - 3.5 x 10^-5

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1000 LIP 300°C 75.6 0.9 - - 12

6000-8000 EN, pH- 8 to 10, T = 95°C

410°C, 60s 72.4 0.32 9m 13

Table. Ni seed layer conditions with solar cell metallization properties

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Fabrication of Ni seed layer for solar cells

a) b)

Figure. Electroless plated Ni from alkaline bath a) 45 and b) 30 s deposition

• For 100nm seed layer, annealing to be done at 550°C for 30 s.• For 50nm seed layer, annealing to be done at 500°C for 30s.• TLM samples will be prepared for ρc calculation, target < 2mΩ sq.cm.• Silicide phase to be determined via XPS.

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References:

1) Analysis of Resistance Behavior in Ti-and Ni-Salicided Polysilicon Films, Tatsuya

Ohguro, et.al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 12,1994.

2) In situ real-time studies of nickel silicide phase formation, M. Tinani, et.al, J. Vac. Sci.

Technol. B 19 2 , March – April 2001. 3) In situ transmission electron microscopy study of Ni silicide phases formed on 001 Si active lines, V. Teodorescu, et.al, J. Appl. Phys., Vol. 90, No. 1, 1 July 2001.

4) Electrical Properties and Solid-Phase Reactions in Ni/Si(100) Contacts, Yoshinori

TSUCHIYA, et. al, Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 2450–2454.

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(1998) 143–150.

7) A Self- Aligned Emitter Base Nisi Electrode Technology for Advanced High-speed Bipolar

LSIs, T. linuma, et. al, IEEE 1992 Bipolar Circuits and Technology Meeting 4.4.

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Hamburg, September 2009.

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