SiLC (Silicon tracking for the International Linear Collider)

http://silc.in2p3.fr

H.J.Kim (KyungPook National U.)

on behalf of the SILC R&D Collaboration

(major transpariencies from Aurore Savoy-Navarro)

OutlineOutlineThe CollaborationGoalsThe R&D activities ¤¤ R&D on sensors ¤¤ R&D on electronics ¤¤ R&D on MechanicsThe tools >>>> Alignment(s) & calibrations >> Lab test benches >>>> Test beams >>>> Simulations

The SILC R&D CollaborationThe SILC R&D Collaboration

U.S.AU.S.A

Michigan U. Michigan U. SCIPP-UCSCSCIPP-UCSC

EuropeEurope

IMB-CSIC, Barcelone (SP)IMB-CSIC, Barcelone (SP)Geneva U, Geneve (CH)Geneva U, Geneve (CH)

Helsinki U. (Fi)Helsinki U. (Fi)IEKP, Karlsuhe U. (D)IEKP, Karlsuhe U. (D)

Moscow St. U. , Moscou(Ru)Moscow St. U. , Moscou(Ru)Obninsk St. U., Obninsk (Ru)Obninsk St. U., Obninsk (Ru)

LPNHE, Paris (Fr)LPNHE, Paris (Fr)INFN-Pisa, Pisa (It)INFN-Pisa, Pisa (It)

Charles U. , Prague (CZ)Charles U. , Prague (CZ)Roma 1, La Sapienza (It)Roma 1, La Sapienza (It)

IFCA, Santander(Sp)IFCA, Santander(Sp)Torino U., Torino (It)Torino U., Torino (It)

IHEP, Academy Sci., Vienna (Au)IHEP, Academy Sci., Vienna (Au)

AsiaAsia

Kyungpook U. Taegu, KoKyungpook U. Taegu, KoKorea U. Seoul, KoKorea U. Seoul, Ko

Seoul Nat. U., Seoul, KoSeoul Nat. U., Seoul, KoTokyo U. (Japan)Tokyo U. (Japan)

HAMAMATSU (Japan)HAMAMATSU (Japan)Close connections:

FNAL (DOE prop 05)UCSC, FNAL, LPNHE SLAC (DOE prop 03:funded): UCSC, SLACMichigan U, LPNHE

and meetings

Launched January 2002, Proposal to the PRC May 2003, Status Report May 2005Several contracts of collaborations between Institutes, ex:

HPRN-CT-2002-00292, CICYT-IN2P3, IN2P3-Hamamatsu, DOE proposals, EUDET

85 participants

R&D GoalsR&D Goals

• Very high precision on momentum and spatial measurements• Full coverage• Low material budget• Robustness• Easy to build and to work with• Low cost

SiLC is a generic R&D collaboration to develop the next generation of large area Silicon Detectors for the ILC; It applies to all the detector

concepts and indeed gathers teams from all 3 detector concepts:

In all 3 detector concepts Si tracking plays an essential role SILC R&D offers a unique framework to compare tracking performances

between the various detector concepts. Main difference between the detector concepts = tracking system

SiDGLD

LDC

LDC

R&D on SensorsR&D on Sensors

Silicon strips are the baseline with:Silicon strips are the baseline with:• Larger size wafers• Thinner/Thinning• Smaller pitch• High yield• Eventually different shapes

Possibility to use new technos in some regions:Possibility to use new technos in some regions: From ‘standard’ pixels of 50µ x 300µ to new Pixel technos: FPCCD, DEPFET, MAPS/FAPS, SOI …

First Prototype on Si strips of different lengthFirst Prototype on Si strips of different length

VA64_hdrTsh=3.7µs

28cm x N=1,4 Built by Geneva U., ETH Zurich & Pariswith AMS technique

Courtesy G.Ambrosi(Perrugia)

‘’Serpentine technique’’

recto/verso

Signal over noise as a function of strip length

Signal spectrum is summed over a cluster after pedestal and common mode subtraction.

The radioactive source is aSr90-Y90 beta source.

The S/N measurements were achievedon variable length strips with the prototype

at Paris test bench

sensorto be measured

Results see next slide

Results on S/N Results on S/N Collaboration Paris-Prague New

L=28cm, S/N(MPV)=2020or S/N(Mean)=30

L=56cm, S/N(MPV)=12or S/N(Mean)=18

Cluster size~2

Noise vs capa

Next steps: Change detector & FE prototypesgo to test beam

Some other S/N measurements and/or Some other S/N measurements and/or computationscomputations

Nomad experiment: results from beam tests on S/N with same sensors and VA1 FE chips

These results and the ones we have obtained are confirmingthat 30 cm long strips have S/N greater than 20, and 60 cm long strips have S/N greater than 10.

Nota bene: These results are of course dependent of the detector prototype and the associated F.E.E.

Curve computed with the

known parametersof VA_64hdr

2) Development of fabrication line for new sensors2) Development of fabrication line for new sensors

Several Institutions in SILC(also Helsinki U.) are developing new

sensor research lines Such facilities are very usefull for developing& testing new ideas and transfer to Industry.

For large production, high quality and reliability: HAMAMATSU Monopoly

Ex1: 5’’ DSSD fab. line in Korean U.Ex2: rad hard sensor techno at IMB-CNM

J.Lee’s talk

3) Process Quality Control and sensor characterization3) Process Quality Control and sensor characterization

Self-made chuck and probe card support

Semi-automatic sensorprobe station for qualityControl: system overview

Process control scheme: Test structure

(Vienna, Karlsruhe, Korea, Helsinki, Pisa ….)

Test of 10 Hamamatsu det.S8743 (GLAST)

8.9500+/-20 x idem µmStrip pitch: 228µmNb of strips: 384

(done @Vienna PQC set up )

Developing new sensorsTest of production

Essential forEssential for

Longer term prospects on the R&D on sensors

• To develop Si strip wafers single sided of at least 8’’, with readout pitch of 50µm, as thin as possible, and with high yield (>50%)

• To develop ‘’thinning’’ technique in order to get at least 2:1 reduction in thickness (already underway)

• To develop double sided wafers of at least 6’’, and with high yield (>50%)• Keep in mind some of the µvertex technologies for certain parts of the

Si tracking system.• New way(s) to connect electronic on detector with strips (connectics)

Objectives:

To develop R&D sensors fab line in Research Laboratories in order to develop ideas as listed above, and later on, to transfer technology to Industrial firm(s).

Presently, HAMAMATSU is THE firm able to produce large amounts of detectors in the most reliable way; Will this continue in the future?

R&D on ElectronicsThe Si tracking system: a few 100m2, a few 106 stripsEvents tagged every bunch (300ns) during the overall train (1 ms)Data taking/pre-processing ~ 200 msOccupancy: < a few %

Goals:Goals:Low noise preamplifiers

Shaping time (from 0.5 to 5 µs,depending the strip length)

Analogue samplingHighly shared ADC

Digitization @ sparsification Very low power dissipation

Power cyclingCompact and transparent

First LPNHE prototypeFirst LPNHE prototypefulfills most of these fulfills most of these

goalsgoals

NEW!!NEW!!

Two designsTwo designs

SCIPP-UCSC: Double-comparator discrimination system

Improve spatial resolution (25%) Next foundry: May 9.

LPNHE-Paris:Analogue sampling+A/D,

including sparsification on sums of 3 adjacent strips.

Deep sub micron CMOS techno.First chip successfully submitted

and now under testNext version: in progress

LPNHE chip: layout results & testsLPNHE chip: layout results & tests

3 mm

1.6

mm

Shaper: simu vs measurement

the layout: 16 +1 ch.(Nov 04) the chip (Feb 05) the test board

VERY ENCOURAGING FIRST RESULTSVERY ENCOURAGING FIRST RESULTS

Lab test benchesLab test benches

Pb Pb

reference sensor

sensor

90Sr source

Dark box

S/N ~ 10.

In most Labs:LD & radioactiveSource (ex: Paris & Korea)

Paris test bench

Korean test bench

sigma=14.4±0.2

J.Lee’s talk

Test beams: GoalsTest beams: Goals

To qualify in conditions closest to the real life: prototypes of detectors (including New Si technologies) and of the associated FE and readout electronics.

Detection efficiency vs operational parameters Spatial resolution, cluster size Signal/Bruit Effect of magnetic field (Lorenz angle determination) Angular scans, bias scans Integration with other sub-detectors Alignment Cooling (including power cycling) In the specific & new ILC conditions.

Foreseen beams

1T, 6 GeV e- beam

5T cosmiques, laser

Bonn electron 3.5 GeV

Others:

CERN, FNAL,

KEK

(Korean

colleagues)

Participants: All + FNAL

Using the test beam setup in Bonn

beam

BAT 1 2 3 4Szintillator Szintillator3 x 3 mm²

ATLAS Diamond

T riggerL ogicU nit

coincidence

trigger busy

Si tracker

Prototype

Collaboration with DEPFET(under preparation)

Detector Prototypes:Detector Prototypes:Support mobile

• Design (just started)• Fabrication• Assembling & Mounting Module with 3 sensors Module with 2 sensors

Second layer partly covering the first one.

Total of 60 trapezoidal sensors,

About 10 K readout channelsReady by end 2006/beg. 2007Other prototypes: Ladders of

different sizes and sensors

Forward Prototype:under CAD study

Schedule & Financing

0706

Construction barrel pototypeTests (cont’d) also combined withOther sub detectorsNew foundry (>=512 ch + techno)

Beam tests: elementary modulesconstruction protoForward Chips 128 ch.

Preparationstests Proto1

EUDET (I3 EU project) foresees for Si-tracking in JRA2, the financing of: Part of the chips (2 submissions) & large number of channels Protos large dimension: a part of the Si central & Si forward trackers Protos alignment Protos cooling

An R&D activity on a new scale is starting within SiLC when going to test beams.

08 09now

Bonn

SiLC R&D proposal was presented to the PRC on May 2003Goal: to develop the next generation of large area Si trackers suited for

performing very high precision measurements in spatial position and momentum at the ILC,

All R&D aspects, on sensors, electronics and mechanics are addressed.All needed tools: simulations, Lab test benches, test beams,

alignment and calibration are being developed

Highlights/important progress these last 2 years:Work on sensors: characterization of strips of variable length,

development of fab linesFE electronics in deep submicron CMOS techno

Developing Lab test bench for highly precise measurementsCAD of all the tracking components, for both LDC (Si Envelope) & SiD

Thermo mechanical studies

NOW:Preparing for test beams and getting even closer to the real life conditions.The collaboration is getting speed and established close contacts with all

3 detector concepts Keeping synergy with LHC (SuperLHC).

Next step: going to 128 channelswith analogue sampling included;

second chip prototype currently under design, foreseen submission Fall 05.Will equip the test beam prototypes

Second Parigi prototype is underway Second Parigi prototype is underway

Longer term prospects for the FE readout chip and processing of the Si-tracking information

• Higher multiplexing factor for A/D, at least 512:1, possibly 1024:1• Go to deeper DSM techno (90 nm)• Try SiGe techno for analogue part of the FE chip• Work out packaging, output of signal and cabling issues: following last

developments on those topics• Develop upper stages of the readout and of the data processing for the Si-

trackers:

>> Clusterization to improve the position resolution

>> track reconstruction (track segments)• and their inclusion in the overall data flow architecture.• Study the time information provided by those detectors (shorter shaping time

possibility)• Stay in close contact with/participate to the new developments for the SLHC

tracking.• Tests prototypes on Lab test bench but also on more real life set ups= use

them for the readout of prototype detectors in test beams.

A systematic work is underway on an electronic test bench to fully characterizethe 40 first prototyped chips: amplifier gain, linearity, dynamic range, noise,

power dissipation; The power cycling will also be experienced.All the results are compared with simulations performed before sending for

foundry as well as post simulations.As an example here below the results on the noise

By courtesy of Jean Francois Genat