SiC Overview - Agarwal

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Progress in Silicon Carbide Power Devices Anant Agarwal, Mrinal Das, Brett Hull, Sumi Krishnaswami, John Palmour, James Richmond, Sei-Hyung Ryu, Jon Zhang Cree Inc., 4600 Silicon Dr., Durham, NC 27703, USA [email protected], (919) 313-5539 ABSTRACT SiC materials and device technology has entered a new era with the commercialization and acceptance of 600 V/10 A and 1200 V/10 A Schottky Barrier Diodes (SBDs) in the marketplace. These diodes are finding applications in the Power Factor Correction (PFC) stage of Switch Mode Power Supplies (SMPS). SiC power MOSFETs with ratings of 800-1200 V up to 10 A will soon be commercially available. The next step is to integrate the SiC MOSFET and Schottky diodes in a power module for PFC and motor control applications. For high temperature applications, greater than 2000C, a bipolar switch such as a SiC BJT offers superior performance over the MOSFETs. The lack of gate oxide in the BJT offers better reliability at such extreme temperatures, in addition to the lowest combined switching and conduction losses. INTRODUCTION SiC offers an opportunity to replace Si PiN diodes and IGBTs with SiC Schottky diodes and MOSFETs, respectively, up to about 3000 V. The combination of SiC Schottky diode and MOSFET will save approximately 60-80% of switching losses resulting in an efficiency improvement of 4-6% points in a typical power electronic system. In addition, cooling requirements will be substantially reduced in direct proportion to the reduction in losses. SiC MOSFET can operate reliably up to junction temperatures of 2000C. However, for operation above 2000C, SiC BJTs are an excellent choice. 1200 V SiC MOSFETs The 4H-SiC DMOSFET structure is shown in Fig. 1. The MOS channel length is defined by the p-well and n+ implants, and can range from 0.5 ptm to 1.5 ptm. Electrons flow laterally from the n+ source through an inversion layer across the implanted p-well, then flow vertically through the JFET region formed by two adjacent p-well regions, and then through the lightly doped n- drift region into the drain. The blocking voltage of the MOSFET is determined by the doping concentration and thickness of the n- epilayer. For 1200 V devices, an epilayer with a doping concentration of 6x1015 cm-3 and a thickness of 12 ptm can be used. A thermally grown oxide layer is typically used as gate dielectric due to its repeatability and stability. Typically, the gate oxide is nitrided in NO or N2O to reduce MOS interface state density, which improves the transconductance of the MOSFET. source gate source Figure 2 shows the on-state I-V characteristics of a 1.8 kV s. 4H-SiC DMOSFET. The device has a 500 A thick gate oxide. P+ N+ JP-wel N+ p+ The gate oxide electric field was limited to approximately 3 MV/cm (Vgs = 15 V). The active area of this device is 0.0936 cm2. An on-resistance of 85 mQ (Ron,sp = 8 mQ-cm2), and a drain n- epilayer current of 50 A (534 A/cm2) at a forward drop of 5.7 V were measured at room temperature. At an operating temperature of 1500C, the on-resistance increases to 100 mQ (9.4 mQ-cm2). A N+4H-SiC substrate slight negative shift in MOS threshold voltage at elevated temperatures decreases the MOS channel resistance at a fixed drain gate bias. This cancels out, to some extent, the increase in drift Fig. 1. Simplified cross-section of the SiC layer resistance, resulting in temperature stable on-resistance. DMOSFET. Figure 3 shows the blocking characteristics of the 4H-SiC DMOSFET. The device is normally off, and showed stable avalanche characteristics at a VDS of 1.8 kV with a VGS of 0 V. The biggest challenge in the commercialization of 4H-SiC MOSFET is control of the threshold voltage due to the presence of high positive charge in the oxide (QF - 2E12 cm 2). The room temperature 0-7803-9749-5/06/$20.00 ©2006 IEEE 155

Transcript of SiC Overview - Agarwal

Page 1: SiC Overview - Agarwal

Progress in Silicon Carbide Power Devices

Anant Agarwal, Mrinal Das, Brett Hull, Sumi Krishnaswami,John Palmour, James Richmond, Sei-Hyung Ryu, Jon Zhang

Cree Inc., 4600 Silicon Dr., Durham, NC 27703, [email protected], (919) 313-5539

ABSTRACTSiC materials and device technology has entered a new era with the commercialization and

acceptance of 600 V/10 A and 1200 V/10 A Schottky Barrier Diodes (SBDs) in the marketplace. Thesediodes are finding applications in the Power Factor Correction (PFC) stage of Switch Mode PowerSupplies (SMPS). SiC power MOSFETs with ratings of 800-1200 V up to 10 A will soon be commerciallyavailable. The next step is to integrate the SiC MOSFET and Schottky diodes in a power module for PFCand motor control applications. For high temperature applications, greater than 2000C, a bipolar switchsuch as a SiC BJT offers superior performance over the MOSFETs. The lack of gate oxide in the BJToffers better reliability at such extreme temperatures, in addition to the lowest combined switching andconduction losses.

INTRODUCTIONSiC offers an opportunity to replace Si PiN diodes and IGBTs with SiC Schottky diodes and

MOSFETs, respectively, up to about 3000 V. The combination of SiC Schottky diode and MOSFET willsave approximately 60-80% of switching losses resulting in an efficiency improvement of 4-6% points in atypical power electronic system. In addition, cooling requirements will be substantially reduced in directproportion to the reduction in losses. SiC MOSFET can operate reliably up to junction temperatures of2000C. However, for operation above 2000C, SiC BJTs are an excellent choice.

1200 V SiC MOSFETsThe 4H-SiC DMOSFET structure is shown in Fig. 1. The MOS channel length is defined by the p-well

and n+ implants, and can range from 0.5 ptm to 1.5 ptm. Electrons flow laterally from the n+ source throughan inversion layer across the implanted p-well, then flow vertically through the JFET region formed by twoadjacent p-well regions, and then through the lightly doped n- drift region into the drain. The blockingvoltage of the MOSFET is determined by the doping concentration and thickness of the n- epilayer. For1200 V devices, an epilayer with a doping concentration of 6x1015 cm-3 and a thickness of 12 ptm can beused. A thermally grown oxide layer is typically used as gate dielectric due to its repeatability and stability.Typically, the gate oxide is nitrided in NO or N2O to reduce MOS interface state density, which improvesthe transconductance of the MOSFET. source gate source

Figure 2 shows the on-state I-V characteristics of a 1.8 kV s.4H-SiC DMOSFET. The device has a 500 A thick gate oxide. P+ N+ JP-wel N+ p+

The gate oxide electric field was limited to approximately 3MV/cm (Vgs = 15 V). The active area of this device is 0.0936 cm2.An on-resistance of 85 mQ (Ron,sp = 8 mQ-cm2), and a drain n- epilayercurrent of 50 A (534 A/cm2) at a forward drop of 5.7 V weremeasured at room temperature. At an operating temperature of1500C, the on-resistance increases to 100 mQ (9.4 mQ-cm2). A N+4H-SiC substrateslight negative shift in MOS threshold voltage at elevatedtemperatures decreases the MOS channel resistance at a fixed draingate bias. This cancels out, to some extent, the increase in drift Fig. 1. Simplified cross-section of the SiClayer resistance, resulting in temperature stable on-resistance. DMOSFET.Figure 3 shows the blocking characteristics of the 4H-SiCDMOSFET. The device is normally off, and showed stable avalanche characteristics at a VDS of 1.8 kVwith a VGSof 0 V.

The biggest challenge in the commercialization of 4H-SiC MOSFET is control of the threshold voltagedue to the presence of high positive charge in the oxide (QF - 2E12 cm 2). The room temperature

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threshold voltage is approximately 3.5 V, which decreases to 2.2 V at 1500C. However, for powerswitches, the drain current should be less than 1 [tA in off-state. At this drain current, the gate biasneeded to keep the device at off-state is very close to zero, about 1.55 V at room temperature and 1.05 Vat 1500C (Fig. 4). Any small glitch in the gate drive can turn the device on, resulting in a 'normally-on'device. Therefore, a more positive low current Vth is desired for stable operation and to ensure a 'normallyoff' device.

60 20 . . .0 I . . . . . . . .0..,'''' 0.1

50 [email protected] BV = 1.8 kV-| 0.01Vg=15V 15 1 E-3

40-RoomDtem Slo -

1E-4 VDS =5 my~30 <AoLm 1 1E-5

vg=OV olE-6-20 Vg=S D V a t Room temp5 IE-7

-0150 Oc10 1E-8

Vg=5V o 1E-90_

0 1 2 3 4 5 60 1 23 4 5 6 7 200 400 600 800 1000 1200 1400 1600 1800 2000 VGS (V)

VDS (V) VDS (V)Fig. 2. On-state characteristics of a 0.0936 Fig. 3. Blocking characteristics of a 0.0936 Fig. 4. Sub-threshold behavior of acm2SiC DMOSFET at room temperature. cm2SiC DMOSFET at room temperature. 0.0936 cm2 4H-SiC DMOSFET.

Inversion layer mobility of the SiC MOSFET is yet another area where considerable improvement isneeded. Significant effort has been focused on improving the channel mobility ([tch) in lateral MOSFETs.Some of the important factors known to reduce the channel mobility are: (a) high interface trap charge,Dit, (b) high fixed oxide charge, QF, and (c) poor surface morphology in the channel of the device due toion implantation and high temperature activation. High value of Dit near the conduction band has beensteadily improved by introducing nitrogen, either from NO or N20, at the SiC-SiO2 interface. Nitric oxide(NO) anneals at 1 1 750C have lowered Dit to 1-5E1 1 eV1cm2 and increased the ptch from single digits to-30 cm2N-s in lateral MOSFETs [1]. However, in the vertical devices, the channel mobility is stillsomewhat low, less than 20 due to the high doping of theimplanted p-wells. 60

Several groups have demonstrated even higher tch ( -150 ReOx2 50 NO_ _ _ _ _ _ _cm N-s) in lateral MOSFETs by oxidizing in an environment 5 NO

containing metallic impurities [2-4]. However, non-idealities in N_ 40 _iE_*the oxidation process resulted in enhanced oxide thickness (>1500 A), and incompatibility with high temperature processing 2 Al

like ohmic contact anneals. Recently, Das et. al demonstrated 2an optimized Metal Enhanced Oxidation (MEO) process which _produced acceptable gate oxide thickness (- 600 to 900 A). iL 10While, QF and Dit values for the MEO gate oxide wascomparable to that of the conventional NO annealed oxide, A4 0 4 8 12 16 20the inversion layer mobility of the MEO MOSFET with GateVoltage (V)implanted p-wells increased to 48 cm2IV-s at Vgs of 20 V, a Fig. 5. Channel mobility versus gate voltage for

* g ~~~~~~~~~~~~MEOand NO MOSFETs formed on 1 x 1018 cm340% increase from the NO process [4]. This would translate in Al nd channel.to a mobility of 30-35 in the vertical DMOSFET, which is mplanted channel.

sufficient for production. A comparison of channel mobility as a function of gate voltage for three differentoxidation processes is shown in Fig. 5 for a lateral MOSFET with Al implanted channel. While the NOprocess is immediately available for the MOSFET fabrication, the MEO requires further optimization toremove unwanted metal species from the gate oxide. Successful isolation of the relevant MEO specie(s)will enable the next generation of high performance SiC MOS devices.

Further improvement in mobility is possible by reducing the surface roughness occurring duringimplantation and high temperature anneals. Capped activation anneals with graphitized resist has provento be beneficial in reducing the surface roughness. Incorporation of capped anneal process in thefabrication will also help in a more reliable and robust MOSFET device.

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SiC BIPOLAR JUNCTION TRANSISTORS 5 tm5 tm IO -tmThe cross-section of an NPN BJT is shown in Fig. 6. The

emitter, base and collector layers are all epitaxially grown in 1.5~tmone continuous growth run. The blocking layer for the 1200 V E17 3 J153 ~~~1~tm,2x1O cm- BBJT is 15 pim thick and doped at 4.8 x 1015 cm3 . The BJT chip N' Bconsists of alternating base and emitter fingers to form an Pinter-digitated structure. A double metal process was used.The active area of the device is 0.16 cm2. N, 15 tm, 4.8x1015 cm-3

Fig. 7 shows the forward I-V characteristics of the BJT in P+GRs P+GRsthe common emitter mode at room temperature. The deviceconducts 20 A at a forward voltage of 0.57 V and at IB of 600 N+, 4HSiCmA. The measured specific on-resistance is 4.6 mQ-cm2 The ccurrent gain of the device is 45. Forward blocking Fig. 6. Cross-section of 1200 V SiC BJT.characteristics in the common emitter mode is shown in Fig. 8.The device shows avalanche behavior and blocks 1350 V at a leakage current of 50 pIA.

One of the major challenges today in the commercialization of SiC BJTs is the phenomenon of currentgain instability. Recently, current gain degradation was observed in 4H-SiC BJTs [5]. The degradationcauses the current gain to decrease and the on-resistance to increase with time. This degradationbehavior in a 1200 V SiC BJT is shown in Figs. 9(a) and 9(b).

20 1 .E-04

18 - IB=50Omk RT 9.E-05

16 - -_45 L e 8E-05 -X--E I = 400mA514 - _ - 7.E-05 50 A at 1350 VD 12 - 6.E-05

10 - -- B --mA 5.E-05 - %X

8 D 4.E-05 - t --t0

o 6 t t --t - 20 mA2 3.E-05nA A4-2.E-05

2 'IB 100mA 1.E-05="t I~~~~~~~~~~~'= O mA|l

0 O.E+00

0 1 2 3 4 5 6 7 8 9 10 11 12 0 200 400 600 800 1000 1200 1400 1600

Collector Voltage (volts) Collector voltage (volts)Fig. 7. Forward I-V characteristics of the 0.16 cm2 4H-SiC BJT. Fig. 8. Blocking capability of the 0.16 cm2 4H-SiC BJT.

The output characteristics of the BJT device in common emitter mode before any stress is shown inFig. 9(a). The transistor conducts 10 A of collector current at VCE = 1.4 V and IB = 500 mA. After the initialmeasurement, the device was stressed at 10 A for a given amount of time. The device was powereddown, allowed to cool and then the output characteristics were recorded each time. One can observe thatthe current gain has decreased from 30 to 15, by almost 50%, after about 16 hrs of stress (Fig. 9(b)). Inaddition, the on-resistance of the device in the saturation region has also increased.

The origin of this current gain instability in SiC BJTs is still not very clear. One speculation is that thedegradation could be due to the generation and growth of stacking faults in the base of the transistor (Fig.10). This is similar to what is observed in the drift layer of a SiC PiN diode causing the forward voltagedrop to drift. In the PiN diodes, the energy for this expansion of the stacking fault comes from theelectron-hole recombination in the conductivity modulated drift layer. This results in reduction of theminority carrier lifetime, reducing the conductivity modulation in the immediate vicinity of the stackingfault, leading to an increase in Vf. Concurrently, in the BJTs, the base of the transistor gets flooded withelectron-hole pairs during the operation of the device. The recombination of electron-hole pairs in thebase can give rise to stacking faults, which can then reduce the lifetime of the minority carriers locally inthe base, resulting in the reduced current gain. The reduction in current gain can also explain theincrease in the on-resistance of the BJT in the saturation region since not many carriers make it acrossthe base into the collector.

Another possible mechanism for the current gain degradation could be similar to what has beenobserved in AlGaAs/GaAs Heterojunction Bipolar Transistors (HBTs) [6,7]. In these devices, when thegeometry was scaled down to improve the device performance, the current gain was found to drift withtime. The drift in the current gain was strongly influenced by the surface recombination effect due to the

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8 AT ok-B-4 8 1 L XR ++ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1, ;1 A

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0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10

Vce (Volts) Vce (Volts)

(a) (b)Fig. 9. Current gain degradation in SiC BJT with increasing cumulative stress at 10 A for 0 min and 16 hrs.

BI_l

CFig. 10 Stacking faults in the base result in reduced lifetime and DC current gain.

high surface recombination velocity in GaAs. In order to suppress the surface recombination effect, andtherefore the instability in the current gain, several device design and process controls were proposed.Among them the introduction of a thin depleted layer with wide-gap and lower surface recombinationvelocity, such as an AlGaAs passivating 'ledge', on to the extrinsic base was proven to be effective inreducing this behavior [7]. A similar effect may be responsible for current gain degradation in SiC BJTs.Whether it is the generation of stacking faults in the base or surface recombination current in the base-emitter region, the exact origin to the mechanism of current gain instability in SiC BJTs has to be firstunderstood before these devices can be commercialized.

ACKNOWLEDGEMENTThis research was funded through the Cooperative Agreement W911INF-04-2-0022 funded by the

Army Research Laboratory in Adelphi, Md and by TIA # FA8650-04-2-2410, funded by the Air ForceResearch Laboratory, in Dayton, Ohio.

REFERENCES

[1] M.K. Das, RecentAdvances in (0001) 4H-SiC MOS Device Technology, Materials Science Forum, Vol. 457-460 (2003), pp.1275-1280.

[2] H.O. Olafsson, Ph.D. Dissertation, Chalmers University (2004).[3] D. Alok, et al., US Patent and Trademark Office 6,559,068 (2003).[4] M. Das et. al, Improved 4H-SiC MOS Interfaces Produced via Two Independent Processes: Metal Enhanced Oxidation and13000°C NO Anneal, presented at IOSORM 2005.[5] A. Agarwal et. al, Influence of Basal Plane Dislocation Induced Stacking Faults on the Current Gain in SiC BJTs, presented atIOSORM, Pittsburgh, USA, Sept. 2005.[6] P. Ma et. al, InGaP/GaAs HBT Failure Mechanism Investigation and Reliability Enhancement, Report for MICRO Project 98-018,1999.[7] J-M. Lee et. al, Fabrication and Temperature-dependent characteristics of AIGaAs/GaAs Heterojunction Bipolar Transistors withan AlGaAs-Ledge Structure, J. Korean Physical Society, 40, pp. 320-324, 2002.

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