SHRI VISHNU ENGINEERING COLLEGE FOR WOMEN ...Design and ASIC Implemntation using CADENCE EDA...
Transcript of SHRI VISHNU ENGINEERING COLLEGE FOR WOMEN ...Design and ASIC Implemntation using CADENCE EDA...
A Five Day Workshop on “ Analog Intgrated Cicuit Design and ASIC Implementation using CADENCE EDA Tools” on 6-10,June,2016
SHRI VISHNU ENGINEERING COLLEGE FOR
WOMEN(Autonomous)::BHIMAVARAM
� Report A Five Day Workshop on “ Analog Intgrated Cicuit Design and ASIC Implementation using CADENCE EDA Tools” on 6-10,June,2016
Convenor: Dr.GRLVN Srinivasa Raju
Co-ordinators:� Mr.V .Srinivasa Rao Mr.M.Pradeep
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Shri Vishnu Engineering College for Women
(Autonomous) Bhimavaram-534 202
A REPORT
on
“A Five Day Workshop on “ Analog Intgrated Cicuit Design and ASIC Implemntation using CADENCE EDA Tools” on 6-10,June,2016.Under TEQIP-II for Faculty of SVECW and outside Engineering
Colleges, on 6-10,June,2016
Organized by
Department of Electronics and Communication
Engineering
About the Wokshop:
This workshop is intended for the broader academic community who seeks to explore
the impact of chip design in the industry and Academics. Workshop provides faculty with
a personalized experience that is rich with technical knowledge. This workshop covers
basic concepts of Chip design back end tools using Cadence.
The objectives of the program:
To provide a theoretical &practical introduction to Analog IC Design and ASIC
Implementation.
Drawing layouts and performing DRC
To draw simple circuits and perform simulation and RC Extraction using CADENCE
EDA Tools.
Course outline:
Topics Covered:
Introduction to Analog IC Design
Drawing Schematics
Analysis of OP-AMP Design
Hands on experience
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Inaugural Session:
On 6th
June, the proceedings began with inauguration ceremony, with the esteemed
presence of Honourable Principal Dr. G. Srinivasa Rao, Convenor & and HOD of ECE
Department Dr. G.R.L.V.N Srinivas Raju , along with coordinators Mr V.Srinivasa Rao &
Mr.M.Pradeep.
Principal of SVECW , Dr. P. Srinivasa Rao Delivered the welcome speech.Dr. G.R.L.V.N
Srinivas Raju, Head, Electronics and Communication Engineering Department, gave the
introductory speech about the schedule and key features of the Program. Coordinator of this
program Proposed vote of thanks for this Inaugural session.
Glimpses of Inauguration Ceremony:
GALLERY
Opening remarks by the Principal
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Opening Remarks by Resource Person
Opening Remarks by Convener
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Gathering for the workshop
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Hands on Experience at the Lab sessions
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Technical sessions (Schedule)
Date Timings Event
6/7/2016
9.30am-10.30am Inaugural Function
10.30am-10.45am Tea Break
10.45am-11.30am Introduction on CIC Design Flow and ASIC Design flow
11.30am-12.00am CIC Front End Lab Session
12.00am-1.00pm
Schematic capture And Simulation On- PDK Device Characterization – channel
resistance for NMOS and PMOS
Lab Session 1:Basic CMOS Inverter Schematic Capture and Simulation On -
Characterization of – Tpd, VOH, VIL, VOL, VIL, VSP
1.00pm-2.00pm Lunch Break
2.00pm-3.30pm Layout Extraction – Formulate the Standard Cell Layout Template
3.30pm-3.45pm Tea Break
3.45pm-5.00pm Physical Verification – DRC, LVS
Parasitic Extraction and Post Layout Simulation
7/7/2016
9.00am-11.00am
Fundamentals of Analog Signal Processing – CMOS Amplifier Topologies and
Performance- Review of the generic amplifier performance parameters – Gain,
Power Dissipation, Frequency Response, (Noise – optional, time permitting
11.am-11.15am Tea Break
11.15am-1.00pm Synthesis of Basic Amplifier Circuit Topologies - Basic Amplifier Circuit
Topologies: CS, CD and CG
1.00pm-2.00pm Lunch Break
2.00pm-3.30pm
Large and Small Signal DC Performance Analysis and Design of Basic
Amplifiers,Single and Differential Ended Signaling – Concept Illustration -
What really is a common mode signal?
The Basic Ideal OP-AMP and its properties - What really is virtual short and
virtual ground?
3.30pm-3.45pm Tea Break
3.45pm-5.00pm
Lab Session 2:PDK Device Characterization for Analog Model Parameters
Lab Session 3:Hands – on Tutorial on Design and Simulation of a CS Amplifier
for Large and Small Signal DC performance
Lab Session 4:Design and Simulation of the Bias Circuit for the CS amplifier:
Hands – on Tutorial
8/7/2016
9.00am-11.00am Small Signal DC Design and Simulation of the Basic Differential Pair/ Analog
Layout Design Concepts,Interpreting the Design Specifications
11.am-11.15am Tea Break
11.15am-1.00pm Design Methodology and Flow - Large Signal and Small Signal DC Design
1.00pm-2.00pm Lunch Break
2.00pm-3.30pm
Large and Small Signal DC Performance Analysis and Design of Basic
AmplifiersSingle and Differential Ended Signaling – Concept Illustration -
What really is a common mode signal?
Analog Layout Design Concepts – Importance of Device Matching in Layouts;
LDEs (Optional)
3.30pm-3.45pm Tea Break
3.45pm-5.00pm
Lab Session 5:Design and Performance Characterization of CMOS Current
Mirror (Schematic Design and Simulation)
Lab Session 6:DC Performance Characterization of the Basic CMOS
Differential Amplifier (5 – Pack OP-AMP)
9/7/2016
9.00am-11.00am Effect of the Amplifier BW limitations on Analog Signal Processing –
Illustration
11.am-11.15am Tea Break
11.15am-1.00pm Review of Transfer Functions and Frequency Response Plots;
FB concepts and Effect of FB on Frequency Response, Stability and
Compensation
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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1.00pm-2.00pm Lunch Break
2.00pm-3.30pm Small Signal AC Performance of CS and Differential Pair
3.30pm-3.45pm Tea Break
3.45pm-5.00pm
Lab Session 7:Design and Characterization of Differential Pair for Small Signal
DC and AC Performance
Design and Performance Characterization of a 7 – Pack OPAMP
10/7/2016
9.00am-11.00am Deep Understanding of ASIC Implementation
Lab Session 8:HDL Capturing and Functional Simulation of HDL codes
11.am-11.15am Tea Break
11.15am-1.00pm Lab Session 9:Synthesis of HDL Designs by introducing timing
constraintsusing Encounter RTL Compiler
1.00pm-2.00pm Lunch Break
2.00pm-3.30pm Lab Session 10:Analysis of Reports like Area, Power, Timing, Logic and Netlist
Lab Session 11:Running Physical Design using SoC Encounter
3.30pm-3.45pm Tea Break
3.45pm-4.45pm Understand the concepts of Floorplanning, Power Planning, Palcement , CTS,
Routing & Signoff
4.45pm-5.15pm Valedictory Function
Valedictory Function:
The last session was the valedictory session. The valedictory function was addressed by
Convenor and HOD of ECE Department Prof G.R.L.V.N Srinivas Raju, Coordinator Mr.
V.Srinivasa Rao. Resource Persons,shared experiences about this Workshop. Some of the
participants expressed their experiences in the workshop. The function ended with vote of
thanks by Mr.V.Srinivasa Rao, who expressed his gratitude towards all the dignitaries,
participants and all other helping hands, which contributed towards the success of the event.
GALLERY
Certificates distributed to the participants by Resource Person
SVECW Dept. of ECE ASIC Implementation Using CADENCE EDA Tools
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Certificates distributed to the participants by Coordinator